ON MC44608 Few external components reliable flexible greenline very high voltage pwm controller Datasheet

MC44608
Few External Components
Reliable and Flexible
GreenLine Very High Voltage
PWM Controller
The MC44608 is a high performance voltage mode controller
designed for off–line converters. This high voltage circuit that
integrates the start–up current source and the oscillator capacitor,
requires few external components while offering a high flexibility and
reliability.
The device also features a very high efficiency stand–by
management consisting of an effective Pulsed Mode operation. This
technique enables the reduction of the stand–by power consumption to
approximately 1W while delivering 300mW in a 150W SMPS.
• Integrated Start–Up Current Source
• Lossless Off–Line Start–Up
• Direct Off–Line Operation
• Fast Start–Up
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8
1
DIP–8
P SUFFIX
CASE 626
PIN CONNECTIONS AND
MARKING DIAGRAM
General Features
Flexibility
Duty Cycle Control
Undervoltage Lockout with Hysteresis
On Chip Oscillator Switching Frequency 40, or 75kHz
Secondary Control with Few External Components
Demag
1
8
Isense
2
7
Control Input
3
Gnd
4
44608Pxxx
AWL
YYWW
•
•
•
•
•
Vi
6
Vcc
5
Driver
Protections
•
•
•
•
•
•
AWL = Manufacturing Code
YYWW = Date Code
Maximum Duty Cycle Limitation
Cycle by Cycle Current Limitation
Demagnetization (Zero Current Detection) Protection
“Over VCC Protection” Against Open Loop
(Top View)
Programmable Low Inertia Over Voltage Protection Against Open Loop
Internal Thermal Protection
GreenLine Controller
• Pulsed Mode Techniques for a Very High Efficiency Low Power
•
•
Mode
Lossless Startup
Low dV/dT for Low EMI Radiations
 Semiconductor Components Industries, LLC, 1999
January, 2000 – Rev. 2
1
ORDERING INFORMATION
Device
Switching Package
Frequency
Shipping
MC44608P40
40kHz
Plastic
DIP–8
50 / Rail
MC44608P75
75kHz
Plastic
DIP–8
50 / Rail
Publication Order Number:
MC44608/D
MC44608
REPRESENTATIVE BLOCK DIAGRAM
Demag
Vi
1
DMG
+
–
8
UVLO2
50 mV
/20 mV
>24 mA
>120 m A
9 mA
Start–up
Source
Latched off Phase
Demag
Logic
1
Start–up Phase
Output
Start–up
Phase
200 m A Switching
Phase
0
&
OSC
Enable
Stand–by
Management
Leading Edge
Blanking
Output
2
Isense
+
–
&
&
5
Driver
4
VPWM
+
CS
–
1V
Buffer
Thermal
S
Shutdown
PWM
Latch
R Q
&
PWM
OC NOC
V CC
OUT Disable
DMG
Clock
OSC
6
OVP
UVLO1
UVLO2
2 mS
Start–up
Phase
S1
&
Stand–by
Switching Phase
Latched off
Phase
V CC
Management
4 kHz Filter
GND
Latched off Phase
&
Stand–by
S2
S3
Regulation
Block
Switching Phase
3
Control
Input
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Total Power Supply Current
ICC
30
mA
Output Supply Voltage with Respect to Ground
VCC
16
V
Vinputs
–1.0 to +16
V
Vi
500
V
600
100
mW
°C/W
Operating Junction Temperature
PD
RθJA
TJ
150
°C
Operating Ambient Temperature
TA
–25 to +85
°C
All Inputs except Vi
Line Voltage
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation at TA = 85°C
Thermal Resistance, Junction–to–Air
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MC44608
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
ROL
ROH
5.0
8.5
15
15
OUTPUT SECTION
Unit
W
Output Resistor
Sink Resistance
Source Resistance
Output Voltage Rise Time (from 3 V up to 9 V) (1)
tr
50
ns
Output Voltage Falling Edge Slew–Rate (from 9 V down to 3 V) (1)
tf
50
ns
CONTROL INPUT SECTION
Duty Cycle @ Ipin3 = 2.5 mA
d2mA
Duty Cycle @ Ipin3 = 1.0 mA
d1mA
Control Input Clamp Voltage (Switching Phase) @ Ipin3 = –1.0 mA
2.0
%
36
43
48
%
4.75
5.0
5.25
V
Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +500 mA
VLP–stby
3.4
3.9
4.3
V
Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +1.0 mA
VLP–stby
2.4
3.0
3.7
V
VCS–th
0.95
1.0
1.05
IB–cs
–1.8
ICS–stby
180
200
220
ICS–stup
180
200
220
CURRENT SENSE SECTION
Maximum Current Sense Input Threshold
Input Bias Current
Stand–By Current Sense Input Current
Start–up Phase Current Sense Input Current
Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3 V)
1.8
V
mA
mA
mA
TPLH(In/Out)
220
ns
Leading Edge Blanking Duration
MC44608P40
TLEB
480
ns
Leading Edge Blanking Duration
MC44608P75
TLEB
250
ns
Leading Edge Blanking Duration
MC44608P100
TLEB
200
ns
Leading Edge Blanking + Propagation Delay
MC44608P40
TDLY
500
680
900
ns
Leading Edge Blanking + Propagation Delay
MC44608P75
TDLY
370
470
570
ns
Leading Edge Blanking + Propagation Delay
MC44608P100
TDLY
400
ns
OSCILLATOR SECTION
Normal Operation Frequency MC44608P40
fosc
36
Normal Operation Frequency MC44608P75
fosc
68
Normal Operation Frequency MC44608P100
fosc
Maximum Duty Cycle @ f = fosc
dmax
40
44
kHz
75
82
kHz
100
78
82
kHz
86
%
OVERVOLTAGE SECTION
Quick OVP Input Filtering (Rdemag = 100 kW)
Tfilt
Propagation Delay (Idemag > Iovp to output low)
250
TPHL(In/Out)
Quick OVP Current Threshold
Protection Threshold Level on VCC
Minimum Gap Between VCC–OVP and Vstup–th
3
µs
2.0
IOVP
105
120
140
µA
VCC–OVP
14.8
15.3
15.8
V
VCC–OVP –
Vstup
1.0
NOTES:
(1) This parameter is measured using 1.0 nF connected between the output and the ground.
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ns
V
MC44608
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless otherwise
noted) (Note 1)
Characteristic
Symbol
Min
Typ
Max
Unit
Vdmg–th
30
50
69
mV
DEMAGNETIZATION DETECTION SECTION (Note 2)
Demag Comparator Threshold (Vpin1 increasing)
Demag Comparator Hysteresis (Note 3)
Hdmg
Propagation Delay (Input to Output, Low to High)
30
tPHL(In/Out)
Input Bias Current (Vdemag = 50 mV)
mV
300
ns
mA
Idem–lb
–0.6
Negative Clamp Level (Idemag = –1 mA)
Vcl–neg–dem
–0.9
–0.7
–0.4
V
Positive Clamp Level @ Idemag = 125 mA
Vcl–pos–
dem–H
2.05
2.3
2.8
V
Positive Clamp Level @ Idemag = 25 mA
Vcl–pos–
dem–L
1.4
1.7
1.9
V
OVERTEMPERATURE SECTION
Trip Level Over Temperature
Thigh
160
°C
Hysteresis
Thyst
30
°C
STAND–BY MAXIMUM CURRENT REDUCTION SECTION
Normal Mode Recovery Demag Pin Current Threshold
Idem–NM
20
25
30
mA
K FACTORS SECTION FOR PULSED MODE OPERATION
ICCS / Istup
MC44608P40
10 x K1
2.4
2.9
3.8
–
ICCS / Istup
MC44608P75
10 x K1
2.8
3.3
4.2
–
MC44608P100
10 x K1
ICCS / Istup
3.5
–
103 x K2
46
52
63
–
(Vstup – UVLO2) / (Vstup – UVLO1)
102 x Ksstup
1.8
2.2
2.6
–
(UVLO1 – UVLO2) / (Vstup – UVLO1)
102 x Ksl
106 x Ycstby
90
120
150
–
175
198
225
–
Dmgr
3.0
4.7
5.5
–
ICCL / Istup
ICS / Vcsth
Demag ratio Iovp / Idem NM
(V3 1 mA – V3 0.5 mA) / (1 mA – 0.5 mA)
R3
1800
W
Vcontrol Latch–off
V3
4.8
V
SUPPLY SECTION
Minimum Start–up Voltage
Vilow
VCC Start–up Voltage
Output Disabling VCC Voltage After Turn On
Hysteresis (Vstup–th – Vuvlo1)
Vstup–th
12.5
Vuvlo1
9.5
Hstup–uvlo1
VCC Undervoltage Lockout Voltage
Vuvlo2
Hysteresis (Vuvlo1 – Vuvlo2)
50
V
13.1
13.8
V
10
10.5
V
3.1
6.2
Huvlo1–uvlo2
6.6
V
7.0
3.4
V
V
Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and
(VCC = 9 V)
–(ICC)
7.0
9.5
12.8
mA
Switching Phase Supply Current (no load)
ICCS
2.0
2.4
–
2.6
3.2
3.4
3.6
4.0
–
mA
ICC–latch
0.3
0.5
0.68
mA
MC44608P40
MC44608P75
MC44608P100
Latched Off Phase Supply Current
dHiccup
Hiccup Mode Duty Cycle (no load)
10
%
NOTES:
(1) Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction
temperature as close to ambient as possible.
(2) This function can be inhibited by connecting pin 1 to GND.
(3) Guaranteed by design (non tested)
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MC44608
PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
Demag
The Demag pin offers 3 different functions: Zero voltage crossing detection (50mV), 24µA current detection
and 120µA current detection. The 24µA level is used to detect the secondary reconfiguration status and the
120µA level to detect an Over Voltage status called Quick OVP.
2
Isense
The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the
power MOSFET. When Isense reaches 1V, the Driver output (pin 5) is disabled. This is known as the Over
Current Protection function. A 200µA current source is flowing out of the pin 3 during the start–up phase and
during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the
sense resistor and the pin 3, thus a programmable peak current detection can be performed during the SMPS
stand–by mode.
3
Control Input
A feedback current from the secondary side of the SMPS via the opto–coupler is injected into this pin. A
resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during
the Stand–by mode.
4
Ground
5
Driver
The current and slew rate capability of this pin are suited to drive Power MOSFETs.
6
VCC
This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher
than 15V and the operating range is between 6.6V and 13V. An intermediate voltage level of 10V creates a
disabling condition called Latched Off phase.
This pin is the ground of the primary side of the SMPS.
7
This pin is to provide isolation between the Vi pin 8 and the VCC pin 6.
8
Vi
This pin can be directly connected to a 500V voltage source for start–up function of the IC. During the
Start–up phase a 9 mA current source is internally delivered to the VCC pin 6 allowing a rapid charge of the
VCC capacitor. As soon as the IC starts–up, this current source is disabled.
OPERATING DESCRIPTION
Regulation
The switch S3 is closed in Stand–by mode during the
Latched Off Phase while the switch S2 remains open. (See
section PULSED MODE DUTY CYCLE CONTROL).
The resistor Rdpulsed (Rduty cycle burst) has no effect on
the regulation process. This resistor is used to determine the
burst duty cycle described in the chapter “Pulsed Duty Cycle
Control” on page 8.
V LP–stby
V CC
Control
Input
1
S3
0
1
S2
0
Stand–by
Latched off Phase
&
3
20 W
5V
Switching Phase
PWM Latch
V dd
The MC44608 works in voltage mode. The on–time is
controlled by the PWM comparator that compares the
oscillator sawtooth with the regulation block output (refer to
the block diagram on page 2).
The PWM latch is initialized by the oscillator and is reset
by the PWM comparator or by the current sense comparator
in case of an over current. This configuration ensures that
only a single pulse appears at the circuit output during an
oscillator cycle.
PWM
Regulation Comparator
Output
4 kHz
Filter
1.6 V
Figure 1. Regulator
Current Sense
The pin 3 senses the feedback current provided by the opto
coupler. During the switching phase the switch S2 is closed
and the shunt regulator is accessible by the pin 3. The shunt
regulator voltage is typically 5V. The dynamic resistance of
the shunt regulator represented by the zener diode is 20W.
The gain of the Control input is given on Figure 10 which
shows the duty cycle as a function of the current injected into
the pin 3.
A 4kHz filter network is inserted between the shunt
regulator and the PWM comparator to cancel the high
frequency residual noise.
The inductor current is converted to a positive voltage by
inserting a ground reference sense resistor RSense in series
with the power switch.
The maximum current sense threshold is fixed at 1V. The
peak current is given by the following equation:
Ipk max
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1
+ Rsense
(A)
(W )
MC44608
Oscillator Buffer Output
In stand–by mode, this current can be lowered as due to the
activation of a 200µA current source:
cs(kW) 0, 2) (A)
Ipk
+ * (RRsense
max *stby
(W )
R Q
DMG
S
1
Demag
200 m A
1
DMG
STAND–BY
&
0
&
50/20 mV
> 24 m A
>120 m A
START–UP
1
+
–
Idemag
Switching Phase
Idemag
Current Mirror
Isense
Rcs
L.E.B.
2
Overcurrent
Comparator
+
Figure 3. Demagnetization Block
OC
This function can be inhibited by grounding it but in this
case, the quick and programmable OVP is also disabled.
–
Rsense
1V
Oscillator
The MC44608 contains a fixed frequency oscillator. It is
built around a fixed value capacitor CT succesively charged
and discharged by two distinct current sources ICH and
IDCH. The window comparator senses the CT voltage value
and activates the sources when the voltage is reaching the
2.4V/4V levels.
Figure 2. Current Sense
The current sense input consists of a filter (6kW, 4pF) and
of a leading edge blanking. Thanks to that, this pin is not
sensitive to the power switch turn on noise and spikes and
practically in most applications, no filtering network is
required to sense the current.
Finally, this pin is used:
– as a protection against over currents (Isense > I)
– as a reduction of the peak current during a Pulsed Mode
switching phase.
The overcurrent propagation delay is reduced by
producing a sharp output turn off (high slew rate). This
results in an abrupt output turn off in the event of an over
current and in the majority of the pulsed mode switching
sequense.
ICH
DMG
from Demag
logic block
OSC
SCH
&
4V
2.4 V
Window
+ comp
Clock
–
SDCH
IDCH
CT
Demagnetization Section
The MC44608 demagnetization detection consists of a
comparator designed to compare the VCC winding voltage
to a reference that is typically equal to 50mV.
This reference is chosen low to increase effectiveness of
the demagnetization detection even during start–up.
A latch is incorporated to turn the demagnetization block
output into a low level as soon as a voltage less than 50 mV
is detected, and to keep it in this state until a new pulse is
generated on the output. This avoids any ringing on the input
signal which may alter the demagnetization detection.
For a higher safety, the demagnetization block output is
also directly connected to the output, which is disabled
during the demagnetization phase.
The demagnetization pin is also used for the quick,
programmable OVP. In fact, the demagnetization input
current is sensed so that the circuit output is latched off when
this current is detected as higher than 120µA.
Figure 4. Oscillator Block
The complete demagnetization status DMG is used to
inhibit the recharge of the CT capacitor. Thus in case of
incomplete transformer demagnetization the next switching
cycle is postpone until the DMG signal appears. The
oscillator remains at 2.4V corresponding to the sawtooth
valley voltage. In this way the SMPS is working in the so
called SOPS mode (Self Oscillating Power Supply). In that
case the effective switching frequency is variable and no
longer depends on the oscillator timing but on the external
working conditions (Refer to DMG signal in the Figure 5).
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MC44608
OSC
4V
V
CC
13 V
Vcont
2.4 V
10 V
Clock
6.5 V
DMG
Start–up
Phase
Latched off
Phase
Switching
Phase
Iprim
Figure 6. Hiccup Mode
Figure 5.
In case of the hiccup mode, the duty cycle of the switching
phase is in the range of 10%.
The OSC and Clock signals are provided according to the
Figure 5. The Clock signals correspond to the CT capacitor
discharge. The bottom curve represents the current flowing
in the sense resistor Rcs. It starts from zero and stops when
the sawtooth value is equal to the control voltage Vcont. In
this way the SMPS is regulated with a voltage mode control.
Mode Transition
The LW latch Figure 7 is the memory of the working status
at the end of every switching sequence.
Two different cases must be considered for the logic at the
termination of the SWITCHING PHASE:
1. No Over Current was observed
2. An Over Current was observed
These 2 cases are corresponding to the signal labelled
NOC in case of “No Over Current” and “OC” in case of Over
Current. So the effective working status at the end of the ON
time memorized in LW corresponds to Q=1 for no over
current and Q=0 for over current.
This sequence is repeated during the Switching phase.
Several events can occur:
1. SMPS switch OFF
2. SMPS output overload
3. Transition from Normal to Pulsed Mode
4. Transition from Pulsed Mode to Normal Mode
Overvoltage Protection
The MC44608 offers two OVP functions:
– a fixed function that detects when VCC is higher than
15.4V
– a programmable function that uses the demag pin. The
current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120µA). Thus this
OVP is quicker as it is not impacted by the VCC inertia and
is called QOVP.
In both cases, once an OVP condition is detected, the
output is latched off until a new circuit START–UP.
Start–up Management
The Vi pin 8 is directly connected to the HV DC rail Vin.
This high voltage current source is internally connected to
the VCC pin and thus is used to charge the VCC capacitor. The
VCC capacitor charge period corresponds to the Start–up
phase. When the VCC voltage reaches 13V, the high voltage
9mA current source is disabled and the device starts
working. The device enters into the switching phase.
It is to be noticed that the maximum rating of the Vi pin 8
is 700V. ESD protection circuitry is not currently added to
this pin due to size limitations and technology constraints.
Protection is limited by the drain–substrate junction in
avalanche breakdown. To help increase the application
safety against high voltage spike on that pin it is possible to
insert a small wattage 1kW series resistor between the Vin
rail and pin 8.
The Figure 6 shows the VCC voltage evolution in case of
no external current source providing current into the VCC
pin during the switching phase. This case can be
encountered in SMPS when the self supply through an
auxiliary winding is not present (strong overload on the
SMPS output for example). The Figure 16 also depicts this
working configuration.
Latched Off
Phase
VPWM
OUT
&
NOC
OC
S
Q
R
LEB out
1V
&
LW
Q
+
CS
–
&
S Q Stand–by
&
Mode
R1
R2
S1
Switch
Start–up Idemag Switching Start–up
Phase > 24 m A Phase Phase
Figure 7. Transition Logic
• 1. SMPS SWITCH OFF
When the mains is switched OFF, so long as the bulk
electrolithic bulk capacitor provides energy to the SMPS,
the controller remains in the switching phase. Then the peak
current reaches its maximum peak value, the switching
frequency decreases and all the secondary voltages are
reduced. The VCC voltage is also reduced. When VCC is
equal to 10V, the SMPS stops working.
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MC44608
• 2. Overload
according to the equation of the current sense section, page
5. The C.S. clamping level depends on the power to be
delivered to the load during the SMPS stand–by mode.
Every switching sequence ON/OFF is terminated by an OC
as long as the secondary Zener diode voltage has not been
reached. When the Zener voltage is reached the ON cycle is
terminated by a true PWM action. The proper SWITCHING
PHASE termination must correspond to a NOC condition.
The LW latch stores this NOC status.
The LATCHED OFF PHASE: The MODE latch is set.
The START–UP PHASE is similar to the Overload Mode.
The MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The Stand–by signal is
validated and the 200µA is sourced out of the Current Sense
pin 2.
In the hiccup mode the 3 distinct phases are described as
follows (refer to Figure 6):
The SWITCHING PHASE: The SMPS output is low and
the regulation block reacts by increasing the ON time (dmax
= 80%). The OC is reached at the end of every switching
cycle. The LW latch (Figure 7) is reset before the VPWM
signal appears. The SMPS output voltage is low. The VCC
voltage cannot be maintained at a normal level as the
auxiliary winding provides a voltage which is also reduced
in a ratio similar to the one on the output (i.e. Vout nominal
/ Vout short–circuit). Consequently the VCC voltage is
reduced at an operating rate given by the combination VCC
capacitor value together with the ICC working consumption
(3.2mA) according to the equation 2. When VCC crosses
10V the WORKING PHASE gets terminated. The LW latch
remains in the reset status.
The LATCHED–OFF PHASE: The VCC capacitor
voltage continues to drop. When it reaches 6.5V this phase
is terminated. Its duration is governed by equation 3.
The START–UP PHASE is reinitiated. The high voltage
start–up current source (–ICC1 = 9mA) is activated and the
MODE latch is reset. The VCC voltage ramps up according
to the equation 1. When it reaches 13V, the IC enters into the
SWITCHING PHASE.
The NEXT SWITCHING PHASE: The high voltage
current source is inhibited, the MODE latch (Q=0) activates
the NORMAL mode of operation. Figure 2 shows that no
current is injected out pin 2. The over current sense level
corresponds to 1V.
As long as the overload is present, this sequence repeats.
The SWITCHING PHASE duty cycle is in the range of 10%.
• 4. Transition from Stand–by to Normal
The secondary reconfiguration is removed. The
regulation on the low voltage secondary rail can no longer
be achieved, thus at the end of the SWITCHING PHASE, no
PWM condition can be encountered. The LW latch is reset.
At the next WORKING PHASE a NORMAL mode status
takes place.
In order to become independent of the recovery time
constant on the secondary side of the SMPS an additional
reset input R2 is provided on the MODE latch. The condition
Idemag<24µA corresponds to the activation of the
secondary reconfiguration status. The R2 reset insures a
return into the NORMAL mode following the first
START–UP PHASE.
Pulsed Mode Duty Cycle Control
During the sleep mode of the SMPS the switch S3 is
closed and the control input pin 3 is connected to a 4.6V
voltage source thru a 500W resistor. The discharge rate of the
VCC capacitor is given by ICC–latch (device consumption
during the LATCHED OFF phase) in addition to the current
drawn out of the pin 3. Connecting a resistor between the Pin
3 and GND (RDPULSED) a programmable current is drawn
from the VCC through pin 3. The duration of the LATCHED
OFF phase is impacted by the presence of the resistor
RDPULSED. The equation 3 shows the relation to the pin 3
current.
• 3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer
to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL
mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS stand–by mode all the SMPS outputs are
lowered except for the low voltage output that supply the
wake–up circuit located at the isolated side of the power
supply. In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.
The secondary reconfiguration status can be detected on
the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the
Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The VCC self–powering is no
longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.
In the SMPS stand–by mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload
mode. The current sense clamping level is reduced
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective
behavior during the PULSED MODE operation. The
equations 6, 7, and 8 contain K, Y, and D factors. These
factors are combinations of measured parameters. They
appear in the parameter section “Kfactors for pulsed mode
operation” page 4. In equations 3 through 8 the pin 3 current
is the current defined in the above section “Pulsed Mode
Duty Cycle Control”.
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MC44608
EQUATION 1
Start–up Phase Duration:
t start–up
+
C
* UVLO2)
(Vstup
I stup
Vcc
where: Istup is the start–up current flowing through VCC pin
CVcc is the VCC capacitor value
EQUATION 2
Switching Phase Duration:
t
+
switch
C
*
(Vstup
UVLO1)
I
I
ccS
G
Vcc
)
where: IccS is the no load circuit consumption in switching phase
IG is the current consumed by the Power Switch
EQUATION 3
Latched–off Phase Duration:
t
C
Vcc
+
latched*off
(UVLO1
I
ccL
* UVLO2)
) Ipin3
where: IccL is the latched off phase consumption
Ipin3 is the current drawn from pin3 adding a resistor
EQUATION 4
Burst Mode Duty Cycle:
d
BM
+t
t
start*up ) t switch ) t latched*off
switch
EQUATION 5
C
d
+C
BM
EQUATION 6
d
BM
+
1
*
(V
UVLO2)
stup
I
stup
Vcc
)
ǒ
k
ń
S Stup
I
)
)
I
ccS G
I
stup
C
Vcc
Vcc
Ǔǒ
*
(V
UVLO1)
stup
I
I
ccS G
(V
UVLO1)
stup
I
I
ccS G
)
*
)
1
)
k
ń
S L
)
C
Ǔ
) IG
I
)I
ccL pin3
I
ccS
where: kS/Stup = (Vstup – UVLO2)/(Vstup – UVLO1)
kS/L = (UVLO1 – UVLO2)/(Vstup – UVLO1)
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9
*
)
I
ccL pin3
(UVLO1 UVLO2)
Vcc
I
MC44608
ǒ ǒ
EQUATION 7
d
BM
ȡȧ
Ȣ
+
1
)
I
ǓǓȣȧȤ
1
)
I
ccS G
I
stup
k
)
SńStup
k
ń
I
S L
stup
I
I
ccL
pin3
)
EQUATION 8
d
BM
+
1
ȡȧ
)ȥ
ȧȢ
ȡȧ
ȧȧ ń
Ȣ
ǒ Ǔ
)I G
I
k1
k
stup
1
S Stup
) (kSńL
)
k2
ǒǓ
ȣȧȣȧ
ȧȧȦȧ
ȤȤ
1
)
I
pin3
I
stup
where: k1 = Iccs/Istup
k2 = IccL/Istup
kS/Stup = (Vstup–UVLO2)/(Vstup–UVLO1)
kS/L = (UVLO1–UVLO2)/(Vstup–UVLO1)
PULSED MODE CURRENT SENSE CLAMPING LEVEL
Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the
SMPS stand–by mode.
EQUATION 9
Ipk
stby
+ Vcs–th *R(Rcs
I cs)
S
where: Vcs–th is the CS comparator threshold
Ics is the CS internal current source
RS is the sensing resistor
Rcs is the resistor connected between pin 2 and RS
EQUATION 10
Ipk
stby
+ Vcs–th
1
*
ǒ
Ǔ
Ics
V
cs–th
R cs
R
S
EQUATION 11
Ipk
+ Vcs–th
stby
1
* (Rcs
)
Y
cs–stby
R
S
where: Ycs–stby = Ics/Vcs–th
Taking into account the circuit propagation delay (dtcs) and the Power Switch reaction time (dtps):
EQUATION 12
Ipk
+
stby
ƪ
1
V
cs–th
* (Rcs
Y
)
cs–stby
R
S
ƫ
(dt cs
) Vin
) dtps)
Lp
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MC44608
60
5.08
5.07
50
5.06
t_rise
5.05
Vpin3 (V)
Time (nS)
85° C
5.04
40
t_fall
30
5.03
25° C
5.02
5.01
–25° C
5.00
20
4.99
10
10
11
12
13
14
4.98
0.5
15
1
1.5
2
2.5
Current Injected in Pin 3 (mA)
Pin6 VCC Voltage (V)
Figure 8. Output Switching Speed
Figure 11. Vpin3 During the Working Period
5.0
79.0
4.5
85° C
77.0
75.0
25° C
Vpin3 Voltage (V)
Frequency
–25° C
4.0
–25° C
73.0
71.0
69.0
3.5
25° C
3.0
85° C
2.5
2.0
67.0
65.0
10
11
12
13
14
1.5
–1.6
15
–1.4
–1.2
VCC Voltage (V)
80
4.60
70
4.40
60
4.20
Pin6 Current (mA)
Switching Duty Cycle (%)
4.80
85° C
–25° C
30
25° C
10
0.5
1.0
–.04
–.02
0.0
–25° C
4.00
25° C
3.80
3.60
85° C
3.40
20
0
0.0
–.06
Figure 12. Vpin3 During the Latched Off Period
90
40
–.08
Current Injected in Pin 3 (mA)
Figure 9. Frequency Stability
50
–1.0
3.20
1.5
2.0
3.00
10
2.5
Current Injected in Pin3 (mA)
11
12
13
14
15
Pin6 VCC Voltage (V)
Figure 10. Duty Cycle Control
Figure 13. Device Consumption when Switching
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11
MC44608
Figure 14. High Voltage Current Source
Figure 15. Overload Burst Mode
11.00
12.00
–25° C
11.00
Switching Duty Cycle (%)
10.00
–Icc (mA)
9.00
8.00
25° C
7.00
85° C
6.00
–25° C
10.00
9.00
25° C
8.00
85° C
7.00
6.00
5.00
5.00
0
100
200
300
400
500
0
100
Vi Pin8 Voltage (Vi)
200
300
Vi Pin Voltage (V)
Figure 16. Hiccup Mode Waveforms
The data in Figure 15 corresponds to the waveform in
Figure 16. The Figure 16 shows VCC, ICC, Isense (pin 2) and
Vout (pin 5). Vout (pin 5) in fact shows the envelope of the
output switching pulses. This mode corresponds to an
overload condition.
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12
400
500
MC44608
The Figure 18 represents a complete power supply using the secondary reconfiguration.
The specification is as follows:
Input source:
85Vac to 265Vac
3 Outputs
112V / 0.45A
16V / 1.5A
8V / 1A
Output power
80W
Stand–by mode
@ Pout = 300mW, 1.3W
R F6
47288900
FI
C20
2N2FY
WIDE
C1
AINS 100 nF
C11
220 pF
500 V
RFI
FILTER
R16
4.7 k W
4 kV
C3
1 nF
D1, D2, D3, D4
1N5404
C5
220 m F
400 V
C4
1 nF
100 k W
6
2
3
4
+
7
6
5
VCC
1
1
D9
MR852
11
2 10
C8
100 nF
3.9 k W
R3
0.27
2
C14
1000
35 V
mF
C16
120 pF
D13
1N4148
D10
MR852
8
R17
2.2 k W
5W
R4
DZ1
MCR22–6
R19
18 k W
D14
MR856
MTP6N60E
3
16 V/1.5 A
3
8 V/1 A
C9
470 pF
630 V
Post
Reg.
C15 +
1000 m F
16 V
mP
9
W
R21
47
W
R9
100 k W
OPT1
R11
4.7 k W
R12
1 kW
DZ3
10 V
C19
33 nF
Figure 17. Typical Application
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13
C18
100 nF
R10
10 k W
ON
DZ2
TL431CLP
J3
1
1N4934
7
R2
10 W
2
D12
+
C7
22 m F
16 V
C13
100 nF
C17
120 pF
R7
47 k W
D7
1N4148
8
MC44608P75
1
12
R1
22 k W
5W
C6
47 nF
630 V
D6
MR856
R5
D5
1N4007
112 V/0.45 A
C12 +
47 m F
250 V
+
Isense
D18
MR856
14
R8
2.4 k W
OFF
ON = Normal Mode
OFF = Pulsed Mode
J4
MC44608
The secondary reconfiguration is activated by the µP
through the switch. The dV/dt appearing on the high voltage
winding (pins 14 of the transformer) at every TMOS switch
off, produces a current spike through the series RC network
R7, C17. According to the switch position this spike is either
absorbed by the ground (switch closed) or flows into the
thyristor gate (switch open) thus firing the MCR22–6. The
closed position of the switch corresponds to the Pulsed
Mode activation. In this secondary side SMPS status the
high voltage winding (12–14) is connected through D12 and
DZ1 to the 8V low voltage secondary rail. The voltages
applied to the secondary windings 12–14, 10–11 and 6–7
(Vaux) are thus divided by ratio N12–14 / N9–8 (number of
turns of the winding 12–14 over number of turns of the
winding 9–8). In this reconfigured status all the secondary
voltages are lowered except the 8V one. The regulation
during every pulsed or burst is performed by the zener diode
DZ3 which value has to be choosen higher than the normal
mode regulation level. This working mode creates a voltage
ripple on the 8V rail which generally must be post regulated
for the microProcessor supply.
Figure 18. SMPS Pulsed Mode
is the result of the 200µA current source activated during the
start–up phase and also during the working phase which
flows through the R4 resistor. The used high resolution
mode of the oscilloscope does not allow to show the
effective ton current flowing in the sensing resistor R11.
The Figure 18 shows the SMPS behavior while working
in the reconfigured mode. The top curve represents the VCC
voltage (pin 6 of the MC44608). The middle curve
represents the 8V rail. The regulation is taking place at
11.68V. On the bottom curve the pin 2 voltage is shown. This
voltage represents the current sense signal. The pin 2 voltage
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14
MC44608
PACKAGE DIMENSIONS
DIP–8
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
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15
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
AC IN
DC + IN
DC – IN
AC IN
GROUND
OUTPUT
AUXILIARY
VCC
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
MC44608
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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16
MC44608/D