MCNIX MX25L1635EM2I10G 16m-bit [x 1/x 2/x 4] cmos serial flash Datasheet

MX25L1635E
MX25L1635E
DATASHEET
P/N: PM1553
1
REV. 1.6, DEC. 12, 2012
MX25L1635E
Content
FEATURES................................................................................................................................................................... 5
General............................................................................................................................................................... 5
Performance........................................................................................................................................................ 5
Software Features............................................................................................................................................... 5
Hardware Features............................................................................................................................................. 6
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Feature Comparison............................................................................................................. 7
PIN CONFIGURATIONS .............................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM........................................................................................................................................................ 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes........................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11
Memory Organization................................................................................................................................................ 12
Table 4. Memory Organization (16Mb)............................................................................................................. 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1. Serial Modes Supported.................................................................................................................... 13
COMMAND DESCRIPTION........................................................................................................................................ 14
Table 5. Command Set...................................................................................................................................... 14
(1) Write Enable (WREN).................................................................................................................................. 15
(2) Write Disable (WRDI)................................................................................................................................... 15
(3) Read Identification (RDID)........................................................................................................................... 15
(4) Read Status Register (RDSR)..................................................................................................................... 16
(5) Write Status Register (WRSR)..................................................................................................................... 17
Table 6. Protection Modes................................................................................................................................. 17
(6) Read Data Bytes (READ)............................................................................................................................ 18
(7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 18
(8) 2 x I/O Read Mode (2READ)....................................................................................................................... 18
(9) 4 x I/O Read Mode (4READ)....................................................................................................................... 19
(10) Sector Erase (SE)...................................................................................................................................... 19
(11) Block Erase (BE)........................................................................................................................................ 20
(12) Chip Erase (CE)......................................................................................................................................... 20
(13) Page Program (PP)................................................................................................................................... 20
(14) 4 x I/O Page Program (4PP)...................................................................................................................... 21
(15) Deep Power-down (DP)............................................................................................................................. 21
(16) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 21
(17) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................... 22
P/N: PM1553
2
REV. 1.6, DEC. 12, 2012
MX25L1635E
Table 7. ID Definitions ...................................................................................................................................... 22
(18) Enter Secured OTP (ENSO)...................................................................................................................... 23
(19) Exit Secured OTP (EXSO)......................................................................................................................... 23
(20) Read Security Register (RDSCUR)........................................................................................................... 23
(21) Write Security Register (WRSCUR)........................................................................................................... 24
Table 8. Security Register Definition................................................................................................................. 24
POWER-ON STATE.................................................................................................................................................... 25
ELECTRICAL SPECIFICATIONS............................................................................................................................... 26
Absolute Maximum Ratings ............................................................................................................................. 26
Figure 2. Maximum Negative Overshoot Waveform......................................................................................... 26
Capacitance...................................................................................................................................................... 26
Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 26
Figure 4. Input Test Waveforms and Measurement Level................................................................................. 27
Figure 5. Output Loading.................................................................................................................................. 27
Table 9. DC Characteristics............................................................................................................................... 28
Table 10. AC Characteristics............................................................................................................................. 29
Timing Analysis......................................................................................................................................................... 30
Figure 6. Serial Input Timing............................................................................................................................. 30
Figure 7. Output Timing..................................................................................................................................... 30
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1.................................................. 31
Figure 9. Write Enable (WREN) Sequence (Command 06).............................................................................. 31
Figure 10. Write Disable (WRDI) Sequence (Command 04)............................................................................. 31
Figure 11. Read Identification (RDID) Sequence (Command 9F)..................................................................... 32
Figure 12. Read Status Register (RDSR) Sequence (Command 05)............................................................... 32
Figure 13. Write Status Register (WRSR) Sequence (Command 01).............................................................. 32
Figure 14. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 33
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 33
Figure 16. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 34
Figure 17. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 34
Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB)............................................ 35
Figure 19. Page Program (PP) Sequence (Command 02).............................................................................. 36
Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 36
Figure 21. Sector Erase (SE) Sequence (Command 20)................................................................................. 37
Figure 22. Block Erase (BE) Sequence (Command D8).................................................................................. 37
Figure 23. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 37
Figure 24. Deep Power-down (DP) Sequence (Command B9)....................................................................... 38
Figure 25. Read Electronic Signature (RES) Sequence (Command AB)......................................................... 38
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 38
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)......... 39
Figure 28. Power-up Timing.............................................................................................................................. 40
Table 11. Power-Up Timing .............................................................................................................................. 40
P/N: PM1553
3
REV. 1.6, DEC. 12, 2012
MX25L1635E
Initial Delivery State.......................................................................................................................................... 40
OPERATING CONDITIONS........................................................................................................................................ 41
Figure 29. AC Timing at Device Power-Up........................................................................................................ 41
Figure 30. Power-Down Sequence................................................................................................................... 42
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 43
DATA RETENTION..................................................................................................................................................... 43
LATCH-UP CHARACTERISTICS............................................................................................................................... 43
ORDERING INFORMATION....................................................................................................................................... 44
PART NAME DESCRIPTION...................................................................................................................................... 45
PACKAGE INFORMATION......................................................................................................................................... 46
REVISION HISTORY .................................................................................................................................................. 47
P/N: PM1553
4
REV. 1.6, DEC. 12, 2012
MX25L1635E
16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
FEATURES
General
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits structure or 4,194,304 x 4 bits structure
• 512 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
Performance
• High Performance
- Fast read
- 1 I/O: 108MHz with 8 dummy cycles
- 2 I/O: 80MHz (Vcc=2.7V~3.6V); 104MHz (Vcc=3.0V~3.6V) with 4 dummy cycles
- 4 I/O: 108MHz with 6 dummy cycles
- Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 6s(typ.) /chip
• Low Power Consumption
- Low active read current: 25mA(max.) at 108MHz and 10mA(max.) at 50MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (typ.); 50uA (max.)
- Deep power down current: 3uA (typ.); 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
Software Features
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 4K-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- All REMS, REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
P/N: PM1553
5
REV. 1.6, DEC. 12, 2012
MX25L1635E
Hardware Features
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• NC/SIO3
- NC pin or serial data Input/Output for 4 x I/O read mode
• PACKAGE
- 8-pin SOP (200mil)
- All devices are RoHS Compliant
P/N: PM1553
6
REV. 1.6, DEC. 12, 2012
MX25L1635E
GENERAL DESCRIPTION
The MX25L1635E are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it
is in four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1635E feature
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input
and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1
pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25L1635E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte),
or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Secured OTP and Block Protection, please see security feature and write status register section for more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 50uA DC current.
Table 1. Additional Feature Comparison
Protection and
Security
Additional
Features Flexible
Block
4K-bit
Part
Protection secured
Name
(BP0OTP
BP3)
MX25L1635E
P/N: PM1553
V
V
Read Performance
Identifier
1 I/O
Read
(108
MHz)
2 I/O
Read
(80MHz;
104MHz)
4 I/O
Read
(108
MHz)
V
V
V
RES
REMS
REMS2
REMS4
RDID
(command: (command: (command: (command: (command:
AB hex)
90 hex)
EF hex)
DF hex)
9F hex)
25 (hex)
7
C2 25 (hex) C2 25 (hex)
(if ADD=0) (if ADD=0)
C2 25
C2 25 15
(hex)
(hex)
(if ADD=0)
REV. 1.6, DEC. 12, 2012
MX25L1635E
PIN CONFIGURATIONS
PIN DESCRIPTION
8-PIN SOP (200mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
SYMBOL
CS#
8
7
6
5
VCC
NC/SIO3
SCLK
SI/SIO0
SI/SIO0
SO/SIO1
SCLK
WP#/SIO2
NC/SIO3
VCC
GND
P/N: PM1553
8
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O) /
Serial Data Input & Output (for 2xI/O
or 4xI/O read mode)
Serial Data Output (for 1 x I/O)
Serial Data Input & Output (for 2xI/O
or 4xI/O read mode)
Clock Input
Write protection: connect to GND or
Serial Data Input & Output (for 4xI/O
read mode)
NC pin (Not connect) or Serial Data
Input & Output (for 4xI/O read mode)
+ 3.3V Power Supply
Ground
REV. 1.6, DEC. 12, 2012
MX25L1635E
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SRAM
Buffer
CS#
WP#/SIO2
NC/SIO3
SCLK
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
SO/SIO1
P/N: PM1553
Sense
Amplifier
9
REV. 1.6, DEC. 12, 2012
MX25L1635E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Page Program (4PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
•
Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Table 2. Protected Area Sizes", the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "Table 2. Protected Area Sizes".
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into four I/O read mode, the feature of HPM will be disabled.
P/N: PM1553
10
REV. 1.6, DEC. 12, 2012
MX25L1635E
Table 2. Protected Area Sizes
Status bit
Protect Level
BP3
BP2
BP1
BP0
No.
16Mb
0
0
0
0
0
(none)
0
0
0
1
1
(1block, protected block 31th)
0
0
1
0
2
(2blocks, protected block 30th-31th)
0
0
1
1
3
(4blocks, protected block 28th-31th)
0
1
0
0
4
(8blocks, protected block 24th-31th)
0
1
0
1
5
(16blocks, protected block 16th-31th)
0
1
1
0
6
(32blocks, protected all)
0
1
1
1
7
(32blocks, protected all)
1
0
0
0
8
(32blocks, protected all)
1
0
0
1
9
(32blocks, protected all)
1
0
1
0
10
(16blocks, protected block 0th-15th)
1
0
1
1
11
(24blocks, protected block 0th-23th)
1
1
0
0
12
(28blocks, protected block 0th-27th)
1
1
0
1
13
(30blocks, protected block 0th-29th)
1
1
1
0
14
(31blocks, protected block 0th-30th)
1
1
1
1
15
(32blocks, protected all)
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to "Table 3. 4K-bit Secured OTP Definition".
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
xxx000~xxx00F
128-bit
ESN (electrical serial number)
xxx010~xxx1FF
3968-bit
N/A
P/N: PM1553
11
Customer Lock
Determined by customer
REV. 1.6, DEC. 12, 2012
MX25L1635E
Memory Organization
Block
Table 4. Memory Organization (16Mb)
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P/N: PM1553
Sector
511
:
496
495
:
480
479
:
464
463
:
448
447
:
432
431
:
416
415
:
400
399
:
384
383
:
368
367
:
352
351
:
336
335
:
320
319
:
304
303
:
288
287
:
272
271
:
256
Address Range
1FF000h
1FFFFFh
:
:
1F0000h
1F0FFFh
1EF000h
1EFFFFh
:
:
1E0000h
1E0FFFh
1DF000h
1DFFFFh
:
:
1D0000h
1D0FFFh
1CF000h
1CFFFFh
:
:
1C0000h
1C0FFFh
1BF000h
1BFFFFh
:
:
1B0000h
1B0FFFh
1AF000h
1AFFFFh
:
:
1A0000h
1A0FFFh
19F000h
19FFFFh
:
:
190000h
190FFFh
18F000h
18FFFFh
:
:
180000h
180FFFh
17F000h
17FFFFh
:
:
170000h
170FFFh
16F000h
16FFFFh
:
:
160000h
160FFFh
15F000h
15FFFFh
:
:
150000h
150FFFh
14F000h
14FFFFh
:
:
140000h
140FFFh
13F000h
13FFFFh
:
:
130000h
130FFFh
12F000h
12FFFFh
:
:
120000h
120FFFh
11F000h
11FFFFh
:
:
110000h
110FFFh
10F000h
10FFFFh
:
:
100000h
100FFFh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
12
Sector
255
:
240
239
:
224
223
:
208
207
:
192
191
:
176
175
:
160
159
:
144
143
:
128
127
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
2
1
0
Address Range
0FF000h
0FFFFFh
:
:
0F0000h
0F0FFFh
0EF000h
0EFFFFh
:
:
0E0000h
0E0FFFh
0DF000h
0DFFFFh
:
:
0D0000h
0D0FFFh
0CF000h
0CFFFFh
:
:
0C0000h
0C0FFFh
0BF000h
0BFFFFh
:
:
0B0000h
0B0FFFh
0AF000h
0AFFFFh
:
:
0A0000h
0A0FFFh
09F000h
09FFFFh
:
:
090000h
090FFFh
08F000h
08FFFFh
:
:
080000h
080FFFh
07F000h
07FFFFh
:
:
070000h
070FFFh
06F000h
06FFFFh
:
:
060000h
060FFFh
05F000h
05FFFFh
:
:
050000h
050FFFh
04F000h
04FFFFh
:
:
040000h
040FFFh
03F000h
03FFFFh
:
:
030000h
030FFFh
02F000h
02FFFFh
:
:
020000h
020FFFh
01F000h
01FFFFh
:
:
010000h
010FFFh
00F000h
00FFFFh
:
:
002000h
002FFFh
001000h
001FFFh
000000h
000FFFh
REV. 1.6, DEC. 12, 2012
MX25L1635E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, all SO pins of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ, RES, REMS,
REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data
being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP,
4PP, CP, RDP, DP, ENSO, EXSO, and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1553
13
REV. 1.6, DEC. 12, 2012
MX25L1635E
COMMAND DESCRIPTION
Table 5. Command Set
Command (byte)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Command (byte)
1st byte
2nd byte
3rd byte
4th byte
Action
4READ
RDSR
WRSR
FAST READ 2READ
WRDI (write RDID (read
READ
(4 x I/O read
(read status (write status
(fast read (2 x I/O read
disable) identification)
(read data)
command)
register)
register)
data)
command)
Note1
06 (hex)
04 (hex)
9F (hex)
05 (hex)
01 (hex)
03 (hex)
0B (hex)
BB (hex)
EB (hex)
AD1
ADD(4) &
Values
AD1
ADD(2)
(A23-A16)
Dummy(4)
AD2
ADD(2) &
AD2
Dummy(4)
(A15-A8)
Dummy(2)
AD3
AD3
(A7-A0)
Dummy
sets the
resets the
outputs
to read out to write new n bytes n bytes read n bytes
n bytes
(WEL) write (WEL) write
JEDEC
the values values of
read out
out until
read out
read out
enable latch enable latch ID: 1-byte of the status the status until CS# CS# goes by 2 x I/O by 4 x I/O
bit
bit
Manufacturer register
register
goes high
high
until CS#
until CS#
ID & 2-byte
goes high goes high
Device ID
WREN
(write
enable)
4PP (quad
page
program)
38 (hex)
AD1
SE (sector
erase)
20 (hex)
AD1
AD2
AD3
quad input to to erase the
program the
selected
selected page
sector
REMS (read
Commelectronic
and (byte) manufacturer
& device ID)
1st byte
90 (hex)
2nd byte
X
3rd byte
X
4th byte ADD (Note 2)
output the
Manufacturer
ID & Device
ID
Action
BE (block
erase)
CE (chip
erase)
PP (page
program)
D8 (hex) 60 or C7 (hex)
02 (hex)
AD1
AD1
AD2
AD2
AD3
AD3
to erase the
to erase
to program
selected
whole chip the selected
block
page
RDP (Release
RES (read
from deep
electronic ID)
power down)
B9 (hex)
AB (hex)
AB (hex)
X
X
X
enters deep release from to read out
power down deep power 1-byte Device
mode
down mode
ID
DP (Deep
power down)
REMS2 (read REMS4 (read
RDSCUR
WRSCUR
ENSO (enter EXSO (exit
Release Read
ID for 2x I/O ID for 4x I/O
(read security (write security
secured OTP) secured OTP)
Enhanced
mode)
mode)
register)
register)
EF (hex)
DF (hex)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
FF (hex)
X
X
X
X
X
X
ADD (Note 2) ADD (Note 2)
X
output the
output the
to enter
to set the
All these
to exit the 4K- to read value
Manufacturer Manufacturer the 4K-bit
of security lock-down bit commends
bit secured
ID & Device ID & Device secured OTP OTP mode
register
as "1" (once FFh, 00h, AAh
ID
ID
lock-down,
or 55h will
mode
cannot be
escape the
update)
performance
enhance
mode
Note 1: The count base is 4-bit for ADD(4) and Dummy(4) because of 4 x I/O. And the MSB is on SI/SIO1,
WP#/SIO2 which is different from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
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MX25L1635E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the
WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to "Figure 9. Write Enable (WREN) Sequence (Command 06)")
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to "Figure 10. Write Disable (WRDI) Sequence (Command 04)")
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Quad Page Program (4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. Macronix
Manufacturer ID is C2(hex), the memory type ID is 25(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as "Table 7. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→ 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to "Figure 11. Read
Identification (RDID) Sequence (Command 9F)".)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1553
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REV. 1.6, DEC. 12, 2012
MX25L1635E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to "Figure 12. Read Status Register (RDSR) Sequence (Command 05)")
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable
WP# or is set to "1" to enable Quad SIO2 and SIO3. Once the system goes into Quad I/O mode, the feature of HPM
will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, which is set to "0" (factory default). The
SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The
hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and
Block Protect bits (BP3, BP2, BP1, BP0) are read only.
Status Register
bit7
bit6
SRWD (status
register write
protect)
QE
(Quad
Enable)
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
1=Quad
1=status
Enable
register write
(note 1)
(note 1)
0=not Quad
disable
Enable
Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
Factory
Factory
Factory
Factory
default=0
default=0
default=0
default=0
Note 1: see the "Table 2. Protected Area Sizes".
P/N: PM1553
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
Non-volatile
bit
Factory
default=0
Non-volatile
bit
Factory
default=0
16
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
Factory
default=0
Factory
default=0
REV. 1.6, DEC. 12, 2012
MX25L1635E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to "Figure 13. Write Status Register (WRSR) Sequence (Command 01)")
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode
Status register condition WP# and SRWD bit status
Memory
Software protection mode
(SPM)
Status register can be
WP#=1 and SRWD bit=0, or
written in (WEL bit is set to
The protected area cannot
WP#=0 and SRWD bit=0,
"1") and the SRWD, BP0be programmed or erased.
WP#=1 and SRWD bit=1
BP1 bits can be changed
Hardware protection mode
(HPM)
The SRWD, BP0-BP1 of
status register bits can be
changed
WP#=0, SRWD bit=1
The protected area cannot
be programmed or erased.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
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Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O read mode, the feature of HPM will be disabled.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read
out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address
on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to
"Figure 14. Read Data Bytes (READ) Sequence (Command 03)")
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address can be at any
location. The address is automatically increased to the next higher address after each byte data is shifted out, so
the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3byte address on SI→ 1-dummy byte address on SI→data out on SO→to end FAST_READ operation can use CS#
to high at any time during data out. (Please refer to "Figure 15. Read at Higher Speed (FAST_READ) Sequence
(Command 0B)")
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction,
the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→4 dummy cycles on SIO1 & SIO0→data out interleave on SIO1 & SIO0→ to end 2READ
operation can use CS# to high at any time during data out (see "Figure 16. 2 x I/O Read Mode Sequence (Command
BB)").
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1553
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REV. 1.6, DEC. 12, 2012
MX25L1635E
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (see "Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB)").
Another sequence of issuing 4 READ instruction especially useful in random access is: CS# goes low→sending
4 READ instruction→24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles →data out interleave on SIO3, SIO2, SIO1 and SIO0 till CS# goes high → CS# goes low
(reduce 4 Read instruction) →24-bit random access address (see "Figure 18. 4 x I/O Read enhance performance
Mode Sequence (Command EB)").
In the performance-enhancing mode (Note of Figure. 17), P[7:4] must be toggling with P[3:0] ; likewise
P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is
no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered,
the system then will escape from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see table 4) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI →
CS# goes high. (Please refer to "Figure 21. Sector Erase (SE) Sequence (Command 20)")
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
P/N: PM1553
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REV. 1.6, DEC. 12, 2012
MX25L1635E
(11) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see "Table 4. Memory Organization (16Mb)") is
a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit
of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI →
CS# goes high. (Please refer to "Figure 22. Block Erase (BE) Sequence (Command D8)")
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(12) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary (the eighth bit of address byte been latched-in), otherwise the instruction will be
rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (Please
refer to "Figure 23. Chip Erase (CE) Sequence (Command 60 or C7)")
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed
when BP3, BP2, BP1, BP0 all set to "0".
(13) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs
only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0)
should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length
are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the
data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous
data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at
the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high. (Please refer to "Figure 19. Page Program (PP) Sequence (Command
02)")
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
P/N: PM1553
20
REV. 1.6, DEC. 12, 2012
MX25L1635E
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(14) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than
85MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 85MHz below. The other
function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to "Figure 20. 4 x I/O Page Program (4PP)
Sequence (Command 38)")
(15) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. (Please
refer to "Figure 24. Deep Power-down (DP) Sequence (Command B9)")
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode.
(16) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 10. AC Characteristics". Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions in next page. This is not the same as RDID instruction. It is not recommended to use for new design.
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For new design, please use RDID instruction.
The sequence is shown as "Figure 25. Read Electronic Signature (RES) Sequence (Command AB)", "Figure 26.
Release from Deep Power-down (RDP) Sequence (Command AB)". Even in Deep power-down mode, the RDP
and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle;
there's no effect on the current program/erase/write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
(17) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction
that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS4 instruction is recommended to use for 4 I/O identification and REMS2 instruction is recommended to use for 2 I/O identification.
The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh" followed
by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in "Figure 27.
Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)". The Device ID values
are listed in Table 7 of ID Definitions in next page. If the one-byte address is initially set to 01h, then the device ID
will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Table 7. ID Definitions
RDID Command
manufacturer ID
C2
memory type
25
electronic ID
25
device ID
25
RES Command
REMS/REMS2/REMS4
Command
P/N: PM1553
manufacturer ID
C2
22
memory density
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MX25L1635E
(18) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid.
(19) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(20) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction →Security Register
data out on SO→ CS# goes high.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP
area cannot be update any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.
P/N: PM1553
23
REV. 1.6, DEC. 12, 2012
MX25L1635E
(21) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
x
x
x
x
x
x
LDSO
(indicate if
lock-down
Secured OTP
indicator bit
0 = nonfactory
lock
1 = factory
lock
non-volatile bit
reserved
reserved
reserved
reserved
reserved
reserved
0 = not lockdown
1 = lock-down
(cannot
program/erase
OTP)
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile bit
P/N: PM1553
24
REV. 1.6, DEC. 12, 2012
MX25L1635E
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
P/N: PM1553
25
REV. 1.6, DEC. 12, 2012
MX25L1635E
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Rating
Value
Industrial grade
Ambient Operating Temperature
Storage Temperature
-40°C to 85°C
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see "Figure 2.
Maximum Negative Overshoot Waveform", "Figure 3. Maximum Positive Overshoot Waveform".
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
Capacitance
TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM1553
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
26
Conditions
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 4. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. Output Loading
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
P/N: PM1553
27
REV. 1.6, DEC. 12, 2012
MX25L1635E
Table 9. DC Characteristics
Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
ISB1
VCC Standby Current
1
20
50
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
3
20
uA
25
mA
15
mA
fT=80MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
10
mA
f=50MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
20
mA
20
mA
1
20
mA
Erase in Progress, CS#=VCC
1
20
mA
Erase in Progress, CS#=VCC
-0.5
0.3VCC
V
0.7VCC
VCC+0.4
V
0.4
V
IOL = 1.6mA
V
IOH = -100uA
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector Erase
Current (SE)
VCC Chip Erase Current
(CE)
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
1
1
VCC-0.2
VIN = VCC or GND,
CS# = VCC
f=108MHz,
fT=104MHz(VCC=3.0V~3.6V,
2 x I/O read)
fQ=108MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. It is measured under checkboard pattern.
P/N: PM1553
28
REV. 1.6, DEC. 12, 2012
MX25L1635E
Table 10. AC Characteristics
Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V
Symbol
fSCLK
fRSCLK
fTSCLK
f4PP
tCH(1)
tCL(1)
tCLCH(2)
tCHCL(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL(3)
tSHQZ(2)
tCLQV
tCLQX
tWHS
tSHWL
tDP(2)
tRES1(2)
tRES2(2)
tW
tBP
tPP
tSE
tBE
tCE
Alt. Parameter
Clock Frequency for the following instructions:
fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI,
RDID, RDSR, WRSR
fR Clock Frequency for READ instructions
2.7~3.6V
fT Clock Frequency for 2READ instructions
3.0~3.6V
fQ Clock Frequency for 4READ instructions
Clock Frequency for 4PP
2.7~3.6V
(Quad Page Program)
3.0~3.6V
Serial
tCLH Clock High Time
Normal Read
4PP
Serial
tCLL Clock Low Time
Normal Read
4PP
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
tDH Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
tCSH CS# Deselect Time
Write/Erase/Program
tDIS Output Disable Time
Loading: 30pF
tV Clock Low to Output Valid
Loading: 15pF
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
Min.
Typ.
D.C.
4.5
9
5.5
4.5
9
5.5
0.1
0.1
3
3
2
2
3
3
15
50
Max.
Unit
108
MHz
50
80
104
108
85
104
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
ms
us
ms
ms
s
s
9
6
6
1
20
100
40
9
0.7
60
0.4
6
10
20
20
100
300
3
300
2.2
30
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC or fR or f4PP).
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1553
29
REV. 1.6, DEC. 12, 2012
MX25L1635E
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM1553
tSHQZ
ADDR.LSB IN
30
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
SO
High-Z
Figure 9. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 10. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
SCLK
Command
SI
SO
P/N: PM1553
04
High-Z
31
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 11. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
High-Z
SO
7
6
5
3
2
1
Device Identification
0 15 14 13
MSB
3
2
1
0
MSB
Figure 12. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
Status Register Out
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 13. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
SO
P/N: PM1553
Status
Register In
01
7
6
5
4
3
2
1
0
MSB
High-Z
32
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 14. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
24-Bit Address
23 22 21
03
SI
3
2
1
0
MSB
Data Out 1
High-Z
SO
7
6
5
4
Data Out 2
2
3
1
7
0
MSB
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Configurable
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM1553
4
33
6
5
4
3
2
1
0
7
MSB
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 16. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
18 19 20 21 22 23 24 25 26 27
9 10 11
SCLK
8 Bit Instruction
BB(hex)
SI/SIO0
SO/SIO1
4 dummy
cycle
12 BIT Address
High Impedance
Data Output
address
bit22, bit20, bit18...bit0 P2 P0
data
bit6, bit4, bit2...bit0, bit6, bit4....
address
bit23, bit21, bit19...bit1 P3 P1
data
bit7, bit5, bit3...bit1, bit7, bit5....
Note:
1. SI/SIO0 or SO/SIO1 should be kept "00" or "11" in the first 2 dummy cycles.
In other words, P2=P0 or P3=P1 is necessary.
Figure 17. 4 x I/O Read Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
SI/SIO0
SO/SIO1
WP#/SIO2
NC/SIO3
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
P/N: PM1553
34
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
SCLK
8 Bit Instruction
WP#/SIO2
NC/SIO3
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
High Impedance
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
High Impedance
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
High Impedance
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
EB(hex)
SI/SIO0
SO/SIO1
6 Address cycles
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
SCLK
6 Address cycles
Performance
enhance
indicator (Note)
4 dummy
cycles
Data Output
SI/SIO0
address
bit20, bit16..bit0
P4 P0
data
bit4, bit0, bit4....
SO/SIO1
address
bit21, bit17..bit1
P5 P1
data
bit5 bit1, bit5....
WP#/SIO2
address
bit22, bit18..bit2
P6 P2
data
bit6 bit2, bit6....
NC/SIO3
address
bit23, bit19..bit3
P7 P3
data
bit7 bit3, bit7....
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1553
35
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 19. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
Data Byte 3
2
0
1
MSB
7
6
5
4
3
2
Data Byte 256
1
7
0
MSB
6
5
4
3
2
MSB
Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Command
20 16 12 8
4
0
4
0
4
0
4
0
4
0
SO/SIO1
21 17 13 9
5
1
5
1
5
1
5
1
5
1
WP#/SIO2
22 18 14 10
6
2
6
2
6
2
6
2
6
2
NC/SIO3
23 19 15 11
7
3
7
3
7
3
7
3
7
3
SI/SIO0
P/N: PM1553
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
6 Address cycle
38
36
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 21. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
7
20
6
2
1
0
MSB
Note: SE command is 20(hex).
Figure 22. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8
2
1
0
MSB
Note: BE command is D8(hex).
Figure 23. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
P/N: PM1553
37
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 24. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
B9
SI
Stand-by Mode
Deep Power-down Mode
Figure 25. Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
tRES2
3 Dummy Bytes
23 22 21
AB
3
2
1
0
MSB
Electronic Signature Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
Stand-by Mode
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
SO
AB
High-Z
Deep Power-down Mode
P/N: PM1553
38
Stand-by Mode
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
X
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
1
MSB
MSB
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
(2) Instruction is either 90(hex) or EF(hex) or DF(hex).
P/N: PM1553
39
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 28. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
Device is fully
accessible
tVSL
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 11. Power-Up Timing
Symbol
Parameter
Min.
tVSL(1)
VCC(min) to CS# low
300
Max.
Unit
us
Note: 1. The parameter is characterized only.
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1553
40
REV. 1.6, DEC. 12, 2012
MX25L1635E
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 29. AC Timing at Device Power-Up" and "Figure 30. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 29. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tSHCH
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 10. AC Characteristics".
P/N: PM1553
41
REV. 1.6, DEC. 12, 2012
MX25L1635E
Figure 30. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
P/N: PM1553
42
REV. 1.6, DEC. 12, 2012
MX25L1635E
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
Unit
Write Status Register Cycle Time
40
100
ms
Sector Erase Cycle Time
60
300
ms
Block Erase Cycle Time
0.4
2.2
s
Chip Erase Cycle Time
6
30
s
Byte Program Time (via page program command)
9
300
us
0.7
3
ms
Page Program Cycle Time
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
DATA RETENTION
Parameter
Condition
Min.
Data retention
55˚C
20
Max.
Unit
years
LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1553
43
REV. 1.6, DEC. 12, 2012
MX25L1635E
ORDERING INFORMATION
PART NO.
MX25L1635EM2I-10G
P/N: PM1553
CLOCK
(MHz)
TEMPERATURE
PACKAGE
Remark
108
-40°C~85°C
8-SOP (200mil)
RoHS Compliant
44
REV. 1.6, DEC. 12, 2012
MX25L1635E
PART NAME DESCRIPTION
MX 25
L 1635E
M2
I
10 G
OPTION:
G: RoHS Compliant
SPEED:
10: 1 I/O 108MHz, 2 I/O 80MHz, 4 I/O 108MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M2: 200mil 8-SOP
DENSITY & MODE:
1635E: 16Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1553
45
REV. 1.6, DEC. 12, 2012
MX25L1635E
PACKAGE INFORMATION
P/N: PM1553
46
REV. 1.6, DEC. 12, 2012
MX25L1635E
REVISION HISTORY
Revision No. Description
1.0
1. Removed title of "Advanced Information"
1.1
1. Corrected wrong spec: tSLCH from 8ns to 5ns, tSHCH from 8ns to
5ns
2. Removed undefined spec: tQLQH and tQHQL
3. Modified Figure 29. AC Timing at Device Power-Up
4. Added Figure 30. Power-Down Sequence
5. Corrected wrong wording from 512-bit to 4K-bit
6. Corrected wrong address range from xxx010~xxxFFF to
xxx010~xxx1FF
1.2
1. Modified description for RoHS compliance
2. Updated 4PP program frequency
Page
P5
P29
P6,44,45
P21,29
APR/26/2011
1.3
1.4
P29
P29
P29
P29
P29
FEB/20/2012
MAR/19/2012
1.5
1.6
P/N: PM1553
1. Modified spec for tCLQV from both 9ns and 8ns to 6ns (Max.)
1. Modified tCHDX(Min.) from 5ns to 3ns
2. Added f4PP=104MHz @VCC=3.0~3.6V
1. Modified tSLCH, tCHSL, tCHDX, tCHSH, tSHCH time
1. Modified tCLQX time in AC Characteristics Table
47
Date
DEC/09/2009
MAR/18/2010
P30
P41
P42
P14,23,24
P11
JUN/13/2012
DEC/12/2012
REV. 1.6, DEC. 12, 2012
MX25L1635E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
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distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2011~2012. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
48