STMicroelectronics L6926013TR High efficiency monolithic synchronous step down regulator Datasheet

L6926
High efficiency monolithic synchronous step down regulator
Features
■
2 V to 5.5 V battery input range
■
High efficiency: up to 95%
■
Internal synchronous switch
■
No external Schottky required
■
Extremely low quiescent current
■
1 mA max shutdown supply current
■
800 mA max output current
■
Adjustable output voltage from 0.6 V
■
DSC
■
Low drop-out operation: up to 100% duty cycle
■
GPS
■
Selectable low noise/low consumption mode at
light load
Description
MSOP8
■
Power Good signal
■
± 1% output voltage accuracy
■
Current-mode control
■
600 kHz switching frequency
■
Externally synchronizable from 500 kHz to 1.4
MHz
■
OVP
■
Short circuit protection
The device is DC-DC monolithic regulator
specifically designed to provide extremely high
efficiency. L6926 supply voltage can be as low as
2 V allowing its use in single Li-ion cell supplied
applications. Output voltage can be selected by
an external divider down to 0.6 V. Duty cycle can
saturate to 100% allowing low drop-out operation.
The device is based on a 600 kHz fixedfrequency, current mode-architecture. Low
consumption mode operation can be selected at
light load conditions, allowing switching losses to
be reduced. L6926 is externally synchronizable
with a clock which makes it useful in noisesensitive applications. Other features like powergood, overvoltage protection, short-circuit
protection and thermal shutdown (150 °C) are
also present.
Applications
■
Battery-powered equipment
■
Portable instruments
■
Cellular phones
■
PDAs and hand held terminals
Figure 1.
Application test circuit
L 6.8μH
VIN=2V to 5.5V
C1
10μF
6.3V
SYNC
VCC
RUN
5
7
6
R3
500K
VOUT=1.8V
R2
200K
C4
10μF
6.3V
PGOOD
2
D01IN1305
LX
8
1
COMP
April 2011
VFQFPN8
(3x3x1.0 mm)
4
C2
220pF
3
VFB
GND
Doc ID 9302 Rev 9
R1
100K
1/16
www.st.com
16
Contents
L6926
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
5
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1
Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.2
Low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.3
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3
Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4
Loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
DROPOUT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2
PGOOD (Power Good output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3
Adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4
OVP (overvoltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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L6926
1
Pin settings
Pin settings
Figure 2.
Pin connection (top view)
RUN
1
8
PGOOD
COMP
2
7
SYNC
VFB
3
6
VCC
GND
4
5
LX
D01IN1239AMOD
Table 1.
Pin description
Pin n°
Name
1
RUN
2
COMP
Error amplifier output. A compensation network has to be connected to this pin.
Usually a 220 pF capacitor is enough to guarantee the loop stability.
3
VFB
Error amplifier inverting input. The output voltage can be adjusted from 0.6 V up
to the input voltage by connecting this pin to an external resistor divider.
4
GND
Ground.
5
LX
Switch output node. This pin is internally connected to the drain of the internal
switches.
6
VCC
Input voltage. The start up input voltage is 2.2 V (typ) while the operating input
voltage range is from 2 V to 5.5 V. An internal UVLO circuit realizes a 100 mV
(typ.) hysteresis.
7
8
SYNC
Description
Shutdown input. When connected to a low level (lower than 0.4 V) the device
stops working. When high (higher than 1.3 V) the device is enabled.
Operating mode selector input. When high (higher than 1.3 V) the Low
Consumption Mode is selected. When low (lower than 0.5 V) the low noise
mode is selected. If connected with an appropriate external synchronization
signal (from 500 kHz up to 1.4 MHz) the internal synchronization circuit is
activated and the device works at the same switching frequency.
Power good comparator output. It is an open drain output. A pull-up resistor
should be connected between PGOOD and VOUT (or VCC depending on the
PGOOD requirements). The pin is forced low when the output voltage is lower than 90%
of the regulated output voltage and goes high when the output voltage is greater
than 90% of the regulated output voltage. If not used the pin can be left floating.
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Maximum ratings
2
L6926
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Value
Unit
V6
Input voltage
-0.3 to 6
V
V5
Output switching voltage
-1 to VCC
V
V1
Shutdown
-0.3 to VCC
V
V3
Feedback voltage
-0.3 to VCC
V
V2
Error amplifier output voltage
-0.3 to VCC
V
V8
PGOOD
-0.3 to VCC
V
V7
Synchronization mode selector
-0.3 to VCC
V
PTOT
Power dissipation at TA = 70 °C
0.45
W
Junction operating temperature range
-40 to 150
°C
TSTG
Storage temperature range
-65 to 150
°C
LX pin
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “Human body model”
acceptance criteria: “normal performance’
±1000
V
±2000
V
TJ
Other pins
Table 3.
Symbol
RthJA
4/16
Parameter
Thermal data
Parameter
Value
Unit
Maximum thermal resistance junction-ambient for MSOP8
180
°C/W
Maximum thermal resistance junction-ambient for VFQFPN8
56
°C/W
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L6926
3
Electrical characteristics
Electrical characteristics
TJ = 25 °C, VIN = 3.6 V unless otherwise specified.
Table 4.
Electrical characteristics (1)
Symbol
Vcc
Parameter
Test condition
Operating input voltage
Vcc ON
Turn on threshold
Vcc OFF
Turn off threshold
Vcc hys
Hysteresis
After turn on
Min.
(1)
Typ.
2
High side Ron
Rn
Low side Ron
Vcc = 3.6 V, Ilx =100 mA
(1)
Vcc = 3.6 V, Ilx =100 mA
(1)
Vcc = 3.6 V
(1)
Vcc = 3.6 V
(1)
Ilim
fsync
Sync mode clock (2)
(1)
V
mV
300
mΩ
300
mΩ
400
1.2
1.5
A
0.85
1
Valley current limit
Oscillator frequency
V
400
1
fosc
V
100
Peak current limit
Output voltage range
5.5
2
215
VOUT
Unit
2.2
240
Rp
Max.
1.65
1.4
1.7
A
0.9
1.85
Vfb
VCC
450
600
700
400
600
800
V
kHz
500
1400
kHz
DC characteristics
Vsync = 0 V, no load,
VFB > 0.6 V
Quiescent current
(low noise mode)
Vsync = 0 V, no load,
VFB > 0.6 V
Iq
Ish
Ilx
200
300
µA
(1)
300
Quiescent current
(low consumption mode)
Vsync = Vcc, no load,
VFB > 0.6 V
Shutdown current
RUN to GND, Vcc = 5.5 V
0.2
µA
RUN to GND, VLX = 5.5 V,
Vcc = 5.5 V
1
µA
RUN to GND, VLX = 0V,
Vcc = 5.5 V
1
µA
LX leakage current (2)
(1)
25
50
µA
Error amplifier characteristics
Vfb
Ifb
Voltage feedback
Feedback input current
(1)
(2)
VFB = 0.6 V
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0.593
0.600
0.607
V
0.590
0.600
0.610
V
25
nA
5/16
Electrical characteristics
Table 4.
L6926
Electrical characteristics (1) (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.3
V
Run
Vrun_H
RUN threshold high
Vrun_L
RUN threshold low
Irun
RUN input current
0.4
(2)
V
25
nA
SYNC/MODE function
Vsync_H
Sync mode threshold high
Vsync_L
Sync mode threshold low
1.3
0.5
V
V
PGOOD section
VPGOOD
Power good threshold
VOUT = Vfb
90
%VOUT
ΔVPGOOD
Power good hysteresis
VOUT = Vfb
4
%VOUT
VPgood(low) Power good low voltage
ILK-PGOOD
Run to GND
0.4
V
Power good leakage
current (2)
VPGOOD = 3.6 V
50
nA
Hard overvoltage
threshold
VOUT = Vfb
10
%VOUT
Protections
HOVP
1. Specification referred to TJ from -40 °C to +125 °C. Specification over the -40 to +125 °C TJ temperature range are assured
by design, characterization and statistical correlation
2. Guaranteed by design
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L6926
4
Operation description
Operation description
The main loop uses slope compensated PWM current mode architecture. Each cycle the
high side MOSFET is turned on, triggered by the oscillator, so that the current flowing
through it (the same as the inductor current) increases. When this current reaches the
threshold (set by the output of the error amplifier E/A), the peak current limit comparator
PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock
cycle begins or the current flowing through it goes down to zero (ZERO CROSSING
comparator). The peak inductor current required to trigger PEAK_CL depends on the slope
compensation signal and on the output of the error amplifier.
In particular, the error amplifier output depends on the VFB pin voltage. When the output
current increases, the output capacitor is discharged and so the VFB pin decreases. This
produces increase of the error amplifier output, so allowing a higher value for the peak
inductor current. For the same reason, when due to a load transient the output current
decreases, the error amplifier output goes low, so reducing the peak inductor current to
meet the new load requirements.
The slope compensation signal allows the loop stability also in high duty cycle conditions
(see related section).
Figure 3.
Device block diagram
RUN
SYNC
VCC
OSCILLATOR
COM P
FB
GND
LOW
NOISE/
CONSUM PTION
SLOPE
LOOP
CONTROL
E/A
VREF
POWER
PMOS
SENSE
PMOS
GND
PEAK
CL
LX
DRIVER
0.6V
OVP
PGOOD
VREF
ZERO
CROSSING
0.9V
Vcc
SENSE
NMOS
Vcc
POWER
NMOS
GND
PGOOD
VALLEY
CL
GND
4.1
Modes of operation
Depending on the SYNC pin value the device can operate in low consumption or low noise
mode. If the SYNC pin is high (higher than 1.3 V) the low consumption mode is selected
while the low noise mode is selected if the SYNC pin is low (lower than 0.5 V).
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Operation description
4.1.1
L6926
Low consumption mode
In this mode of operation, at light load, the device operates discontinuously based on the
COMP pin voltage, in order to keep the efficiency very high also in these conditions. While
the device is not switching the load discharges the output capacitor and the output voltage
goes down. When the feedback voltage goes lower than the internal reference, the COMP
pin voltage increases and when an internal threshold is reached, the device starts to switch.
In these conditions the peak current limit is set approximately in the range of 200 mA - 400
mA, depending on the slope compensation (see related section).
Once the device starts to switch the output capacitor is recharged. The feedback pin
increases and, when it reaches a value slightly higher than the reference voltage, the output
of the error amplifier goes down until a clamp is activated. At this point, the device stops to
switch. In this phase, most of the internal circuitries are off, so reducing the device
consumption down to a typical value of 25 µA.
4.1.2
Low noise mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable,
the low noise mode can be selected. In low noise mode, the efficiency is a little bit lower
compared with the low consumption mode in very light load conditions but for medium-high
load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600 kHz. Obviously,
in very light load conditions, the device could skip some cycles in order to keep the output
voltage in regulation.
4.1.3
Synchronization
The device can also be synchronized with an external signal from 500 kHz up to 1.4 MHz.
In this case the low noise mode is automatically selected. The device will eventually skip
some cycles in very light load conditions.
The internal synchronization circuit is inhibited in short-circuit and overvoltage conditions in
order to keep the protections effective (see relative sections).
4.2
Short circuit protection
During the device operation, the inductor current increases during the high side turn ON
phase and decrease during the high side turn off phase based on the following equations:
Equation 1
( V IN – V OUT )
ΔI ON = ---------------------------------- ⋅ T ON
L
Equation 2
( V OUT )
ΔI OFF = ------------------- ⋅ T OFF
L
In strong overcurrent or short-circuit conditions the VOUT can be very close to zero. In this
case ΔION increases and ΔIOFF decreases. When the inductor peak current reaches the
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Doc ID 9302 Rev 9
L6926
Operation description
current limit, the high side MOSFET turns off and so the TON is reduced down to the
minimum value (250 ns typ.) in order to reduce as much as possible ΔION.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases
because during the TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has
been introduced. This protection doesn't allow the high side MOSFET to turn on if the
current flowing through the inductor is higher that a specified threshold (valley current limit).
Basically the TOFF is increased as much as required to bring the inductor current down to
this threshold.
So, the maximum peak current in worst case conditions will be:
Equation 3
V IN
I PEAK = I VALLEY + --------- ⋅ T ON_MIN
L
Where IPEAK is the valley current limit (1.4 A typ.) and TON_MIN is the minimum TON of the
high side MOSFET.
4.3
Slope compensation
In current mode architectures, when the duty cycle of the application is higher than
approximately 50%, a pulse-by-pulse instability (the so called sub harmonic oscillation) can
occur.
To allow loop stability also in these conditions a slope compensation is present. This is
realized by reducing the current flowing through the inductor necessary to trigger the COMP
comparator (with a fixed value for the COMP pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an
higher input voltage (due to the increased current ripple across the inductor), so the slope
compensation effect increases as the input voltage increases.
From an application point of view, the final effect is that the peak current limit depends both
on the duty cycle (if higher than approximately 40%) and on the input voltage.
4.4
Loop stability
Since the device is realized with a current mode architecture, the loop stability is usually not
a big issue. For most of the application a 220 pF connected between the COMP pin and
ground is enough to guarantee the stability. In case very low ESR capacitors are used for
the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor
itself can shift at very high frequency and the transient loop response could be affected.
Adding a series resistor to the 220 pF capacitor can solve this problem.
The right value for the resistor (in the range of 50 k) can be determined by checking the load
transient response of the device. Basically, the output voltage has to be checked at the
scope after the load steps required by the application. In case of stability problems, the
output voltage could oscillates before to reach the regulated value after a load step.
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Additional features and protections
L6926
5
Additional features and protections
5.1
DROPOUT operation
The Li-Ion battery voltage ranges from approximately 3 V and 4.1 V - 4.2 V (depending on
the anode material). In case the regulated output voltage is from 2.5 V and 3.3 V, it can be
that, close to the end of the battery life, the battery voltage goes down to the regulated one.
In this case the device stops to switch, working at 100% of duty cycle, so minimizing the
dropout voltage and the device losses.
5.2
PGOOD (Power Good output)
A power good output signal is available. The VFB pin is internally connected to a comparator
with a threshold set at 90% of the of reference voltage (0.6 V). Since the output voltage is
connected to the VFB pin by a resistor divider, when the output voltage goes lower than the
regulated value, the VFB pin voltage goes lower than 90% of the internal reference value.
The internal comparator is triggered and the PGOOD pin is pulled down.
The pin is an open drain output and so, a pull up resistor should be connected to him.
If the feature is not required, the pin can be left floating.
5.3
Adjustable output voltage
The output voltage can be adjusted by an external resistor divider from a minimum value of
0.6V up to the input voltage. The output voltage value is given by:
Equation 4
R
V OUT = 0.6 ⋅ ⎛ 1 + ------2-⎞
⎝
R ⎠
1
5.4
OVP (overvoltage protection)
The device has an internal overvoltage protection circuit to protect the load.
If the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher
than the reference voltage, the low side power MOSFET is turned on until the feedback
voltage goes lower than the reference one.
During the overvoltage circuit intervention, the zero crossing comparator is disabled so that
the device is also able to sink current.
5.5
Thermal shutdown
The device has also a thermal shutdown protection activated when the junction temperature
reaches 150 °C. In this case both the high side MOSFET and the low side one are turned
off. Once the junction temperature goes back lower than 95 °C, the device restarts the
normal operation.
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L6926
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 5.
MSOP8 mechanical data
mm.
Dim.
Min.
Typ.
A
Max.
1.10
A1
0
A2
0.75
b
0.22
0.40
c
0.08
0.23
(1)
D
E
E1
(1)
0.85
3.00
3.20
4.65
4.90
5.15
2.80
3.00
3.10
0.65
0.40
0.60
L1
0.95
L2
0.25
k
0.95
2.80
e
L
0.15
0
ccc
0.80
8
0.10
1. Dimension “D” and “E1” does not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.15 mm per side.
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11/16
Package mechanical data
Figure 4.
L6926
MSOP8 package dimensions
7113595_B
12/16
Doc ID 9302 Rev 9
L6926
Package mechanical data
mm
inch
DIM.
MIN.
TYP.
MAX.
0.80
0.90
1.00
0.0315 0.0354 0.0394
A1
0.02
0.05
0.0008 0.0020
A2
0.70
0.0276
A3
0.20
0.0079
A
b
0.18
D
D2
2.23
2.38
1.49
1.64
2.48
0.40
MAX.
OUTLINE AND
MECHANICAL DATA
0.0071 0.0091 0.0118
0.0878 0.0937 0.0976
0.1181
1.74
0.50
0.30
TYP.
0.1181
3.00
e
L
0.30
3.00
E
E2
0.23
MIN.
0.0587 0.0646 0.0685
0.0197
0.50
0.0118 0.0157 0.0197
VFQFPN8 (3x3x1.0 8mm)
Very thin Fine pitch Quad Packages No lead
ddd
0.08
0.0031
7426334 B
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13/16
Order codes
7
Order codes
Table 6.
14/16
L6926
Order codes
Order codes
Packages
Packaging
L6926
MSOP8
Tube
L6926013TR
MSOP8
Tape and reel
L6926Q1
VFQFPN8
Tube
L6926Q1TR
VFQFPN8
Tape and reel
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L6926
8
Revision history
Revision history
Table 7.
Document revision history
Date
Revision
Changes
Jan-2004
2
First Issue in EDOCS.
Sep-2004
3
Changed the style look and feel.
Add. new package VFSON8.
Add. V8 and V7 parameter in the Table 2 - Absolute Maximum Ratings.
Nov-2004
4
Update order codes
Sep-2005
5
Updated Table. 5 electrical characteristics.
Nov-2005
6
Added VFQFPN8 package and new part numbers.
27-Oct-2006
7
Added RthJA for VFQFPN8 in Table 3.
16-Sep-2008
8
VFSON8 package no longer available
11-Apr-2011
9
Updated MSOP8 package mechanical data Table 5 on page 11 and
Figure 4 on page 12.
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15/16
L6926
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