ISSI IS41LV16256B-60K 256k x 16 (4-mbit) dynamic ram with edo page mode Datasheet

ISSI
®
IS41LV16256B
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
APRIL 2005
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden
• JEDEC standard pinout
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Lead-free available
The ISSI IS41LV16256B is 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row
with access cycle time as short as 10ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the
IS41LV16256B ideal for use in 16 and 32-bit wide data bus
systems.
These features make the IS41LV16256B ideally suited for
high band-width graphics, digital signal processing, highperformance computing systems, and peripheral applications.
The IS41LV16256B is packaged in 40-pin 400-mil SOJ and
TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
-35
-60
Unit
Max. RAS Access Time (tRAC)
35
60
ns
Max. CAS Access Time (tCAC)
11
15
ns
Max. Column Address Access Time (tAA)
18
30
ns
Min. EDO Page Mode Cycle Time (tPC)
14
25
ns
Min. Read/Write Cycle Time (tRC)
60
110
ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
40-Pin SOJ
VDD
1
40
GND
VDD
1
40
GND
I/O0
2
39
I/O15
I/O0
2
39
I/O15
I/O1
3
38
I/O14
I/O1
3
38
I/O14
I/O2
4
37
I/O13
I/O3
5
36
I/O12
I/O2
4
37
I/O13
VDD
6
35
GND
I/O3
5
36
I/O12
I/O4
7
34
I/O11
VDD
6
35
GND
I/O5
8
33
I/O10
I/O4
7
34
I/O6
9
32
I/O9
I/O5
8
33
I/O7
10
31
I/O8
I/O6
9
32
I/O7
10
NC
11
NC
NC
11
30
NC
NC
12
29
LCAS
WE
13
28
UCAS
RAS
14
27
OE
NC
15
26
A8
PIN DESCRIPTIONS
A0-A8
Address Inputs
I/O0-15
Data Inputs/Outputs
I/O11
WE
Write Enable
I/O10
I/O9
OE
Output Enable
31
I/O8
RAS
Row Address Strobe
30
NC
12
29
LCAS
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
WE
13
28
UCAS
RAS
14
27
OE
NC
15
26
A8
VDD
Power
16
25
A7
GND
Ground
NC
No Connection
A0
16
25
A7
A0
A1
17
24
A6
A1
17
24
A6
A2
18
23
A5
A2
18
23
A5
A3
19
22
A4
A3
19
22
A4
VDD
20
21
GND
VDD
20
21
GND
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
1
ISSI
IS41LV16256B
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ADDRESS
BUFFERS
A0-A8
2
ROW DECODER
REFRESH
COUNTER
MEMORY ARRAY
262,144 x 16
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O15
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
TRUTH TABLE
Function
RAS
WE
OE
Address tR/tC
Standby
H
H
H
X
X
X
Read: Word
L
L
L
H
L
ROW/COL
D OUT
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
D IN
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
Read-Write (1,2)
L
L
L
H→L
L→H
ROW/COL
DOUT, DIN
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
Any Cycle:
L
L
L
H→L
H→L
L→H
H→L
H→L
L→H
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
D OUT
D OUT
D OUT
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
L
L
H→L
H→L
H→L
H→L
L
L
X
X
ROW/COL
NA/COL
D IN
D IN
EDO Page-Mode
Read-Write (1,2)
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
L
L
L
L
H
L
L
X
ROW/COL
ROW/COL
D OUT
D OUT
L
H
H
X
X
ROW/NA
High-Z
H→L
L
L
X
X
X
High-Z
Hidden Refresh2)
RAS-Only Refresh
CBR Refresh(3)
1st Cycle:
2nd Cycle:
Read L→H→L
Write L→H→L
LCAS UCAS
I/O
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
3
ISSI
IS41LV16256B
®
Functional Description
Refresh Cycle
The IS41LV16256B is a CMOS DRAM optimized for highspeed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 18 address bits. These are entered nine bits (A0-A8)
at a time. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter nine bits.
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
The IS41LV16256B has two CAS controls, LCAS and
UCAS. The LCAS and UCAS inputs internally generates
a CAS signal functioning in an identical manner to the
single CAS input on the other 256K x 16 DRAMs. The key
difference is that each CAS controls its corresponding I/O
tristate logic (in conjunction with OE and WE and RAS).
LCAS controls I/O0 through I/O7 and UCAS controls I/O8
through I/O15.
The IS41LV16256B CAS function is determined by the
first CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16256B both BYTE READ and BYTE WRITE
cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
4
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VT
VDD
IOUT
PD
TA
TSTG
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
3.3V
3.3V
Rating
Unit
-0.5 to 4.6
-0.5 to 4.6
50
1
0 to +70
–55 to +125
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
VDD
VIH
VIL
TA
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
3.3V
3.3V
3.3V
Min.
Typ.
Max.
Unit
3.0
2.0
–0.3
0
3.3
—
—
—
3.6
VDD + 0.3
0.8
+70
V
V
V
°C
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
5
ISSI
IS41LV16256B
®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed
Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ VDD
Other inputs not under test = 0V
–10
10
µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ VDD
–10
10
µA
VOH
Output High Voltage Level
IOH = –2 mA
2.4
—
V
VOL
Output Low Voltage Level
IOL = +2 mA
—
0.4
V
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
3V
—
4
mA
ICC2
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VDD – 0.2V
3V
—
1
mA
ICC3
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-35
-60
—
—
230
170
mA
ICC4
Operating Current:
EDO Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-35
-60
—
—
220
160
mA
ICC5
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-35
-60
—
—
230
170
mA
ICC6
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-35
-60
—
—
230
170
mA
Commercial
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
Symbol
Parameter
tRC
-60
Min.
Max.
Min.
Max.
Units
Random READ or WRITE Cycle Time
70
—
110
—
ns
tRAC
Access Time from RAS(6, 7)
35
—
60
—
ns
tCAC
Access Time from CAS
—
11
—
15
ns
(6, 8, 15)
(6)
tAA
Access Time from Column-Address
—
18
—
30
ns
tRAS
RAS Pulse Width
35
10K
60
10K
ns
tRP
RAS Precharge Time
25
—
40
—
ns
tCAS
CAS Pulse Width
6
10K
10
10K
ns
tCP
CAS Precharge Time
6
—
10
—
ns
tCSH
CAS Hold Time (21)
35
—
60
—
ns
tRCD
RAS to CAS Delay Time
13
24
20
45
ns
tASR
Row-Address Setup Time
0
—
0
—
ns
tRAH
Row-Address Hold Time
6
—
10
—
ns
tASC
Column-Address Setup Time(20)
0
—
0
—
ns
tCAH
Column-Address Hold Time(20)
6
—
10
—
ns
tAR
Column-Address Hold Time
(referenced to RAS)
30
—
45
—
ns
tRAD
RAS to Column-Address Delay Time(11)
10
20
15
30
ns
tRAL
Column-Address to RAS Lead Time
18
—
30
—
ns
tRPC
RAS to CAS Precharge Time
0
—
0
—
ns
tRSH
RAS Hold Time
10
—
15
—
ns
tCLZ
CAS to Output in Low-Z
3
—
3
—
ns
tCRP
CAS to RAS Precharge Time(21)
5
—
5
—
ns
3
15
3
15
ns
0
11
—
15
ns
tOD
(26)
(9, 25)
(10, 20)
(27)
(15, 29)
(19, 28, 29)
Output Disable Time
(15, 16)
tOE / tOEA
Output Enable Time
tOEHC
OE HIGH Hold Time from CAS HIGH
8
—
8
—
ns
tOEP
OE HIGH Pulse Width
8
—
8
—
ns
tOES
OE LOW to CAS HIGH Setup Time
5
—
7
—
ns
(17, 20)
tRCS
Read Command Setup Time
0
—
0
—
ns
tRRH
Read Command Hold Time
(referenced to RAS)(12)
0
—
0
—
ns
tRCH
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
0
—
0
—
ns
tWCH
Write Command Hold Time(17, 27)
5
—
10
—
ns
tWCR
Write Command Hold Time
(referenced to RAS)(17)
30
—
50
—
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
7
ISSI
IS41LV16256B
®
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
8
-35
Min. Max.
Parameter
tWP
Write Command Pulse Width
tWPZ
(17)
-60
Min. Max.
Units
5
—
10
—
ns
WE Pulse Widths to Disable Outputs
10
—
10
—
ns
tRWL
Write Command to RAS Lead Time(17)
10
—
15
—
ns
tCWL
Write Command to CAS Lead Time(17, 21)
8
—
15
—
ns
0
—
0
—
ns
(14, 17, 20)
tWCS
Write Command Setup Time
tDHR
Data-in Hold Time (referenced to RAS)
30
—
46
—
ns
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
—
15
—
ns
tOEH
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
8
—
15
—
ns
tDS
Data-In Setup Time(15, 22)
0
—
0
—
ns
(15, 22)
tDH
Data-In Hold Time
6
—
10
—
ns
tRWC
READ-MODIFY-WRITE Cycle Time
80
—
140
—
ns
tRWD
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
46
—
80
—
ns
tCWD
CAS to WE Delay Time(14, 20)
25
—
36
—
ns
tAWD
Column-Address to WE Delay Time
30
—
49
—
ns
tPC
EDO Page Mode READ or WRITE
Cycle Time(24)
14
—
25
—
ns
tRASP
RAS Pulse Width in EDO Page Mode
35
100K
60
100K
ns
tCPA
Access Time from CAS Precharge
—
20
—
35
ns
tPRWC
EDO Page Mode READ-WRITE
Cycle Time(24)
45
—
60
—
ns
tCOH / tDOH
Data Output Hold after CAS LOW
5
—
5
—
ns
tOFF
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
3
10
3
15
ns
tWHZ
Output Disable Delay from WE
3
10
3
15
ns
tCLCH
Last CAS going LOW to First CAS
returning HIGH(23)
10
—
10
—
ns
tCSR
CAS Setup Time (CBR REFRESH)(30, 20)
8
—
10
—
ns
tCHR
CAS Hold Time (CBR REFRESH)(30, 21)
8
—
10
—
ns
tORD
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
0
—
0
—
ns
tREF
Refresh Period (512 Cycles)
—
8
—
8
ms
tT
Transition Time (Rise or Fall)(2, 3)
2
50
2
50
ns
(14)
(15)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
IS41LV16256B
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear
the data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
9
ISSI
IS41LV16256B
®
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Don't Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
OE = DON'T CARE)
EARLY WRITE CYCLE (OE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
11
ISSI
IS41LV16256B
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tAWD
tRCS
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
Don't Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tCAS,
tCLCH
tRCD
tPC(1)
tCAS,
tCP
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
Valid Data
tOE
tOES
tAA
tCPA
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
13
ISSI
IS41LV16256B
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCP
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
tDH
Valid Data
Valid Data
OE
Don't Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tDH
tDS
tCAC
tCLZ
DOUT
DIN
DOUT
tOD
tOE
DIN
DOUT
tOD
tOE
tDH
tDS
tCAC
tCLZ
Open
DIN
tOD
tOE
tOEH
OE
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
15
ISSI
IS41LV16256B
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tRAC
tCAC
tCPA
tCAC
tAA
tWHZ
tCOH
I/O
Open
Valid Data (A)
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don't Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
AC WAVEFORMS
READ CYCLE (With WE
WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
tWHZ
Open
I/O
tCLZ
Valid Data
tOE
Open
tOD
OE
Don't Care
RAS
OE
RAS-ONLY REFRESH CYCLE (OE
OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS/LCAS
tASR
ADDRESS
tRAH
Row
I/O
Row
Open
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
17
ISSI
IS41LV16256B
®
CBR REFRESH CYCLE (Addresses; WE
WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
UCAS/LCAS
Open
I/O
WE = HIGH; OE = LOW)(1)
HIDDEN REFRESH CYCLE (WE
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tASR
tRAD
tRAH tASC
tRSH
tCHR
UCAS/LCAS
tAR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Open
Valid Data
tOE
tOD
tORD
OE
Don't Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
ISSI
IS41LV16256B
®
ORDERING INFORMATION : 3.3V
Commercial Range: 0oC to +70oC
Speed (ns)
35
60
Order Part No.
Package
IS41LV16256B-35K
IS41LV16256B-35KL
IS41LV16256B-35T
IS41LV16256B-35TL
IS41LV16256B-60K
IS41LV16256B-60KL
IS41LV16256B-60T
IS41LV16256B-60TL
400-mil SOJ
400-mil SOJ, Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
400-mil SOJ
400-mil SOJ, Lead-free
400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/28/05
19
ISSI
PACKAGING INFORMATION
®
400-mil Plastic SOJ
Package Code: K
N
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
N/2+1
E1
1
E
N/2
SEATING PLANE
D
b
A
C
A2
e
Symbol
No. Leads
A
A1
A2
B
b
C
D
E
E1
E2
e
B
Millimeters
Inches
Min Max
Min
Max
(N)
28
3.25 3.75
0.128 0.148
0.64 —
0.025
—
2.08 —
0.082
—
0.38 0.51
0.015 0.020
0.66 0.81
0.026 0.032
0.18 0.33
0.007 0.013
18.29 18.54
0.720 0.730
11.05 11.30
0.435 0.445
10.03 10.29
0.395 0.405
9.40 BSC
0.370 BSC
1.27 BSC
0.050 BSC
A1
E2
Millimeters
Min Max
Inches
Min Max
Millimeters
Min Max
32
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
Inches
Min Max
36
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
ISSI
PACKAGING INFORMATION
Millimeters
Inches
Symbol Min Max
Min
Max
No. Leads (N)
40
A
3.25 3.75
0.128 0.148
A1
0.64 —
0.025
—
A2
2.08 —
0.082
—
B
0.38 0.51
0.015 0.020
b
0.66 0.81
0.026 0.032
C
0.18 0.33
0.007 0.013
D
25.91 26.16
1.020 1.030
E
11.05 11.30
0.435 0.445
E1
10.03 10.29
0.395 0.405
E2
9.40 BSC
0.370 BSC
e
1.27 BSC
0.050 BSC
Millimeters
Min Max
Inches
Min Max
Millimeters
Min
Max
42
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
3.25 3.75
0.64 —
2.08 —
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
1.27 BSC
®
Inches
Min
Max
44
0.128 0.148
0.025
—
0.082
—
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
ISSI
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1 E
1
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the
package.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
N/2
D
SEATING PLANE
A
e
Plastic TSOP (T - Type II) (MS 25)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
24/26
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.51
0.012 0.0201
c
0.12 0.21
0.005 0.0083
D
17.01 17.27
0.670 0.6899
E1
7.49 7.75
0.295 0.3051
e
1.27 BSC
0.050 BSC
E
9.02 9.42
0.462 0.4701
L
0.40 0.60
0.016 0.0236
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T40
Rev. C 08/013/99
®
b
L
A1
Plastic TSOP (T - Type II) (MS 24)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
40/44
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.45
0.012 0.0157
c
0.12 0.21
0.005 0.0083
D
18.31 18.51
0.721 0.7287
E1
10.06 10.26
0.396 0.4040
e
0.80 BSC
0.031 BSC
E
11.56 11.96
0.455 0.4709
L
0.40 0.60
0.016 0.0236
α
0°
8°
0°
8°
α
c
Plastic TSOP (T - Type II) (MS 24)
Millimeters
Inches
Symbol Min Max
Min Max
Ref. Std.
N
44/50
A
1.20
0.0472
A1
0.05 0.15
0.002 0.0059
b
0.30 0.45
0.012 0.0157
c
0.12 0.21
0.005 0.0083
D
20.85 21.05
0.821 0.8287
E1
10.06 10.26
0.396 0.4040
e
0.80 BSC
0.031 BSC
E
11.56 11.96
0.455 0.4709
L
0.40 0.60
0.016 0.0236
α
0°
8°
0°
8°