TI CD74HCT670 High-speed cmos logic 4x4 register file Datasheet

[ /Title
(CD74H
C670,
CD74H
CT670)
/Subject
(HighSpeed
CMOS
Logic
4x4 Register
CD74HC670,
CD74HCT670
Data sheet acquired from Harris Semiconductor
SCHS195
High-Speed CMOS Logic
4x4 Register File
January 1998
Features
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
• Simultaneous and Independent Read and Write
Operations
• Expandable to 512 Words of n-Bits
• Three-State Outputs
• Organized as 4 Words x 4 Bits Wide
Description
• Buffered Inputs
The Harris CD74HC670 and CD74HCT670 are 16-bit register
files organized as 4 words x 4 bits each. Read and write
address and enable inputs allow simultaneous writing into one
location while reading another. Four data inputs are provided
to store the 4-bit word. The write address inputs (WA0 and
WA1) determine the location of the stored word in the register.
When write enable (WE) is low the word is entered into the
address location and it remains transparent to the data. The
outputs will reflect the true form of the input data. When (WE)
is high data and address inputs are inhibited. Data acquisition
from the four registers is made possible by the read address
inputs (RA1 and RA0). The addressed word appears at the
output when the read enable (RE) is low. The output is in the
high impedance state when the (RE) is high. Outputs can be
tied together to increase the word capacity to 512 x 4 bits.
• Typical Read Time = 16ns for CD74HC670 VCC = 5V, CL
= 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
Ordering Information
Pinout
CD74HC670, CD74HCT670
(PDIP, SOIC)
TOP VIEW
D1 1
16 VCC
D2 2
15 D0
D3 3
14 WA0
RA1 4
13 WA1
RA0 5
12 WE
Q3 6
11 RE
Q2 7
10 Q0
GND 8
9 Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
1660.1
CD74HC670, CD74HCT670
Functional Diagram
D0
D1
D2
D3
WE
15
10
1
9
2
7
3
6
12
Q0
Q1
Q2
Q3
11
RE
RA1
4
5
14
13
RA0
WA0
WA1
WRITE MODE SELECT TABLE
INPUTS
OPERATING
MODE
Write Data
Data Latched
READ MODE SELECT TABLE
WE
DN
INTERNAL
LATCHES
(NOTE 3)
L
L
L
L
H
H
H
X
No Change
INPUTS
OPERATING
MODE
Read
NOTE:
Disabled
3. The Write Address (WA0 and WA1) to the “internal latches” must
be stable while WE is LOW for conventional operation.
RE
INTERNAL
LATCHES
(NOTE 4)
OUTPUT
QN
L
L
L
L
H
H
H
X
(Z)
NOTE:
4. The selection of the “internal latches” by Read Address (RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State
2
CD74HC670, CD74HCT670
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
VCC
(V)
25oC
MIN
TYP
-40oC TO 85oC -55oC TO 125oC
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD74HC670, CD74HCT670
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
VIL or VIH
VO =
VCC or
GND
6
-
-
±0.5
-
±5.0
-
±10
µA
Three- State Leakage
Current
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
II
VCC and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
VIL or VIH
VO =
VCC or
GND
5.5
-
-
±0.5
-
±5.0
-
±10
µA
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three- State Leakage
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
WE
0.3
WA0
0.2
WA1
0.4
RE
1.5
DATA
0.15
RA0
0.4
RA1
0.7
NOTE: Unit load is ∆ICC limit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.
4
CD74HC670, CD74HCT670
Prerequisite for Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tSU, th
2
60
-
-
75
-
-
90
-
-
ns
4.5
12
-
-
15
-
-
18
-
-
ns
6
10
-
-
13
-
-
15
-
-
ns
2
5
-
-
5
-
-
5
-
-
ns
4.5
5
-
-
5
-
-
5
-
-
ns
6
5
-
-
5
-
-
5
-
-
ns
2
80
-
-
100
-
-
120
-
-
ns
4.5
16
-
-
20
-
-
24
-
-
ns
6
14
-
-
17
-
-
20
-
-
ns
2
100
-
-
125
-
-
150
-
-
ns
4.5
20
-
-
25
-
-
30
-
-
ns
6
17
-
-
21
-
-
26
-
-
ns
HC TYPES
Setup Time
Data to WE
Write to WE
Hold Time
Data to WE
Write to WE
Pulse Width WE
Latch Time WE to RA0,
RA1
tH, tW
tW
tLATCH
HCT TYPES
Setup Time
Data to WE
tSU, th
4.5
12
-
-
15
-
-
18
-
-
ns
Hold Time
Data to WE
Write to WE
tH, tW
4.5
5
-
-
5
-
-
5
-
-
ns
Setup Time
Write to WE
tSU
4.5
18
-
-
23
-
-
27
-
-
ns
Pulse Width WE
tW
4.5
20
-
-
25
-
-
30
-
-
ns
tLATCH
4.5
25
-
-
31
-
-
38
-
-
ns
Latch Time WE to RA0,
RA1
Switching Specifications
PARAMETER
HC TYPES
Propagation Delay
Reading Any Word
Write Enable to Output
CL = 50pF, Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
tPLH, tPHL
-40oC TO
85oC
25oC
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
195
-
245
-
295
ns
4.5
-
-
39
-
49
-
59
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
CL = 50pF
6
-
-
33
-
42
-
50
ns
CL = 50pF
2
-
-
250
-
315
-
375
ns
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
6
-
-
43
-
54
-
64
ns
5
CD74HC670, CD74HCT670
Switching Specifications
PARAMETER
Data to Output
Output Disable Time
Output Enable Time
Output Transition Time
CL = 50pF, Input tr, tf = 6ns (Continued)
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
2
-
-
256
-
315
-
375
ns
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
6
-
-
43
-
54
-
64
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
CL = 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
26
-
33
-
38
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
tPLZ, tPHZ
tPZL, tPZH
tTHL, tTLH
6
-
-
13
-
10
-
19
ns
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 6, 7)
CPD
CL = 15pF
5
-
59
-
-
-
-
-
pF
CL = 50pF
4.5
-
-
40
-
50
-
53
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
4.5
-
-
50
-
63
-
75
ns
HCT TYPES
Propagation Delay
Reading Any Word
tPHL, tPLH
Write Enable to Output
tPHL, tPLH
CL = 50pF
CL = 15pF
5
-
21
-
-
-
-
-
ns
Data to Output
tPHL, tPLH
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
35
-
44
-
53
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
38
-
48
-
57
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
CO
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 6, 7)
CPD
CL = 15pF
5
-
66
-
-
-
-
-
pF
Output Disable Time
Output Enable Time
Output Transition Time
tPLZ, tPHZ
tPZL, tPZH
NOTES:
6. CPD is used to determine the dynamic power consumption, per output.
7. PD = CPD VCC2 fi + ∑ CL VCC2 fO where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
6
CD74HC670, CD74HCT670
Test Circuits and Waveforms
tWL + tWH =
tfCL
trCL
50%
10%
10%
tf = 6ns
tr = 6ns
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
tfCL
VCC
tfCL
GND
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
tH(H)
tTLH
1.3V
10%
tPLH
10%
GND
tTHL
90%
50%
10%
90%
3V
2.7V
1.3V
0.3V
GND
tTHL
trCL
tWH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
INVERTING
OUTPUT
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
VCC
90%
50%
10%
1.3V
1.3V
tWL
tf = 6ns
tPHL
1.3V
0.3V
tWH
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
2.7V
0.3V
GND
tr = 6ns
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
I
fCL
3V
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tREM
VCC
SET, RESET
OR PRESET
tfCL = 6ns
CLOCK
50%
50%
tWL
CLOCK
INPUT
tWL + tWH =
trCL = 6ns
VCC
90%
CLOCK
I
fCL
CL
50pF
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD74HC670, CD74HCT670
Test Circuits and Waveforms
6ns
(Continued)
6ns
OUTPUT
DISABLE
90%
50%
10%
OUTPUTS
ENABLED
2.7
1.3
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
90%
3V
tPZL
tPLZ
OUTPUT LOW
TO OFF
50%
OUTPUT HIGH
TO OFF
6ns
GND
10%
tPHZ
tf
OUTPUT
DISABLE
tPZL
tPLZ
OUTPUT LOW
TO OFF
6ns
tr
VCC
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
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