AD5220–SPECIFICATIONS (V = +3 V ⴞ 10% or +5 V ⴞ 10%, V = +V , V = 0 V, –40ⴗC < T < +85ⴗC unless DD A ELECTRICAL CHARACTERISTICS otherwise noted) Parameter Symbol DD B Conditions DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL2 R-DNL RWB, VA = NC, RAB = 10 kΩ RWB, VA = NC, RAB = 50 kΩ or 100 kΩ R-INL RWB, VA = NC, RAB = 10 kΩ Resistor Nonlinearity2 RWB, VA = NC, RAB = 50 kΩ or 100 kΩ Nominal Resistor Tolerance ∆R TA = +25°C VAB = VDD, Wiper = No Connect Resistance Temperature Coefficient ∆RAB/∆T Wiper Resistance RW IW = VDD/R, VDD = +3 V or +5 V DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N INL RAB = 10 kΩ Integral Nonlinearity3 RAB = 50 kΩ, 100 kΩ DNL RAB = 10 kΩ Differential Nonlinearity Error3 RAB = 50 kΩ, 100 kΩ Code = 40H Voltage Divider Temperature Coefficient ∆VW/∆T Code = 7FH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H A Min Typ1 Max Units –1 –0.5 –1 –0.5 –30 ± 0.4 ± 0.1 ± 0.5 ± 0.1 +1 +0.5 +1 +0.5 +30 LSB LSB LSB LSB % ppm/°C Ω 800 40 7 –1 –0.5 –1 –0.5 –2 0 RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage VA, VB, VW CA, CB f = 1 MHz, Measured to GND, Code = 40H CW f = 1 MHz, Measured to GND, Code = 40H ICM VA = VB = VW 0 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Current Input Capacitance5 VIH VIL IIL CIL 2.4/2.1 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity VDD IDD PDISS PSS DYNAMIC CHARACTERISTICS5, 7, 8 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time BW_10K BW_50K BW_100K THDW tS Resistor Noise Voltage eNWB VDD = +5 V/+3 V VDD = +5 V/+3 V VIN = 0 V or +5 V ± 0.5 ± 0.2 ± 0.4 ± 0.1 20 –0.5 +0.5 100 +1 +0.5 +1 +0.5 0 +1 VDD 10 48 7.5 Bits LSB LSB LSB LSB ppm/°C LSB LSB V pF pF nA 5 V 0.8/0.6 V ±1 µA pF VIH = +5 V or VIL = 0 V, VDD = +5 V VIH = +5 V or VIL = 0 V, VDD = +5 V 15 75 0.004 5.5 40 200 0.015 RAB = 10 kΩ, Code = 40H RAB = 50 kΩ, Code = 40H RAB = 100 kΩ, Code = 40H VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz VA = VDD, VB = 0 V, 50% of Final Value, 10K/50K/100K RWB = 5 kΩ, f = 1 kHz 650 142 69 0.002 kHz kHz kHz % 0.6/3/6 14 µs nV/√Hz 2.7 INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9 Input Clock Pulsewidth tCH, tCL Clock Level High or Low CS to CLK Setup Time tCSS CS Rise to Clock Hold Time tCSH U/D to Clock Fall Setup Time tUDS 25 20 20 10 V µA µW %/% ns ns ns ns NOTES 1 Typicals represent average readings at +25°C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use V DD = +5 V. 9 See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +3 V or +5 V. Specifications subject to change without notice. –2– REV. A AD5220 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input Voltage to GND . . . . . . . . . . . 0 V, VDD + 0.3 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA Thermal Resistance θJA P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W CLK 1 U/D 2 GND 4 U/D Operation L L H t t X H L X Wiper Increment Toward Terminal A Wiper Decrement Toward Terminal B Wiper Position Fixed 1 CS 0 1 tCSS tCL tCH VDD 7 CS 5 W1 PIN FUNCTION DESCRIPTIONS Table I. Truth Table CLK 8 TOP VIEW A1 3 (Not to Scale) 6 B1 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CS AD5220 Pin No. Name Description 1 2 3 4 5 6 7 8 CLK U/D A1 GND W1 B1 CS VDD Serial Clock Input, Negative Edge Triggered UP/DOWN Direction Increment Control Terminal A1 Ground Wiper Terminal Terminal B1 Chip Select Input, Active Low Positive Power Supply tCSH CLK 0 1 U/D tUDS 0 Figure 3. Detail Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE AD5220–Typical Performance Characteristics 5 SS = 300 UNITS VDD = +2.7V TA = +258C 40 50 FREQUENCY 4 VWB – V 3 2 40H 1 RWB 08H 20H 10H RWA 0 0 32 64 96 CODE – Decimal 128 Figure 4. Wiper to End Terminal Resistance vs. Code 0 04H 02H 01H 8 120 20 0.3 0.2 RINL – LSB 50kV VERSION 0.1 0.0 –0.1 0.3 50kV VERSION 0.1 0.0 –0.1 –0.2 –0.2 10kV VERSION 50kV VERSION 0.2 0.1 0.0 –0.1 TA = +258C VDD = +5.5V VA = +5.5V VB = 0V –0.2 10kV VERSION –0.3 –0.3 0.4 100kV VERSION 0.2 100kV VERSION –0.3 10kV VERSION –0.4 –0.5 –0.5 0 16 32 48 64 80 96 CODE – Decimal 112 128 Figure 7. R-DNL Relative Resistance Step Position Nonlinearity Error vs. Code 32 48 64 80 96 CODE – Decimal 112 128 100kV VERSION 50kV VERSION 0.1 0.0 –0.1 –0.2 –0.3 0 16 32 48 64 80 96 CODE – Decimal 0.450 0.375 0.300 0.255 0.150 0.075 10kV VERSION –0.4 CODE = 40H RAB = 50kV VA = VDD 0.525 POTENTIOMETER DIVIDER NONLINEARITY – LSB 0.2 DNL – LSB 16 0.600 TA = +258C VDD = +5.5V VA = +5.5V VB = 0V 0.3 –0.5 0 Figure 8. R-INL Resistance Nonlinearity Error vs. Supply Voltage 0.5 0.4 112 128 Figure 10. Potentiometer Divider DNL Error vs. Code 100kV VERSION –0.4 0.000 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 SUPPLY VOLTAGE – V Figure 11. Potentiometer Divider INL Error vs. Supply Voltage –4– –0.5 0 16 32 48 64 80 96 CODE – Decimal 112 128 Figure 9. Potentiometer Divider INL Error vs. Code NOMINAL END-TO-END RESISTANCE – kV –0.4 60 0.5 TA = +258C VDD = +5.5V 0.4 0.3 28 36 44 52 WIPER RESISTANCE – V Figure 6. Wiper Contact Resistance 0.5 TA = +258C VDD = +5.5V 24 0 40 60 80 100 20 CONDUCTION CURRENT, IWB – mA Figure 5. Resistance Linearity vs. Conduction Current 0.5 0.4 32 16 7FH 25 INL – LSB PERCENT OF NOMINAL END-TO-END RESISTANCE – % RAB VDD = 5.5V RAB = 50kV 75 0 RDNL – LSB 48 6 100 100 100kV VERSION 80 60 50kV VERSION 40 20 10kV VERSION 0 –40 –15 10 35 60 TEMPERATURE – 8C 85 Figure 12. Nominal Resistance vs. Temperature REV. A 46 39 10kV VERSION 32 25 50kV AND 100kV VERSION 18 11 4 –3 –10 0 16 32 48 64 80 96 CODE – Decimal 112 128 32 25 18 50kV AND 100kV VERSION 40H 20H GAIN – dB 10H –18 08H –24 04H –30 02H –36 VDD = +5V A VIN = VA = 100mV rms VB = +2.5V B –54 1k – W + + 2.5V – 16 32 48 64 80 96 CODE – Decimal –6 40H –12 20H 02H 01H DATA = 40H VDD = +5V VIN = VA = 100mV rms VB = +2.5V –54 1k 112 128 – A B W + + 2.5V – OP42 1M 10k 100k FREQUENCY – Hz Figure 15. 10 kΩ Gain vs. Frequency vs. Code 10H –18 08H –24 04H –30 02H DATA = 40H VDD = +5V A VIN = VA = 100mV rms VB = +2.5V B VDD = +5.5V VA = VB = 0V f = 100kHz – W + + 2.5V – OP42 10k 100k FREQUENCY – Hz 1M TIME 2ms / DIV Figure 17. 100 kΩ Gain vs. Frequency vs. Code Figure 18. Digital Feedthrough 0mV 0.01 –5.8 TA = +258C VDD = +5.0V OFFSET GND = +2.5V RAB = 10kV NORMALIZED GAIN FLATNESS – dB 50mV THD + NOISE – % 100mV NONINVERTING TEST CKT 32 0.001 INVERTING TEST CKT 31 5V 0V TIME 500ns / DIV Figure 19. Midscale Transition Glitch 20mV/ DIV VWB 01H –54 1k 1M 150mV REV. A 04H –30 00H 0.10 CLK 08H –24 –48 0 10H –18 –3 1.00 VDD = +5.5V DATA VA = +5.5V 40H v 3FH VB = 0V f = 100kHz 20H –42 –48 Figure 16. 50 kΩ Gain vs. Frequency vs. Code VWB –12 4 –42 OP42 10k 100k FREQUENCY – Hz 40H –36 –36 01H DATA = 40H –6 11 0 –12 GAIN – dB 39 10kV VERSION 00H 0 6 00H –6 –48 46 Figure 14. ∆RWB/∆T Rheostat 6 0 –558C < TA < +858C VDD = +5.5V RWB MEASURED VA = NO CONNECT 53 –10 Figure 13. ∆VWB/∆T Potentiometer Mode Tempco (10 kΩ and 50 kΩ) –42 6 60 –558C < TA < +858C VDD = +5.5V GAIN – dB 60 53 RHEOSTAT MODE TEMPCO – ppm/8C POTENTIOMETER MODE TEMPCO – ppm/8C AD5220 0.0001 10 100 1k 10k FREQUENCY – Hz 100k Figure 20. Total Harmonic Distortion Plus Noise vs. Frequency –5– –5.9 10kV 50kV –6.0 –6.1 –6.2 –6.3 DATA = 40H VDD = +5V VIN = VA = 50mV rms VB = +2.5V –6.4 –6.5 –6.6 A B – W + + 2.5V – 100kV OP42 –6.7 –6.8 10 100 1k 10k 100k FREQUENCY – Hz 1M Figure 21. Normalized Gain Flatness vs. Frequency AD5220 80 400 IDD – SUPPLY CURRENT – mA 350 PSRR – dB 60 40 VDD = +5V DC 61V p-p AC 20 TA = +258C CODE = 40H CL = 10pF VA = 4V, VB = 0V VDD = +2.7V 250 VDD = +5.5V VA = +5.5V 200 150 VDD = +2.7V VA = +2.7V 100 10k 100k FREQUENCY – Hz 40 VDD = +5.5V 20 50 1M 0 1k Figure 22. Power Supply Rejection vs. Frequency 10k 100k 1M CLOCK FREQUENCY – Hz 10M Figure 23. IDD Supply Current vs. Clock Frequency 0.10 0 1 2 3 4 VB – Volts 6 5 Figure 24. Incremental Wiper Contact Resistance vs. VB 10 TA = +258C ALL LOGIC INPUT PINS TIED TOGETHER LOGIC = 0V OR VDD VD = +5.5V SUPPLY CURRENT – mA IDD SUPPLY CURRENT – mA 60 300 0 0 1k 0.01 VDD = +3.3V 0.001 0.0001 –40 TA = +258C SEE FIGURE 34 FOR TEST CIRCUIT DATA = 3FH VB = 0V TA = +258C RON – V 80 1 VDD = +5V 0.1 0.01 0.001 –15 10 35 60 TEMPERATURE – 8C 85 Figure 25. Supply Current vs. Temperature IDD VDD = +3V 0 1.0 2.0 3.0 4.0 DIGITAL INPUT VOLTAGE – V 5.0 Figure 26. Supply Current vs. Input Logic Voltage –6– REV. A Parametric Test Circuits– AD5220 V+ = VDD 1LSB = V+/128 DUT A W V+ VIN A DUT B ~ W +5V OP279 B OFFSET GND VMS Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) VOUT 2.5V DC Figure 31. Inverting Programmable Gain Test Circuit +5V NO CONNECT DUT A W IW VIN OFFSET GND B 2.5V VMS Figure 28. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) ~ W A DUT VMS2 IW = VDD/RNOMINAL VIN VW +15V ~ W DUT B OFFSET GND B VMS1 B Figure 32. Noninverting Programmable Gain Test Circuit A DUT A W VOUT OP279 OP42 VOUT 2.5V RW = [VMS1 – V MS2]/IW –15V ␣␣ Figure 29.␣ Wiper Resistance Test Circuit Figure 33. Gain vs. Frequency Test Circuit VA V+ = VDD ± 10% V+ ~ VDD A B PSRR (dB) = 20 LOG W VMS DVMS% PSS (%/%) = ––––––– DVDD% DV CODE = ØØH W MS ( ––––– ) DV B DD ISW 0.1V 0 TO VDD Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR) REV. A RSW = 0.1V ISW DUT Figure 34. Incremental ON Resistance Test Circuit –7– AD5220 OPERATION Ax The AD5220 provides a 128-position digitally controlled variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the CLK pin while CS is active low. The direction of the increment is controlled by the U/D (UP/DOWN) control input pin. When the wiper hits the end of the resistor (Terminals A or B) additional CLK pulses no longer change the wiper setting. The wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. Appropriate debounce circuitry is required when push button switches are used to control the count sequence and direction of count. The exact timing requirements are shown in Figure 3. The AD5220 powers ON in a centered wiper position exhibiting nearly equal resistances of RWA and RWB. D E UP/ 7 C DOWN O CNTR D E RS EN U/D POR 40H A W B GND AD5220 Figure 35. Block Diagram DIGITAL INTERFACING OPERATION The AD5220 contains a three-wire serial input interface. The three inputs are clock (CLK), CS and UP/DOWN (U/D). The negative-edge sensitive CLK input requires clean transitions to avoid clocking multiple pulses into the internal UP/DOWN counter register, see Figure 35. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. When CS is taken active low the clock begins to increment or decrement the internal UP/DOWN counter dependent upon the state of the U/D control pin. The UP/DOWN counter value (D) starts at 40H at system power ON. Each new CLK pulse will increment the value of the internal counter by one LSB until the full scale value of 3FH is reached as long as the U/D pin is logic high. If the U/D pin is taken to logic low the counter will count down stopping at code 00H (zero-scale). Additional clock pulses on the CLK pin are ignored when the wiper is at either the 00H position or the 3FH position. All digital inputs (CS, U/D, CLK) are protected with a series input resistor and parallel Zener ESD structure shown in Figure 36. 1kV LOGIC Figure 36. Equivalent ESD Protection Digital Pins 20V A, B, W GND RS RS Wx RDAC UP/DOWN CNTR & DECODE RS Bx RS = RNOMINAL/128 Figure 38. AD5220 Equivalent RDAC Circuit VDD CLK CS D0 D1 D2 D3 D4 D5 D6 PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The final three characters of the part number determine the nominal resistance value, e.g., 10 kΩ =10; 50 kΩ = 50; 100 kΩ = 100. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. At power ON the resistance from the wiper to either end Terminal A or B is approximately equal. Clocking the CLK pin will increase the resistance from the Wiper W to Terminal B by one unit of RS resistance (see Figure 38). The resistance RWB is determined by the number of pulses applied to the clock pin. Each segment of the internal resistor string has a nominal resistance value of RS = RAB/128, which becomes 78 Ω in the case of the 10 kΩ AD5220BN10 product. Care should be taken to limit the current flow between W and B in the direct contact state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical (see Figure 38). The resistance between the Wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used the B–terminal should be tied to the wiper. The typical part-to-part distribution of RBA is process lot dependent having a ± 30% variation. The change in RBA with temperature has a 800 ppm/°C temperature coefficient. The RBA temperature coefficient increases as the wiper is programmed near the B-terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a 0.5%/°C temperature coefficient. Figure 14 shows the effect of the wiper contact resistance as a function of code setting. Another performance factor influenced by the switch contact resistance is the relative linearity error performance between the 10 kΩ, and the 50 kΩ or 100 kΩ versions. The same switch contact resistance is used in all three versions. Thus the performance of the 50 kΩ and 100 kΩ devices which have the least impact on wiper switch resistance exhibits the best linearity error, see Figures 7 and 8. Figure 37. Equivalent ESD Protection Analog Pins –8– REV. A AD5220 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation APPLICATIONS INFORMATION The negative-edge sensitive CLK pin does not contain any internal debounce circuitry. This standard CMOS logic input responds to fast negative edges and needs to be debounced externally with an appropriate circuit designed for the type of switch closure device being used. Good performance results at the CLK input pin when the negative logic transition has a minimum slew rate of 1 V/µs. A wide variety of standard circuits can be used such as a one-shot multivibrator, Schmitt Triggered gates, cross coupled flip-flops, or RC filters to drive the CLK pin with uniform negative edges. This will prevent the digital potentiometer from skipping output codes while counting due to switch contact bounce. The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A Terminal to +5 V and B Terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminals AB divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW(D) = D/128 × VAB + VB (1) D represents the current contents of the internal UP/DOWN counter. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value, therefore, the drift improves to 20 ppm/°C. REV. A –9– AD5220 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 39. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 8 3.20 3.00 2.80 0.50 (0.0196) 0.25 (0.0099) 45° 5.15 4.90 4.65 4 PIN 1 IDENTIFIER 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1 5 0.65 BSC 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.95 0.85 0.75 Figure 40. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions in millimeters and (inches) 15° MAX 1.10 MAX 0.15 0.05 COPLANARITY 0.10 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 1 012407-A 8 4.00 (0.1574) 3.80 (0.1497) 3.20 3.00 2.80 Figure 41. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters -10- REV. A AD5220 ORDERING GUIDE Model1, 2, 3 AD5220BNZ10 AD5220BNZ100 AD5220BNZ50 AD5220BR10 AD5220BR10-REEL7 AD5220BR100 AD5220BR100-REEL AD5220BR100-REEL7 AD5220BRZ10 AD5220BRZ10-REEL AD5220BRZ10-REEL7 AD5220WBRZ10-REEL7 AD5220BRZ100 AD5220BRZ100-REEL7 AD5220BRZ50 AD5220BRM100 AD5220BRM100-REEL7 AD5220BRMZ10 AD5220BRMZ10-REEL7 AD5220BRMZ100 AD5220BRMZ100-R7 AD5220BRMZ50 AD5220BRMZ50-RL7 RAB (kΩ) 10 100 50 10 10 100 100 100 10 10 10 10 100 100 50 100 100 10 10 100 100 50 50 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Option N-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding DQC DQC D9H D9H #DQC #DQC #DQB #DQB 1 Z = RoHS Compliant Part. The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies. 3 W = Qualified for Automotive Products. 2 AUTOMOTIVE PRODUCTS The AD5220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. REVISION HISTORY 12/10—Rev. 0 to Rev. A Changes to Features Section ........................................................... 1 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 11 Added Automotive Products Section .......................................... 11 10/98—Revision 0: Initial Version ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03426-0-12/10(A) REV. A -11-