Mitel MT8967AS Iso2-cmos integrated pcm filter codec Datasheet


ISO2-CMOS MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Features
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ISSUE 10
ST-BUS compatible
Transmit/Receive filters & PCM Codec in one
I.C
Meets AT&T D3/D4 and CCITT G711 and G712
µ-Law: MT8960/62/64/67
A-Law: MT8961/63/65/67
Low power consumption:
Op.: 30 mW typ.
Stby.: 2.5 mW typ.
Digital Coding Options:
MT8964/65/66/67 CCITT Code
MT8960/61/62/63 Alternative Code
Digitally controlled gain adjust of both filters
Analog and digital loopback
Filters and codec independently user
accessible for testing
Powerdown mode available
2.048 MHz master clock input
Up to six uncommitted control outputs
±5V ±5% power supply
May 1995
Ordering Information
MT8964/65AC
18 Pin Ceramic DIP
MT8960/61/64/65AE
18 Pin Plastic DIP
MT8962/63AE
20 Pin Plastic DIP
MT8962/63/66/67AS
20 Pin SOIC
0°C to+70°C
Description
Manufactured in ISO 2-CMOS, these integrated filter/
codecs are designed to meet the demanding
performance needs of the digital telecommunications
industry, e.g., PABX, Central Office, Digital
telephones.
ANUL
VX
Analog to
Digital PCM
Encoder
Transmit
Filter
Output
Register
DSTo
SD0
SD1
SD2
SD3
CSTi
CA
A Register
8-Bits
Output
Register
Control
Logic
C2i
SD4
B-Register
8-Bits
SD5
VR
F1i
PCM Digital
to Analog
Decoder
Receive
Filter
VRef
GNDA
GNDD
Input
Register
VDD
DSTi
VEE
Figure 1 - Functional Block Diagram
6-19
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
MT8962/63/66/67
MT8960/61/64/65
CSTi
DSTi
C2i
DSTo
VDD
F1i
CA
SD3
SD2
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
CSTi
DSTi
C2i
DSTo
VDD
SD5
SD4
F1i
CA
SD3
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
18 PIN CERDIP/PDIP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GNDD
VRef
GNDA
VR
ANUL
VX
VEE
SD0
SD1
SD2
20 PIN PDIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin Name
Description
CSTi
Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (VDD), logic low
(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
DSTi
Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.
C2i
DSTo
Clock Input is a TTL-compatible 2.048 MHz clock.
Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM
word.
VDD
Positive power Supply (+5V).
F1i
Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,
PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,
and provides frame and channel synchronization.
CA
Control Address is a three-level digital input which enables PCM input and output and determines
into which control register (A or B) the serial data, presented to CSTi, is stored.
SD3
System Drive Output is an open drain output of an N-channel transistor which has its source tied to
GNDA. Inactive state is open circuit.
SD4-5
System Drive Outputs are open drain outputs of N-channel transistors which have their source tied
to GNDD. Inactive state is open circuit.
SD0-2
System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive
state is logic low.
VEE
Negative power supply (-5V).
VX
Voice Transmit is the analog input to the transmit filter.
ANUL
VR
GNDA
VRef
GNDD
6-20
Auto Null is used to integrate an internal auto-null signal. A 0.1µF capacitor must be connected
between this pin and GNDA.
Voice Receive is the analog output of the receive filter.
Analog ground (0V).
Voltage Reference input to D to A converter.
Digital ground (0V).
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
MT8960/62
MT8964/66
Digital Output
Digital Output
11111111
10000000
11110000
10001111
11100000
10011111
11010000
10101111
11000000
10111111
10110000
11001111
10100000
11011111
10010000
10000000
00000000
00010000
11101111
11111111
01111111
01101111
00100000
01011111
00110000
01001111
01000000
00111111
01010000
00101111
01100000
00011111
01110000
00001111
00000000
01111111
-2.415V
Bit 7...
0
MSB
LSB
-1.207V
0V
+1.207V +2.415V
Analog Input Voltage (VIN)
Figure 3 - µ-Law Encoder Transfer Characteristic
MT8961/63
MT8965/67
Digital Output
Digital Output
11111111
10101010
11110000
10100101
11100000
10110101
11010000
10000101
11000000
10010101
10110000
11100101
10100000
11110101
10010000
10000000
00000000
00010000
11000101
11010101
01010101
01000101
00100000
01110101
00110000
01100101
01000000
00010101
01010000
00000101
01100000
00110101
01110000
00100101
00101010
01111111
-2.5V
Bit 7...
0
MSB
LSB
-1.25V
0V
+1.25V
+2.5V
Analog Input Voltage (VIN)
Figure 4 - A-Law Encoder Transfer Characteristic
6-21
MT8960/61/62/63/64/65/66/67
Functional Description
Figure 1 shows the functional block diagram of the
MT8960-67. These devices provide the conversion
interface between the voiceband analog signals of a
telephone subscriber loop and the digital signals
required in a digital PCM (pulse code modulation)
switching system. Analog (voiceband) signals in the
transmit path enter the chip at VX, are sampled at
8kHz, and the samples quantized and assigned 8-bit
digital values defined by logarithmic PCM encoding
laws. Analog signals in the receive path leave the
chip at V R after reconstruction from digital 8-bit
words.
Separate switched capacitor filter sections are used
for bandlimiting prior to digital encoding in the
transmit path and after digital decoding in the receive
path. All filter clocks are derived from the 2.048 MHz
master clock input, C2i. Chip size is minimized by
the use of common circuitry performing the A to D
and D to A conversion. A successive approximation
technique is used with capacitor arrays to define the
16 steps and 8 chords in the signal conversion
process. Eight-bit PCM encoded digital data enters
and leaves the chip serially on DSTi and DSTo pins,
respectively.
Transmit Path
Analog signals at the input (Vx) are firstly
bandlimited to 508 kHz by an RC lowpass filter
section. This performs the necessary anti-aliasing
for the following first-order sampled data lowpass
pre-filter which is clocked at 512 kHz. This further
bandlimits the signal to 124 kHz before a fifth-order
elliptic lowpass filter, clocked at 128 kHz, provides
the 3.4 kHz bandwidth required by the encoder
section. A 50/60 Hz third-order highpass notch filter
clocked at 8 kHz completes the transmit filter path.
Accumulated DC offset is cancelled in this last
section by a switched-capacitor auto-zero loop which
integrates the sign bit of the encoded PCM word, fed
back from the codec and injects this voltage level
into the non-inverting input of the comparator. An
integrating capacitor (of value between 0.1 and 1 µF)
must be externally connected from this point (ANUL)
to the Analog Ground (GNDA).
The absolute gain of the transmit filter (nominally 0
dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1
dB steps by means of three binary controlled gain
pads.
The resulting bandpass characteristics with the limits
shown in Figure 10 meet the CCITT and AT&T
recommended specifications. Typical atttenuations
6-22
ISO2-CMOS
are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and
above.
The filter output signal is an 8 kHz staircase
waveform which is fed into the codec capacitor array,
or alternatively, into an external capacitive load of
250 pF when the chip is in the test mode. The digital
encoder generates an eight-bit digital word
representation of the 8 kHz sampled analog signal.
The first bit of serial data stream is bit 7 (MSB) and
represents the sign of the analog signal. Bits 4-6
represent the chord which contains the analog
sample value. Bits 0-3 represent the step value of
the analog sample within the selected chord. The
MT8960-63 provide a sign plus magnitude PCM
output code format. The MT8964/66 PCM output
code conforms to the AT &T D3 specification, i.e.,
true sign bit and inverted magnitude bits. The
MT8965/67 PCM output code conforms to the CCITT
specifications with alternate digit inversion (even bits
inverted). See Figs. 3 and 4 for the digital output
code corresponding to the analog voltage, VIN, at VX
input.
The eight-bit digital word is output at DSTo at a
nominal rate of 2.048 MHz, via the output buffer as
the first 8-bits of the 125 µs sampling frame.
Receive Path
An eight-bit PCM encoded digital word is received on
DSTi input once during the 125 µs period and is
loaded into the input register. A charge proportional
to the received PCM word appears on the capacitor
array and an 8 kHz sample and hold circuit
integrates this charge and holds it for the rest of the
sampling period.
The receive (D/A) filter provides interpolation filtering
on the 8 kHz sample and hold signal from the codec.
The filter consists of a 3.4 kHz lowpass fifth-order
elliptic section clocked at 128 kHz and performs
bandlimiting and smoothing of the 8 kHz "staircase"
waveform. In addition, sinx/x gain correction is
applied to the signal to compensate for the
attenuation of higher frequencies caused by the
capacitive sample and hold circuit. The absolute
gain of the receive filter can be adjusted from 0 dB to
-7 dB in 1 dB steps by means of three binary
controlled gain pads.
The resulting lowpass
characteristics, with the limits shown in Figure 11,
meet the CCITT and AT & T recommended
specifications.
Typical attenuation at 4.6 kHz and above is 30 dB.
The filter is followed by a buffer amplifier which
will drive 5V peak/peak into a 10k ohm load, suitable
for driving electronic 2-4 wire circuits.
ISO2-CMOS
V Ref
An external voltage must be supplied to the V Ref pin
which provides the reference voltage for the digital
encoding and decoding of the analog signal. For
V Ref = 2.5V, the digital encode decision value for
overload (maximum analog signal detect level) is
equal to an analog input V IN = 2.415V (µ-Law
version) or 2.5V (A-Law version) and is equivalent to
a signal level of 3.17 dBm0 or 3.14 dBm0
respectively, at the codec.
The analog output voltage from the decoder at V R is
defined as:
µ-Law:
C
V
X
Ref
16.5 + S
2
[( -0.5
128 ) ( 128 )( 33 )]
+
±V
OFFSET
A-Law:
V
Ref
2C+1
128
X
[( )( 0.532+ S )]
X
2
[( 128
)(16.532+ S )]
±V
OFFSETC=0
C
V
Ref
±V
OFFSETC≠0
where C = chord number (0-7)
S = step number (0-15)
V Ref is a high impedance input with a varying
capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960
series of codecs is 2.5V ±0.5%. The output voltage
from the reference source should have a maximum
temperature coefficient of 100 ppm/C°. This voltage
should have a total regulation tolerance of ±0.5%
both for changes in the input voltage and output
loading of the voltage reference source. A voltage
reference circuit capable of meeting these
specifications is shown in Figure 5. Analog Devices
’AD1403A voltage reference circuit is capable of
NC
NC
NC
NC
8
7
6
5
2
3
driving a large number of codecs due to the high
Normal
input impedance of the V Ref input.
precautions should be taken in PCB layout design to
minimize noise coupling to this pin. A 0.1 µF
capacitor connected from V Ref to ground and located
as close as possible to the codec is recommended to
minimize noise entering through V Ref. This capacitor
should have good high frequency characteristics.
Timing
The codec operates in a synchronous manner (see
Figure 9a). The codec is activated on the first
positive edge of C2i after F1i has gone low. The
digital output at DSTo (which is a three-state output
driver) will then change from a high impedance state
to the sign bit of the encoded PCM word to be
output. This will remain valid until the next positive
edge, when the next most significant bit will be
output.
On the first negative clock edge (after F1i signal has
been internally synchronized and CA is at GNDD or
VEE) the logic signal present at DSTi will be clocked
into the input shift register as the sign bit of the
incoming PCM word.
The eight-bit word is thus input at DSTi on negative
edges of C2i and output at DSTo on positive edges
of C2i.
F1i must return to a high level after the eighth
clock pulse causing DSTo to enter high impedance
and preventing further input data to DSTi. F1i will
continue to be sampled on every positive edge of
C2i. (Note: F1i may subsequently be taken low
during the same sampling frame to enable entry of
serial data into CSTi. This occurs usually mid-frame,
in conjunction with CA=V DD, in order to enter an 8-bit
control word into Register B. In this case, PCM input
and output are inhibited by CA at VDD.)
VRef
0.1 µF
AD1403A
1
MT8960/61/62/63/64/65/66/67
MT8960-67
FILTER/CODEC
4
NC
+5V
2.5V
Figure 5 - Typical Voltage Reference Circuit
6-23
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
Internally the codec will then perform a decode cycle
on the newly input PCM word. The sampled and
held analog signal thus decoded will be updated 25
µs from the start of the cycle. After this the analog
input from the filter is sampled for 18 µs, after which
digital conversion takes place during the remaining
82 µs of the sampling cycle.
Since a single clock frequency of 2.048 MHz is
required, all digital data is input and output at this
rate. DSTo, therefore, assumes a high impedance
state for all but 3.9 µs of the 125 µs frame. Similarly,
DSTi input data is valid for only 3.9 µs.
Digital Control Functions
CSTi is a digital input (levels GNDD to VDD) which is
used to control the function of the filter/codec. It
operates in three different modes depending on the
logic levels applied to the Control Address input
(CA) and chip enable input (F1i) (see Table 1).
Mode 2
CA= -5V (VEE); CSTi receives an eight-bit control
word
CSTi accepts a serial data stream synchronously
with DSTi (i.e., it accepts an eight-bit serial word in a
3.9 µs timeslot, updated every 125 µs, and is
specified
identically
to
DSTi
for
timing
considerations).
This eight-bit control word is
entered into Control Register A and enables
programming of the following functions: transmit and
receive gain, powerdown, loopback. Register B is
reset to zero and the SD outputs assume their
inactive state. Test modes cannot be entered.
Mode 3
CA=0V (GNDD); CSTi receives an eight-bit control
word
As in Mode 2, the control word enters Register A and
the aforementioned functions are controlled. In this
mode, however, Register B is not reset, thus not
affecting the states of the SD outputs.
Mode 1
CA=-5V (V EE); CSTi=0V (GNDD)
The filter/codec is in normal operation with nominal
transmit and receive gain of 0dB. The SD outputs
are in their active states and the test modes cannot
be entered.
CA=+5V (VDD); CSTi receives an 8-bit control word
In this case the control word is transferred into
Register B. Register A is unaffected. The input and
output of PCM data is inhibited.
CA = -5V (VEE); CSTi = +5V (VDD)
A state of powerdown is forced upon the chip
whereby DSTo becomes high impedance, V R is
connected to GNDA and all analog sections have
power removed.
MODE
CA
CSTi
1
(Note 1)
VEE
GNDD
2
VEE
VDD
Serial
The contents of Register B controls the six
uncommitted outputs SD0-SD5 (four outputs, SD0SD3, on MT8960/61/64/65 versions of chip) and also
provide entry into one of the three test modes of the
chip.
FUNCTION
Normal chip operation.
Powerdown.
Eight-bit control word into Register A. Register B is reset.
Data
3
(Note 2)
GNDD
Serial
Eight-bit control word into register A. Register B is unaffected.
Data
VDD
Serial
Eight-bit control word into register A. Register B is unaffected.
Data
Note 1:
When operating in Mode 1, there should be only one frame pulse (F1i) per 125µs frame
Note 2:
When operating in Mode 3, PCM input and output is inhibited by CA=V DD.
Table 1. Digital Control Modes
6-24
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
Note: For Modes 1 and 2, F1i must be at logic low
for one period of 3.9 µs, in each 125 µs cycle, when
PCM data is being input and output, and the control
word at CSTi enters Register A. For Mode 3, F1i
must be at a logic low for two periods of 3.9 µs, in
each 125 µs cycle. In the first period, CA must be at
GNDD or VEE, and in the second period CA must be
high (VDD).
BIT 2
BIT 1
BIT 0
TRANSMIT (A/D)
FILTER GAIN (dB)
0
0
0
0
0
0
1
+1
0
1
0
+2
0
1
1
+3
1
0
0
+4
1
0
1
+5
1
1
0
+6
1
1
1
+7
BIT 5
BIT 4
BIT 3
RECEIVE (D/A)
FILTER GAIN (dB)
On initial power-up these registers are set to the
powerdown condition for a maximum of 25 clock
cycles. During this time it is impossible to change
the data in these registers.
0
0
0
0
0
0
1
-1
0
1
0
-2
Chip Testing
0
1
1
-3
1
0
0
-4
1
0
1
-5
1
1
0
-6
1
1
1
-7
BIT 7
BIT 6
FUNCTION CONTROL
0
0
Normal operation
0
1
Digital Loopback
1
0
Analog Loopback
1
1
Powerdown
Control Registers A, B
The contents of these registers control the filter/
codec functions as described in Tables 2 and 3.
Bit 7 of the registers is the MSB and is defined as the
first bit of the serial data stream input (corresponding
to the sign bit of the PCM word).
By enabling Register B with valid data (eight-bit
control word input to CSTi when F1i=GNDD and CA=
VCC) the chip testing mode can be entered. Bits 6
and 7 (most sign bits) define states for testing the
transmit filter, receive filter and the codec function.
The input in each case is V X input and the output in
each case is VR output. (See Table 3 for details.)
Loopback
Loopback of the filter/codec is controlled by the
control word entered into Register A. Bits 6 and 7
(most sign bits) provide either a digital or analog
loopback condition. Digital loopback is defined as
follows:
• PCM input data at DSTi is latched into the PCM
input register and the output of this register is
connected to the input of the 3-state PCM
output register.
•
The digital input to the PCM digital-to-analog
decoder is disconnected, forced to zero (0).
•
The output of the PCM encoder is disabled and
thus the encoded data is lost. The PCM output
at DSTo is determined by the PCM input data.
Analog loopback is defined as follows:
• PCM input data is latched, decoded and filtered
as normal but not output at V R.
Table 2. Control States - Register A
•
Analog output buffer at V R has its input shorted
to GNDA and disconnected from the receive
filter output.
•
Analog input at V X is disconnected from the
transmit filter input.
•
The receive filter output is connected to the
transmit filter input. Thus the decode signal is
fed back through the receive path and encoded
in the normal way. The analog output buffer at
V R is not tested by this configuration.
In both cases of loopback,
and DSTo is the output.
DSTi is the input
6-25
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
Logic Control Outputs SD0-5
These outputs are directly controlled by the logic
states of bits 0-5 in Register B. A logic low (GNDD)
in Register B causes the SD outputs to assume an
inactive state. A logic high (V DD) in Register B
causes the SD outputs to assume an active state
(see Table 3). SD0-2 switch between GNDD and VDD
and may be used to control external logic or
transistor circuitry, for example, that employed on the
line card for performing such functions as relay drive
for application of ringing to line, message waiting
indication, etc.
SD3-5 are used primarily to drive external analog
circuitry. Examples may include the switching in or
out of gain sections or filter sections (eg., ring trip
filter) (Figure 7).
Telephone Set
2 Wire
Analog
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
AA
AA
PCM Highway AA
AA
AA
AA Supervision
AA
AA
AA
AA Protection
AA
AA
AA
AA
AA
AA
AA
MT8960/61
AA
AA
Battery
AA
AA
MT8962/63
AA
AA
Feed
AA
AA
2W/4W
AA
AA
MT8964/65
AA
AA
Converter
AA
AA
Ringing
AA
AA
MT8966/67
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AA
A
MT8962/63/66/67 provides all six SD outputs.
MT8960/61/64/65 each packaged in an 18-pin DIP
provide only four control outputs, SD0-3.
Figure 6 - Typical Line Termination
BITS 0-2
LOGIC CONTROL OUTPUTS SD0-SD2
0
Inactive state - logic low (GNDD).
1
Active state - logic high (VDD).
BIT 3
LOGIC CONTROL OUTPUT SD3
0
Inactive state - High Impedance.
1
Active state - GNDA.
BITS 4,5
LOGIC CONTROL OUTPUTS SD4, SD5
0
Inactive state - High Impedance.
1
Active state - GNDD.
BIT 7
BIT 6
0
0
Normal operation.
0
1
Transmit filter testing, i.e.:
Transmit filter input connected to VX input
Receive filter and Buffer disconnected from VR
1
0
Receive filter testing, i.e.:
Receive filter input connected to VX input
Receive filter input disconnected from codec
1
1
Codec testing i.e.:
Codec analog input connected to VX
Codec analog input disconnected from transmit filter output
Codec analog output connected to VR
VR disconnected from receive filter output
Table 3. Control States - Register B
6-26
CHIP TESTING CONTROLS
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
Powerdown
External Control:
Powerdown of the chip is achieved in several ways:
1)
Register A. Powerdown is controlled by bits 6
and 7 ( when both at logic high) of Register A
which in turn receives its control word input
via CSTi, when F1i is low and CA input is
either at V EE or GNDD. Power is removed
from the filters and analog sections of the chip.
The analog ouput buffer at V R will be
connected to GNDA. DSTo becomes high
impedance and the clocks to the majority of the
logic are stopped. SD outputs are unaffected
and may be updated as normal.
2)
CSTi Input. With CA at VEE and CSTi held at
continuous logic high the chip assumes the
same state as described in External Control
(1) above.
Internal Control:
1)
2)
Initial Power-up. Initial application of VDD and
VEE causes powerdown for a period of 25 clock
cycles and during this period the chip will
accept input only from C2i. The B-register is
reset to zero forcing SD0-5 to be inactive. Bits
0-5 of Register A (gain adjust bits) are forced
to zero and bits 6 and 7 of Register A become
logic high thus reinforcing the powerdown.
Loss of C2i. Powerdown is entered 10 to 40
µs after C2i has assumed a continuous logic
high (V DD). In this condition the chip will be in
the same state as in (1) above.
Note: If C2i stops at a continuous logic low
(GNDD), the digital data and status is
indeterminate.
Message
Waiting
MT8960/61/64/65
From ST-BUS
CSTi
From ST-BUS
DSTi
Master Clock
to ST-BUS
5V
C2i
DSTo
VDD
(With Relay
Drive)
GNDD
VRef
-100V DC
2.5V
GNDA
VR
0.1µF
ANUL
Alignment
F1i
VX
Register Select
CA
VEE
SD3
SD0
SD2
SD1
-5V
Ring Trip
Filter
(With Relay
Drive)
Gain
Section
2/4 Wire
Converter
Telephone
Line
Ring Feed
-48V DC
(With Relay
Drive)
-48V DC
90VRMS
Figure 7 - Typical Use of the Special Drive Outputs
6-27
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
DSTi
VX
DSTo
VR
CDTi
SD0
..
.
SDn
Speech
Switch
8980
••
•
Line
Interface
&
Monitoring
Circuitry
Line 1
MT8960-67
8
8
Controlling
MicroProcessor
•
•
•
•
•
•
Repeated for Lines
2 to 255
Repeated for Lines
2 to 255
8
8
Control &
Signalling
8980
DSTi
VX
DSTo
VR
CDTi
SD0
..
.
SDn
••
•
Line
Interface
&
Monitoring
Circuitry
Line 256
MT8960-67
Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67
6-28
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
Absolute Maximum Ratings*
Parameter
1
DC Supply Voltages
Symbol
Min
Max
Units
VDD-GNDD
-0.3
+6.0
V
VEE-GNDD
-6.0
+0.3
V
VRef
GNDA
VDD
V
2
Reference Voltage
3
Analog Input
VX
VEE
VDD
V
4
Digital Inputs
Except CA
GNDD-0.3
VDD+0.3
V
CA
VEE-0.3
VDD+0.3
V
SD0-2
GNDD-0.3
VDD+0.3
V
SD3
VEE-0.3
VDD+0.3
V
SD 4-5
VEE-0.3
VDD+0.3
V
20
mA
+125
°C
500
mW
5
Output Voltage
6
Current On Any Pin
II
7
Storage Temperature
TS
8
Power Dissipation at 25°C (Derate 16 mW/°C above 75°C)
-55
PDiss
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to GNDD unless otherwise stated
Characteristics
1
Supply Voltage
Sym
Min
Typ*
Max
Units
VDD
4.75
5.0
5.25
V
VEE
-5.25
-5.0
-4.75
V
2.5
VRef
2
Voltage On Digital Ground
VGNDD
0.0
+0.1
Vdc
Ref. to GNDA
-0.4
0.0
+0.4
Vac
Ref. to GNDA 400ns max.
duration in 125µs cycle
+70
°C
4.0
4.0
mA
mA
All digital inputs at VDD
or GNDD (or VEE for CA)
µA
Mean current
mA
mA
All digital inputs at VDD
or GNDD (or VEE for CA)
Operating Temperature
TO
4
Operating Current
VDD
VEE
IDD
IEE
3.0
3.0
VRef
IRef
2.0
VDD
VEE
IDDO
IEEO
0.25
0.25
Standby Current
See Note 1
-0.1
3
5
V
Comments
0
1.0
1.0
Note 1: Temperature coefficient of VRef should be better than 100 ppm/°C.
DC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Input Current
1
2
3
4
5
D
I
G
I
T
A
L
Sym
Min
Typ*
Max
Units
Test Conditions
Except CA
II
10.0
µA
VIN = GNDD to VDD
CA
IIC
10.0
µA
VIN = VEE to VDD
Input Low
Except CA
VIL
0.0
0.8
V
Voltage
CA
VILC
VEE
VEE+1.2
V
Input High Voltage All Inputs
VIH
2.4
5.0
V
Input Intermediate CA
Voltage
VIIC
0.0
0.8
V
Output Leakage
Current (Tristate)
I0Z
10.0
µA
µA
DSTo
SD3-5
±0.1
Output High Impedance
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
6-29
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
DC Electrical Characteristics (cont’d)
Characteristics
6
Sym
Min
Typ*
Max
Units
Test Conditions
Output Low
DSTo
VOL
0.4
V
IOUT =1.6 mA
Voltage
SD0-2
VOL
1.0
V
IOUT =1 mA
Output High
DSTo
VOH
4.0
V
IOUT =-100µA
Voltage
SD0-2
VOH
4.0
V
IOUT =-1mA
Output Resistance
SD3-5
ROUT
1.0
KΩ
VOUT =+1V
9
Output Capacitance
DSTo
COUT
4.0
pF
Output High Impedance
10
Input Current
VX
IIN
µA
VEE ≤ VIN ≤ VCC
Input Resistance
VX
RIN
10.0
MΩ
Input Capacitance
VX
CIN
30.0
pF
fIN = 0 - 4 kHz
Input Offset Voltage
VX
VOSIN
+1.0
mV
See Note 2
Output Resistance
VR
ROUT
100
Ω
VOSOUT
100
mV
7
8
11
12
13
14
D
I
G
I
T
A
L
A
N
A
L
O
G
15
Output Offset Voltage VR
2.0
10.0
Digital Input= +0
Note 2: V OSIN specifies the DC component of the digitally encoded PCM word.
AC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Sym
Min
Typ*
Max
Units
2.046
2.048
2.05
MHz
Test Conditions
See Note 3
1
Clock Frequency
C2i
fC
2
Clock Rise Time
C2i
tCR
50
ns
3
Clock Fall Time
C2i
tCF
50
ns
4
Clock Duty Cycle
C2i
60
%
5
Chip Enable Rise Time
F1i
tER
100
ns
6
Chip Enable Fall Time
F1i
tEF
100
ns
7
Chip Enable Setup Time F1i
tES
50
ns
See Note 4
Chip Enable Hold Time
F1i
tEH
25
ns
See Note 4
Output Rise Time
DSTo
tOR
100
ns
Output Fall Time
DSTo
tOF
100
ns
Propagation Delay Clock DSTo
to Output Enable
tPZL
tPZH
122
122
ns
ns
Propagation Delay
Clock to Output
DSTo
tPLH
tPHL
100
100
ns
ns
13
Input Rise Time
CSTi
DSTi
tIR
100
100
ns
ns
14
Input Fall Time
CSTi
DSTi
tIF
100
100
ns
ns
15
Input Setup Time
CSTi
DSTi
tISH
tISL
25
0
ns
ns
16
Input Hold Time
CSTi
DSTi
tIH
60
60
ns
ns
8
9
10
11
12
D
I
G
I
T
A
L
40
50
RL=10KΩ to VCC
CL=100 pF
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
6-30
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
AC Electrical Characteristics (cont’d)
Characteristics
17
18
19
20
D
I
G
I
T
A
L
Sym
Min
Typ*
Max
Units
Test Conditions
Propagation Delay
Clock to SD Output
SD
tPCS
400
ns
CL = 100 pF
SD Output Fall Time
SD
tSF
200
ns
CL = 20 pF
SD Output Rise Time
SD
tSR
400
ns
tDL
122
ns
Digital Loopback
Time DSTi to DSTo
(See Figures 9a, 9b, 9c)
Note 3:
The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to
C2i. The A/D and D/A functions are unaffected by changes in clock frequency.
Note 4:
This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an
undetermined state to to the internally synchronized enable signal.
AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
Characteristics
Sym
Analog Input at VX equivalent to
the overload decision level at
the codec
VIN
2
Absolute Gain (0dB setting)
GAX
3
Absolute Gain (+1dB to +7dB
settings)
4
Gain Variation
1
5
A
N
A
L
O
G
Gain Tracking
(See Figure 12)
Quantization
Distortion
(See Figure 13)
Typ*
Max
4.829
5.000
Units
Level at codec:
µ-Law: 3.17 dBm0
A-Law: 3.14 dBm0
See Note 6
-0.25
+0.25
dB
0 dBm0 @ 1004 Hz
-0.35
+0.35
dB
from nominal,
@ 1004 Hz
TA=0°C to 70°C
GAXT
0.01
dB
With Supplies
GAXS
0.04
dB/V
GTX1
CCITT G712
(Method 1)
-0.25
+0.25
dB
-0.25
-0.50
+0.25
+0.50
dB
dB
Sinusoidal Level:
+3 to -20 dBm0
Noise Signal Level:
-10 to -55 dBm0
-55 to -60 dBm0
-0.25
-0.50
-1.50
+0.25
+0.50
+1.50
dB
dB
dB
Sinusoidal Level:
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
dB
dB
dB
dB
dB
Noise Signal Level:
-3 dBm0
-6 to -27 dBm0
-34 dBm0
-40 dBm0
-55 dBm0
GTX2
DQX1
CCITT G712
(Method 1)
Test Conditions
VPP
VPP
With Temp
CCITT G712
(Method 2)
AT&T
6
Min
28.00
35.60
33.90
29.30
14.20
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
6-31
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
Transmit (A/D) Path (cont’d)
Characteristics
7
Sym
Min
Typ*
Max
Units
Test Conditions
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
-45 dBm0
Quantization
Distortion
(cont’d)
(See Figure 13)
CCITT G712
(Method 2)
AT&T
DQX2
Idle Channel
C-message
NCX
18
dBrnC0 µ-Law Only
Noise
Psophometric
NPX
-67
dBm0p CCITT G712
NSFX
-56
dBm0
-46
dB
Input Signal:
0 dBm0 @ 1.02 kHz
270
µs
@ 1004 Hz
µs
µs
µs
Input Signal:
400-3200 Hz Sinewave
at 0 dBm0
35.30
29.30
24.30
dB
dB
dB
8
Single Frequency Noise
9
Harmonic Distortion
(2nd or 3rd Harmonic)
10
Envelope Delay
11
Envelope Delay
Variation With
Frequency
1000-2600 Hz
600-3000 Hz
400-3200 Hz
12
Intermodulation
Distortion
CCITT G712
50/60 Hz
IMDX1
-55
dB
50/60 Hz @ -23 dBm0
and any signal within
300-3400 Hz at -9 dBm0
CCITT G712
2 tone
IMDX2
-41
dB
740 Hz and 1255 Hz
@ -4 to -21 dBm0.
Equal Input Levels
AT&T
IMDX3
-47
dB
2nd order products
4 tone
IMDX4
-49
dB
3rd order products
Gain Relative to ≤50 Hz
Gain @ 1004 Hz 60 Hz
(See Figure 10) 200 Hz
300-3000 Hz
3200 Hz
3300 Hz
3400 Hz
4000 Hz
≥4600 Hz
GRX
-25
-30
0.00
0.125
0.125
0.030
-0.100
-14
-32
dB
dB
dB
dB
dB
dB
dB
dB
dB
0 dBm0 Input Signal
14
Crosstalk D/A to A/D
CTRT
-70
dB
0 dBm0 @ 1.02 kHz
in D/A
15
Power Supply
Rejection
dB
dB
Input 50 mVRMS at
1.02 kHz
16
Overload Distortion (See Fig.15)
A
N
A
L
O
G
13
DAX
VDD
VEE
DDX
60
150
250
-1.8
-0.125
-0.275
-0.350
-0.80
PSSR 1
PSSR2
33
35
CCITT G712
Transmit
Filter
Response
Input frequency=1.02kHz
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 6:
0dBm0=1.185 V RMS for the µ-Law codec.
0dBm0=1.231 V RMS for the A-Law codec.
6-32
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
Characteristics
1
Sym
Analog output at VR
equivalent to the overload
decision level at codec
VOUT
2
Absolute Gain (0dB setting)
GAR
3
Absolute Attenuation (-1dB
to -7dB settings)
4
5
6
Gain Variation
Gain Tracking
(See Figure 12)
A
N
A
L Quantization
O Distortion
G (See Fig. 13)
Min
Typ*
Max
4.829
5.000
Units
Vpp
Vpp
-0.25
+0.25
dB
-0.35
+0.35
dB
Level at codec:
µ-Law: 3.17 dBm0
A-Law: 3.14 dBm0
RL=10 KΩ
See Note 7
0 dBm0 @ 1004Hz
From nominal,
@ 1004Hz
With Temp.
GART
0.01
dB
With Supplies
GARS
0.04
dB/V
CCITT G712
(Method 1)
GTR1
CCITT G712
(Method 2)
AT & T
GTR2
CCITT G712
(Method 1)
DQR1
TA=0°C to 70°C
-0.25
+0.25
dB
-0.25
-0.50
+0.25
+0.50
dB
dB
Sinusoidal Level:
+3 to -10 dBm0
Noise Signal Level:
-10 to -55 dBm0
-55 to -60 dBm0
-0.25
-0.50
-1.50
+0.25
+0.50
+1.50
dB
dB
dB
Sinusoidal Level:
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
28.00
35.60
33.90
29.30
14.30
dB
dB
dB
dB
dB
Noise Signal Level:
-3 dBm0
-6 to -27 dBm0
-34 dBm0
-40 dBm0
-55 dBm0
36.40
30.40
25.40
dB
dB
dB
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
-45 dBm0
DQR2
CCITT G712
(Method 2)
AT & T
7
Test Conditions
Idle Channel
C-message
NCR
12
dBrnC0 µ-Law Only
Noise
Psophometric
NPR
-75
dBm0p CCITT G712
NSFR
-56
dBm0
-46
dB
8
Single Frequency Noise
9
Harmonic Distortion
(2nd or 3rd Harmonic)
10
Intermodulation
Distortion
CCITT G712
Input Signal 0 dBm0
at 1.02 kHz
CCITT G712
2 tone
IMDR2
-41
dB
AT & T
IMDR3
-47
dB
2nd order products
4 tone
IMDR4
-49
dB
3rd order products
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
6-33
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
Receive (D/A) Path (cont’d)
Characteristics
Sym
11
Envelope Delay
DAR
12
Envelope Delay 1000-2600 Hz
Variation with
600-3000 Hz
Frequency
400-3200 Hz
DDR
Gain Relative to <200 Hz
Gain @ 1004 Hz 200 Hz
A (See Figure 11)
300-3000 Hz
N
3300 Hz
A
3400 Hz
L
4000 Hz
O
≥4600 Hz
G
14
Crosstalk A/D to D/A
13
15
Power Supply
Rejection
VDD
VEE
16
Overload Distortion
(See Fig. 15)
Min
Typ*
Units
210
µs
@ 1004 Hz
µs
µs
µs
Input Signal:
400 - 3200 Hz digital
sinewave at 0 dBm0
0.125
0.125
0.125
0.030
-0.100
-14.0
-28.0
dB
dB
dB
dB
dB
dB
dB
0 dBm0 Input Signal
-70
dB
0 dBm0 @ 1.02 kHz
in A/D
dB
dB
Input 50 mVRMS at
1.02 kHz
90
170
265
GRR
-0.5
-0.125
-0.350
-0.80
CTTR
PSRR3
PSRR4
Max
33
35
Test Conditions
Receive
Filter
Response
Input frequency=1.02 kHz
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 7: 0dBm0=1.185 VRMS for µ-Law codec and 0dBm0=1.231 V RMS for A-Law codec.
125 µs
AA
AA
AA
AA
AA
AA
AAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
C2i
INPUT
F1i
INTERNAL
ENABLE
6
5
4
3
2
1
AAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
0 AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AAAAAAA
A
AAA
DSTo AAAA
AAAAAAA
7
OUTPUT AAAA
AAAAAAA
AAA
DSTi
INPUT
AA
AA
AAAA
AAAAAAAAAAAAAAAA
AAAAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA 7
AAAA
AAAA
AAAAAAAAAA
AAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
HIGH IMPEDANCE
7
6
7
6
5V
CA
(Mode 3)
0V
CSTi
INPUT
7
6
5
4
3
2
1
LOAD
A-REGISTER
LOAD
B-REGISTER
Figure 9a - Timing Diagram - 125µs Frame Period
6-34
0
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
8 CLOCK CYCLES
(See Note)
90%
50%
10%
C2i
Input
tCR
tEF
tCF
tER
90%
F1i
Input
10%
tES
DSTo
Output
tEH
tES
tEH
tES
high
impedance
tEH
high-Z
tPZL
tPZH
tPZL
tPZH
Figure 9b - Timing Diagram - Output Enable
Note:
In typical applications, F1i will remain low for 8 cycles of C2i. However, the device will function normally as long as t ES and
tEH are met at each positive edge of C2i.
C2i
Input
90%AAAAAAAAAAAAAAAAAA
AA
A
50%AAAAAAAAAAAAAAAA
AA
A
10%AAAAAAAAAAAAAA
A
A
tCR
DSTo
Output
90%
50%
10%
tCF
AAAAAAAAAAAAAAAAAAAAAAA
A
A
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AA
AAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AA
tOR
DSTi, CSTi
Input
tOF
tPLH
tPLH
90% AAAAAAAAAAAAAAAAA
A
AA
50% AAAAAAAAAAAAAAA
A
A
10% AAAAAAAAAAAAA
A
AAA
AAA
tIF
tIR
tISH
tIH
tISL
Figure 9c - Timing Diagram - Input/Output
6-35
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
SCALE B
SCALE AAAAAPASSBAND
SCALE A SCALE B
AAAAAAATTENUATION
AAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAA
AAAAAA
AA AAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
-0.125
STOPBAND ATTENUATION
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA 0
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
-0.125
AAAA
AAAA
AAAA
AAAA
0.125
AAAA
AAAAAAAAAAAA
A AA AAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
0.35
AAAA
AAAAAAAAAAAA
AAAA
A AA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
A AAAAAAAA
AA
0.35
AA AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A-14
AAA SIN ∏(4000-F)
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AA
AAAA
AAAAAAAAAAAA
A AA AAAAAAA
AAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
A
-1
1200
AAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
A
AAAA
AAAA
AA
AAAA
AAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAAAAAAAAAAA
AAAA
A
1 AAAAA 10
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA 10 1
AAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAAA
AAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAA
AAAA
A
-18
Attenuation AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAASIN ∏(4000-F)
AAAA
AAAA
AAAA
AAAA
A
AAAA
A
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAA
A
-7/9
14
1200
Relative To AAAA
AAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
A
AAAAAAAAAAAAA
AAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
A
Attenuation AAAA
AAAA
AAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAAAAAAAAAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAA
At 1 kHz (dB) AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA 20
AAAA
Note: Above function
2
2 AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAA
AAAAAA 20
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A AAA
AAAA
AAAA
AA
AAAA
AAAA
A
crossover occurs
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAA
AAAA
AA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAA
AAAA
AAAA
AAAAA
AAAA
AA
at 4000Hz.
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAA
AAAA
AAAA
AA
AA
AAAA
AAAAA
AA 25
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAA
AAAA
AAAA
AA
AAAA
AAAA
A
AA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAA
AAAAAAAAAAAAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
A
AAAA
AAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAAAAA
AA
AA AAAAAAAAAAAAAAAAAA
AA
AAAA
AAAAAAAA
AA
AAAA
3 AAAA
AA 30
AAAA
AAAAAA 30
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AA
3
AAAA
AAAAA
AAAAAAAA
AA AAAAAAAAAAAAAAAAAA
AAAA
AAAA
A
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
32
AAAA
AAAAA
AAAA
AAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAA
AAAA
AAAAA
AAAA
A 40
4 AAAA
40
4
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAA
AAAA
AAAAAA
0
5060 100
200
300
3000
3200 3300 3400
4000
4600
5000
10000
FREQUENCY (Hz)
Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter
SCALE A
SCALE B
SCALE A
PASSBAND ATTENUATION
AAAA
AAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
STOPBAND
ATTENUATION
-0.125
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A AAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAA
AAAAAAAAAAA
AAAA
AA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
0
0.125
AAAAAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAA
AAAAAA
AA AAAAAAA
AAA
AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA∏(4000-F)
AAAAAAAA
AAAAAAAA
AAAAAA
AA
0.35
SIN
-14
AAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AA AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAAAA AAAA
AAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
- AA
1
1200
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AA AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA 10
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
1
1 AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
Attenuation
AAAA
AAAA
AAAA
AA AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
14
Relative To
AAAA
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
Attenuation
AAAA
AAAA
AAAA
AA AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
At 1 kHz (dB)
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
20
2
2
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
A 28
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
A
AAAA
AAAA
AAAA
AA
AAAA
AAAA
A
3
3 AAAAA 30
AAAA
AAAA
AAAA
A
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AA 40
4
4 AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAA
0
100
200
300
3000
3200 3300 3400
4000
4600
5000
10000
FREQUENCY (Hz)
Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter
6-36
ISO2-CMOS
MT8960/61/62/63/64/65/66/67
5a. CCITT Method 1
Gain Variation (dB)
+1.0
+0.5
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAAAAAAAA
AAAA
AAAAAAAA
AAAA
AA
A
AAAA
CCITT
End-To-End
Spec
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
+1.0
+0.5
+0.25
+0.25
0
0
-60
-55
-50
-40
-30
-20
-10
-1.0
1
2 Channel Spec
-10
0 -3
Input Level
(dBm0)
-0.25
-0.25
-0.5
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
AAA
AAAAAAAAAAAAAAAA
AAA
AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAA
AAAA
AAAAAAAA
A
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAAA
A
AAAA
AAAAA
A
AAAA
AAAA
AAAA
A
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAAAAAAAA
AAAA
AAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Bandlimited White Noise Test Signal
-0.5
-1.0
AAAAAAAAAAAAAAAA
AAA
AAAAAAAA
AAAA
AAA
AAAAAAAA
AAAAAAAA
AAA
AAAAAAAAAAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Sinusiodal Test Signal
5b. CCITT Method 2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAAAAAAAAAAAAAA
AAA
AAAA
CCITT
End-To-End
Spec
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAA
AA
+1.5
Gain Variation (dB)
+1.0
+0.5
1
2 Channel Spec
+0.25
0
-60
-50
-40
-30
-20
-10
0 +3
Input Level
(dBm0)
-0.25
-0.5
-1.0
-1.5
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Sinusoidal Test Signal
Figure 12 - Variation of Gain With Input Level
6-37
MT8960/61/62/63/64/65/66/67
ISO2-CMOS
6a. CCITT Method 1
40
1
2 Channel Spec
Signal to Total Distortion Ratio (dB)
35.6
33.9AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAA
AA AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
A AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAA
AAAA
33.9
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAA32.2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
29.3 AAAAAAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAA 28.0
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
27.6
26.3
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
AAAA
AAAA CCITT End-To-End
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
Spec
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
14.3AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
A
12.6
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
A
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
A
AAAAA
AAAA
AAAA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA
30
20
10
0
-60
-55
-50
-40
-34
-30
-27
-20
-10
-6
-3
0
+3
Input Level (dBm0)
6b. CCITT Method 2
40
Signal to Total Distortion Ratio (dB)
30
20
10
0
-60
-50
Input Level (dBm0)
Figure 13 - Signal to Total Distortion Ratio vs Input Level
6-38
1
36.4 2 Channel Spec
D/A
1
35.3 2 Channel Spec
35.3
A/D
AAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAA
AAA
AAAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAAAAAAAAAAAA33.0
33.0AAAA
30.4AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
CCITT
29.3AAAAAAAAAAAAAA
AAAA
AAAA
AAAA End-To-End
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
Spec
AAAA
AAAA
AAA
AAAAAAAAAAAAAA
AAAA
25.4AAAA
AAAA
AAAA
AAAA
AAA
AAAA
27.0
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAA
24.3AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAA
AAAA
AAA
AAAA
AAAA
AAAA
22.0
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
-40
-30
-20
-10
0
36.4
ISO2-CMOS
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
CCITT
AAAA
AAAA
AAAAAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAAAAA
AAAAAAAAAAAAAAAA
AAA ½ Channel Spec
AAAAAAA
AAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
AAA
AAAAAAAAAAAAAAAAA
AAA
AAAA
AAAA
(2800Hz)
AAAA
AAAAAA
AAAA
AAAA
A
AAAA
AAAA
AAAAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAA
AAAA
AAAAA
AAAA
AAAA
A
AAAA
AAAA
AAAAAA
AAAA
AAAA
AAAA
AAAA
AAAAAA
AAAA
AAAAA
AAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAA
AAAAAA
AAAAAAAAAAAAAAAAAA
AAAAA
AAAAAAAAAAAAAAAA
AAAAAAA
AAAAA
AAAA
AAAA
AAAAAA
AAAAAA
(600Hz)
AAAAA
AAAAA
AAAA
A
AAAA
AAAAA
AAAAAA
A
A
AAAA
AAAA
AAAA
A
AAAA
A
AAAA
AAAA
AAAAAA
AAAAAA
AAAAA
AAAAA
AAAA
AAAA
A
A
AAAAA
AAAA
A
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAA
AAAA
AAAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
(2600Hz)
1000
750
Envelope Delay (µs)
MT8960/61/62/63/64/65/66/67
500
370
250
125
0
500
1000
1500
2000
2500
3000
Figure 14 - Envelope Delay Variation Frequency
Fundamental Output Power (dBm0)*
5
4.5
4
3
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
3
4
5
6
7
8
9
Input Level (dBm0)
*Relative to Fundamental Output power level with +3dBm0 input signal level at a frequency of 1.02kHz.
Figure 15 - Overload Distortion (End-to-End)
6-39
MT8960/61/62/63/64/65/66/67
NOTES:
6-40
ISO2-CMOS

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