LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 LM8261 Single RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT-23-5 Check for Samples: LM8261 FEATURES 1 (VS = 5V, TA = 25°C, Typical Values Unless Specified). 2 • • • • • • • • • • • GBWP 21MHz Wide Supply Voltage Range 2.5V to 30V Slew Rate 12V/µs Supply Current 0.97 mA Cap Load Limit Unlimited Output Short Circuit Current +53mA/−75mA ±5% Settling Time 400ns (500pF, 100mVPP step) Input common mode voltage 0.3V beyond rails Input voltage noise 15nV/√Hz Input current noise 1pA/√Hz THD+N < 0.05% APPLICATIONS • • • • TFT-LCD flat panel VCOM driver A/D converter buffer High side/low side sensing Headphone amplifier DESCRIPTION The LM8261 is a Rail-to-Rail input and output Op Amp which can operate with a wide supply voltage range. This device has high output current drive, greater than Rail-to-Rail input common mode voltage range, unlimited capacitive load drive capability, and provides tested and guaranteed high speed and slew rate while requiring only 0.97mA supply current. It is specifically designed to handle the requirements of flat panel TFT panel VCOM driver applications as well as being suitable for other low power, and medium speed applications which require ease of use and enhanced performance over existing devices. Greater than Rail-to-Rail input common mode voltage range with 50dB of Common Mode Rejection, allows high side and low side sensing, among many applications, without having any concerns over exceeding the range and no compromise in accuracy. Exceptionally wide operating supply voltage range of 2.5V to 30V alleviates any concerns over functionality under extreme conditions and offers flexibility of use in multitude of applications. In addition, most device parameters are insensitive to power supply variations; this design enhancement is yet another step in simplifying its usage. The output stage has low distortion (0.05% THD+N) and can supply a respectable amount of current (15mA) with minimal headroom from either rail (300mV). The LM8261 is offered in the space saving SOT-23-5 package. SOT-23-5 Figure 1. Output Response with Heavy Capacitive Load Figure 2. SOT-23-5 Top View These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Human Body Model (2) ESD Tolerance 2KV Machine Model (3) 200V VIN Differential +/−10V See (4) (5) Output Short Circuit Duration Supply Voltage (V+ - V−) 32V V+ +0.8V, V− −0.1V Voltage at Input/Output pins −65°C to +150°C Storage Temperature Range Junction Temperature (6) Soldering Information: (1) (2) (3) (4) (5) (6) +150°C Infrared or Convection (20 sec.) 235°C Wave Soldering (10 sec.) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see 2.7V Electrical Characteristics. Human Body Model is 1.5kΩ in series with 100pF. Machine Model, 0Ω is series with 200pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Allowable Output Short Circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. OPERATING RATINGS Supply Voltage (V+ - V−) 2.5V to 30V Temperature Range (1) Package Thermal Resistance, θJA, (1) (1) 2 −40°C to +85°C SOT-23-5 325°C/W The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 2.7V ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 2.7V, V− = 0V, VCM = 0.5V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. (1) Symbol Parameter Condition Typ (2) Limit (3) Units +/−0.7 +/−5 +/−7 mV max µV/C VOS Input Offset Voltage VCM = 0.5V & VCM = 2.2V TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 2.2V (4) +/−2 – IB Input Bias Current VCM = 0.5V (5) −1.20 −2.00 −2.70 VCM = 2.2V (5) +0.49 +1.00 +1.60 IOS Input Offset Current VCM = 0.5V & VCM = 2.2V 20 250 400 CMRR Common Mode Rejection Ratio VCM stepped from 0V to 1.0V 100 76 60 VCM stepped from 1.7V to 2.7V 100 VCM stepped from 0V to 2.7V 70 58 50 µA max nA max dB min +PSRR Positive Power Supply Rejection Ratio V+ = 2.7V to 5V 104 78 74 dB min CMVR Input Common-Mode Voltage Range CMRR > 50dB −0.3 −0.1 0.0 V max 3.0 2.8 2.7 V min VO = 0.5 to 2.2V, RL = 10K to V− 78 70 67 dB min VO = 0.5 to 2.2V, RL = 2K to V− 73 67 63 dB min RL = 10K to V− 2.59 2.49 2.46 RL = 2K to V− 2.53 2.45 2.41 Output Swing Low RL = 10K to V− 90 100 120 mV max Output Short Circuit Current Sourcing to V− VID = 200mV (6) (7) 48 30 20 mA min Sinking to V+ VID = −200mV (6) (7) 65 50 30 mA min 0.95 1.20 1.50 mA max 9 – V/µs AVOL VO Large Signal Voltage Gain Output Swing High ISC IS Supply Current No load, VCM = 0.5V SR Slew Rate (8) AV = +1,VI = 2VPP + V min fu Unity Gain-Frequency VI = 10mV, RL = 2KΩ to V /2 10 – MHz GBWP Gain Bandwidth Product f = 50KHz 21 15.5 14 MHz min Phim Phase Margin VI = 10mV 50 – Deg en Input-Referred Voltage Noise f = 2KHz, RS = 50Ω 15 – nV/ √Hz in Input-Referred Current Noise f = 2KHz 1 (1) (2) (3) (4) (5) (6) (7) (8) pA/ √Hz Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 3 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com 2.7V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 2.7V, V− = 0V, VCM = 0.5V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes.(1) Symbol fMAX Parameter Full Power Bandwidth Condition + ZL = (20pF || 10KΩ) to V /2 Typ (2) Limit (3) Units 1 – MHz 5V ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, all limited guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = 1V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Typ (2) Limit (3) Units +/−0.7 +/−5 +/− 7 mV max +/−2 – µV/°C −1.18 −2.00 −2.70 +0.49 +1.00 +1.60 VOS Input Offset Voltage VCM = 1V & VCM = 4.5V TC VOS Input Offset Average Drift VCM = 1V & VCM = 4.5V (4) IB Input Bias Current VCM = 1V (5) VCM = 4.5V (5) IOS Input Offset Current VCM = 1V & VCM = 4.5V 20 250 400 CMRR Common Mode Rejection Ratio VCM stepped from 0V to 3.3V 110 84 72 VCM stepped from 4V to 5V 100 – VCM stepped from 0V to 5V 80 64 61 µA max nA max dB min +PSRR Positive Power Supply Rejection Ratio V+ = 2.7V to 5V, VCM = 0.5V 104 78 74 dB min CMVR Input Common-Mode Voltage Range CMRR > 50dB −0.3 −0.1 0.0 V max 5.3 5.1 5.0 V min VO = 0.5 to 4.5V, RL = 10K to V− 84 74 70 VO = 0.5 to 4.5V, RL = 2K to V− 80 70 66 RL = 10K to V− 4.87 4.75 4.72 RL = 2K to V− 4.81 4.70 4.66 Output Swing Low RL = 10K to V− 86 125 135 Output Short Circuit Current Sourcing to V− VID = 200mV (6) (7) 53 35 20 Sinking to V+ VID = −200mV (6) (7) 75 60 50 No load, VCM = 1V 0.97 1.25 1.75 AVOL VO ISC IS (1) (2) (3) (4) (5) (6) (7) 4 Large Signal Voltage Gain Output Swing High Supply Current dB min V min mV max mA min mA max Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 5V ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise specified, all limited guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = 1V, VO = V+/2, and RL > 1MΩ to V−. Boldface limits apply at the temperature extremes. Symbol Parameter (8) Condition Limit (3) Units 12 10 7 V/µs min 10.5 – MHz MHz min SR Slew Rate fu Unity Gain Frequency VI = 10mV, RL = 2KΩ to V+/2 GBWP Gain-Bandwidth Product f = 50KHz 21 16 15 Phim Phase Margin VI = 10mV 53 – Deg en Input-Referred Voltage Noise f = 2KHz, RS = 50Ω 15 – nV/ √hZ in Input-Referred Current Noise f = 2KHz 1 – pA/ √hZ fMAX Full Power Bandwidth ZL = (20pF || 10kΩ) to V+/2 900 – KHz tS Settling Time (±5%) 100mVPP Step, 500pF load 400 – ns THD+N Total Harmonic Distortion + Noise RL = 1KΩ to V+/2 f = 10KHz to AV= +2, 4VPP swing 0.05 – % (8) AV = +1, VI = 5VPP Typ (2) Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. ±15V ELECTRICAL CHARACTERISTICS (1) Unless otherwise specified, all limited guaranteed for TA = 25°C, V+ = 15V, V− = −15V, VCM = 0V, VO = 0V, and RL > 1MΩ to 0V. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Typ (2) Limit (3) Units +/−0.7 +/−7 +/− 9 mV max µV/°C VOS Input Offset Voltage VCM = −14.5V & VCM = 14.5V TC VOS Input Offset Average Drift VCM = −14.5V & VCM = 14.5V (4) +/−2 – IB Input Bias Current VCM = −14.5V (5) −1.05 −2.00 −2.80 VCM = 14.5V (5) +0.49 +1.00 +1.50 IOS Input Offset Current VCM = −14.5V & VCM = 14.5V 30 275 550 CMRR Common Mode Rejection Ratio VCM stepped from −15V to 13V 100 84 80 VCM stepped from 14V to 15V 100 – VCM stepped from −15V to 15V 88 74 72 µA max nA max dB min +PSRR Positive Power Supply Rejection Ratio V+ = 12V to 15V 100 70 66 dB min −PSRR Negative Power Supply Rejection Ratio V− = −12V to −15V 100 70 66 dB min CMVR Input Common-Mode Voltage Range CMRR > 50dB −15.3 −15.1 −15.0 V max 15.3 15.1 15.0 V min VO = 0V to ±13V, RL = 10KΩ 85 78 74 VO = 0V to ±13V, RL = 2KΩ 79 72 66 AVOL (1) (2) (3) (4) (5) Large Signal Voltage Gain dB min Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 5 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com ±15V ELECTRICAL CHARACTERISTICS(1) (continued) Unless otherwise specified, all limited guaranteed for TA = 25°C, V+ = 15V, V− = −15V, VCM = 0V, VO = 0V, and RL > 1MΩ to 0V. Boldface limits apply at the temperature extremes. Symbol VO Output Swing High Output Swing Low ISC Typ (2) Limit (3) RL = 10KΩ 14.83 14.65 14.61 RL = 2KΩ 14.73 14.60 14.55 RL = 10KΩ −14.91 −14.75 −14.65 RL = 2KΩ −14.83 −14.65 −14.60 Sourcing to ground VID = 200mV (6) (7) 60 40 25 Sinking to ground VID = 200mV (6) (7) 100 70 60 1.30 1.50 1.90 mA max 10 8 V/µs min Parameter Output Short Circuit Current Condition Units V min V max mA min IS Supply Current No load, VCM = 0V SR Slew Rate (8) AV = +1, VI = 24VPP 15 fu Unity Gain Frequency VI = 10mV, RL = 2KΩ 14 – MHz GBWP Gain-Bandwidth Product f = 50KHz 24 18 16 MHz min Phim Phase Margin VI = 10mV 58 – Deg en Input-Referred Voltage Noise f = 2KHz, RS = 50Ω 15 – nV/ √hZ in Input-Referred Current Noise f = 2KHz 1 – pA/ √hZ fMAX Full Power Bandwidth ZL = 20pF || 10KΩ 160 – KHz ts Settling Time (±1%, AV = +1) Positive Step, 5VPP 320 – Negative Step, 5VPP 600 – RL = 1KΩ, f = 10KHz, AV = +2, 28VPP swing 0.01 – THD+N (6) (7) (8) 6 Total Harmonic Distortion +Noise ns % Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS ≤ 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, Unless Otherwise Noted VOS vs. VCM for 3 Representative Units VOS vs. VCM for 3 Representative Units Figure 3. Figure 4. VOS vs. VCM for 3 Representative Units VOS vs. VS for 3 Representative Units Figure 5. Figure 6. VOS vs. VS for 3 Representative Units VOS vs. VS for 3 Representative Units Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 7 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted 8 IB vs. VCM IB vs. VS Figure 9. Figure 10. IS vs. VCM IS vs. VCM Figure 11. Figure 12. IS vs. VCM IS vs. VS (PNP side) Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted IS vs. VS (NPN side) Gain/Phase vs. Frequency Figure 15. Figure 16. Unity Gain Frequency vs. VS Phase Margin vs. VS Figure 17. Figure 18. Unity Gain Freq. and Phase Margin vs. VS Unity Gain Frequency vs. Load Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 9 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted 10 Phase Margin vs. Load Unity Gain Freq. and Phase Margin vs. CL Figure 21. Figure 22. CMRR vs. Frequency +PSRR vs. Frequency Figure 23. Figure 24. −PSRR vs. Frequency Output Voltage vs. Output Sourcing Current Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted Output Voltage vs. Output Sourcing Current Output Voltage vs. Output Sinking Current Figure 27. Figure 28. Max Output Swing vs. Load Max Output Swing vs. Frequency Figure 29. Figure 30. % Overshoot vs. Cap Load ±5% Settling Time vs. Cap Load Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 11 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted 12 +SR vs. Cap Load −SR vs. Cap Load Figure 33. Figure 34. +SR vs. Cap Load −SR vs. Cap Load Figure 35. Figure 36. Settling Time vs. Error Voltage Settling Time vs. Error Voltage Figure 37. Figure 38. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted Input Noise Voltage/Current vs. Frequency Input Noise Voltage for Various VCM Figure 39. Figure 40. Input Noise Current for Various VCM Input Noise Voltage vs. VCM Figure 41. Figure 42. Input Noise Current vs. VCM THD+N vs. Frequency Figure 43. Figure 44. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 13 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = 25°C, Unless Otherwise Noted 14 THD+N vs. Frequency THD+N vs. Frequency Figure 45. Figure 46. THD+N vs. Amplitude THD+N vs. Amplitude Figure 47. Figure 48. Small Signal Step Response Large Signal Step Response Figure 49. Figure 50. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 APPLICATION HINTS BLOCK DIAGRAM AND OPERATIONAL DESCRIPTION A) Input Stage Figure 51. Simplified Schematic Diagram As can be seen from the simplified schematic in Figure 51, the input stage consists of two distinct differential pairs (Q1-Q2 and Q3-Q4) in order to accommodate the full Rail-to-Rail input common mode voltage range. The voltage drop across R5, R6, R7, and R8 is kept to less than 200mV in order to allow the input to exceed the supply rails. Q13 acts as a switch to steer current away from Q3-Q4 and into Q1-Q2, as the input increases beyond 1.4V of V+. This in turn shifts the signal path from the bottom stage differential pair to the top one and causes a subsequent increase in the supply current. In transitioning from one stage to another, certain input stage parameters (VOS, Ib, IOS, en, and in) are determined based on which differential pair is "on" at the time. Input Bias current, IB, will change in value and polarity as the input crosses the transition region. In addition, parameters such as PSRR and CMRR which involve the input offset voltage will also be effected by changes in VCM across the differential pair transition region. The input stage is protected with the combination of R9-R10 and D1, D2, D3, and D4 against differential input over-voltages. This fault condition could otherwise harm the differential pairs or cause offset voltage shift in case of prolonged over voltage. As shown in Figure 52, if this voltage reaches approximately ±1.4V at 25°C, the diodes turn on and current flow is limited by the internal series resistors (R9 and R10). The Absolute Maximum Rating of ±10V differential on VIN still needs to be observed. With temperature variation, the point were the diodes turn on will change at the rate of 5mV/°C. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 15 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 52. Input Stage Current vs. Differential Input Voltage B) Output Stage The output stage Figure 51 is comprised of complementary NPN and PNP common-emitter stages to permit voltage swing to within a VCE(SAT) of either supply rail. Q9 supplies the sourcing and Q10 supplies the sinking current load. Output current limiting is achieved by limiting the VCE of Q9 and Q10; using this approach to current limiting, alleviates the draw back to the conventional scheme which requires one VBE reduction in output swing. The frequency compensation circuit includes Miller capacitors from collector to base of each output transistor (see Figure 51, Ccomp9 and Ccomp10). At light capacitive loads, the high frequency gain of the output transistors is high, and the Miller effect increases the effective value of the capacitors thereby stabilizing the Op Amp. Large capacitive loads greatly decrease the high frequency gain of the output transistors thus lowering the effective internal Miller capacitance - the internal pole frequency increases at the same time a low frequency pole is created at the Op Amp output due to the large load capacitor. In this fashion, the internal dominant pole compensation, which works by reducing the loop gain to less than 0dB when the phase shift around the feedback loop is more than 180°C, varies with the amount of capacitive load and becomes less dominant when the load capacitor has increased enough. Hence the Op Amp is very stable even at high values of load capacitance resulting in the uncharacteristic feature of stability under all capacitive loads. DRIVING CAPACITIVE LOADS The LM8261 is specifically designed to drive unlimited capacitive loads without oscillations (See Settling Time and Percent Overshoot vs. Cap Load plot, Figure 32). In addition, the output current handling capability of the device allows for good slewing characteristics even with large capacitive loads (see Slew Rate vs. Cap Load plots). The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input amplifiers, etc. However, as in most Op Amps, addition of a series isolation resistor between the Op Amp and the capacitive load improves the settling and overshoot performance. Output current drive is an important parameter when driving capacitive loads. This parameter will determine how fast the output voltage can change. Referring to the Slew Rate vs. Cap Load Plots (Figure 33, Figure 34, Figure 35, and Figure 36), two distinct regions can be identified. Below about 10,000pF, the output Slew Rate is solely determined by the Op Amp's compensation capacitor value and available current into that capacitor. Beyond 10nF, the Slew Rate is determined by the Op Amp's available output current. Note that because of the lower output sourcing current compared to the sinking one, the Slew Rate limit under heavy capacitive loading is determined by the positive transitions. An estimate of positive and negative slew rates for loads larger than 100nF can be made by dividing the short circuit current value by the capacitor. 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 For the LM8261, the available output current increases with the input overdrive. Referring to Figure 53 and Figure 54, Output Short Circuit Current vs. Input Overdrive, it can be seen that both sourcing and sinking short circuit current increase as input overdrive increases. In a closed loop amplifier configuration, during transient conditions while the fed back output has not quite caught up with the input, there will be an overdrive imposed on the input allowing more output current than would normally be available under steady state condition. Because of this feature, the Op Amp's output stage quiescent current can be kept to a minimum, thereby reducing power consumption, while enabling the device to deliver large output current when the need arises (such as during transients). Figure 53. Output Short Circuit Sourcing Current vs. Input Overdrive Figure 54. Output Short Circuit Sinking Current vs. Input Overdrive Figure 55 shows the output voltage, output current, and the resulting input overdrive with the device set for AV = +1 and the input tied to a 1VPP step function driving a 47nF capacitor. As can be seen, during the output transition, the input overdrive reaches 1V peak and is more than enough to cause the output current to increase to its maximum value (see Figure 53 and Figure 54 plots). Note that because of the larger output sinking current compared to the sourcing one, the output negative transition is faster than the positive one. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 17 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 55. Buffer Amplifier scope photo ESTIMATING THE OUTPUT VOLTAGE SWING It is important to keep in mind that the steady state output current will be less than the current available when there is an input overdrive present. For steady state conditions, the Output Voltage vs. Output Current plot ( TYPICAL PERFORMANCE CHARACTERISTICS section) can be used to predict the output swing. Figure 56 and Figure 57 show this performance along with several load lines corresponding to loads tied between the output and ground. In each cases, the intersection of the device plot at the appropriate temperature with the load line would be the typical output swing possible for that load. For example, a 1KΩ load can accommodate an output swing to within 250mV of V− and to 330mV of V+ (VS = ±15V) corresponding to a typical 29.3VPP unclipped swing. Figure 56. Output Sourcing Characteristics with Load Lines 18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 Figure 57. Output Sinking Characteristics with Load Lines TFT APPLICATIONS Figure 58 below, shows a typical application where the LM8261 is used as a buffer amplifier for the VCOM signal employed in a TFT LCD flat panel: Figure 58. VCOM Driver Application Schematic Figure 59 shows the time domain response of the amplifier when used as a VCOM buffer/driver with VREF at ground. In this application, the Op Amp loop will try and maintain its output voltage based on the voltage on its non-inverting input (VREF) despite the current injected into the TFT simulated load. As long as this load current is within the range tolerable by the LM8261 (45mA sourcing and 65mA sinking for ±5V supplies), the output will settle to its final value within less than 2µs. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 19 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com Figure 59. VCOM driver performance scope photo OUTPUT SHORT CIRCUIT CURRENT AND DISSIPATION ISSUES The LM8261 output stage is designed for maximum output current capability. Even though momentary output shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher supply voltage conditions. Below supply voltage of 6V, output short circuit condition can be tolerated indefinitely. With the Op Amp tied to a load, the device power dissipation consists of the quiescent power due to the supply current flow into the device, in addition to power dissipation due to the load current. The load portion of the power itself could include an average value (due to a DC load current) and an AC component. DC load current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the Op Amp operates in a single supply application where the output is maintained somewhere in the range of linear operation. Therefore: PTOTAL = PQ + PDC + PAC PQ = IS · VS Op Amp Quiescent Power Dissipation PDC = IO · (VR - VO) DC Load Power PAC = See Table 1 below AC Load Power where: IS: Supply Current VS: Total Supply Voltage (V+ - V−) IO: Average load current VO: Average Output Voltage VR: V+ for sourcing and V− for sinking current Table 1 below shows the maximum AC component of the load power dissipated by the Op Amp for standard Sinusoidal, Triangular, and Square Waveforms: Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms PAC (W.Ω/V2) 20 Sinusoidal Triangular Square 50.7 x 10−3 46.9 x 10−3 62.5 x 10−3 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469I – APRIL 2000 – REVISED MARCH 2013 The table entries are normalized to VS2/ RL. To figure out the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS2/ RL. For example, with ±15V supplies, a 600Ω load, and triangular waveform power dissipation in the output stage is calculated as: PAC= (46.9 x 10−3) · [302/600]= 70.4mW Other Application Hints The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current Op Amps, best results are achieved when each supply line is decoupled with two capacitors; a small value ceramic capacitor (∼0.01µF) placed very close to the supply lead in addition to a large value Tantalum or Aluminum (> 4.7µF). The large capacitor can be shared by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as the charge "bucket" for fast load current spikes at the Op Amp output. The combination of these capacitors will provide supply decoupling and will help keep the Op Amp oscillation free under any load. LM8261 ADVANTAGES Compared to other Rail-to-Rail Input/Output devices, the LM8261 offers several advantages such as: • Improved cross over distortion. • Nearly constant supply current throughout the output voltage swing range and close to either rail. • Consistent stability performance for all input/output voltage and current conditions. • Nearly constant Unity gain frequency (fu) and Phase Margin (Phim) for all operating supplies and load conditions. • No output phase reversal under input overload condition. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 21 LM8261 SNOS469I – APRIL 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision H (March 2013) to Revision I • 22 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 21 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM8261 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM8261M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A45A LM8261M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A45A LM8261M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A45A LM8261M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A45A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM8261M5 SOT-23 DBV 5 1000 178.0 8.4 LM8261M5X SOT-23 DBV 5 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 3.2 3.2 1.4 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8261M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM8261M5X SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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