Megawin MPC82L52 Interrupt controller Datasheet

8051-Based MCU
MPC82E/L52
Data Sheet
Version: A10
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
 Megawin Technology Co., Ltd. 2005 All rights reserved.
2013/04 version A10
2
MPC82x52 Data Sheet
MEGAWIN
Features


1-T 80C51 Central Processing Unit
MPC82E/L52 with 8K Bytes flash ROM
━ ISP memory zone could be optioned as 1.0KB, 2.0KB or 3.0KB
━ Two level code protections for flash memory access
━ Flash write/erase cycle: 20,000
━ Flash data retention: 100 years at 25℃
━ MPC82E/L52 Flash space mapping (Default)
 AP Flash（0000h~17FFh）
 IAP Flash（1800h~1BFFh）
 ISP Flash（1C00h~1FFFh）（ISP Boot code）

On-chip 256 bytes scratch-pad RAM

Interrupt controller
━ 7 sources, four-level-priority interrupt capability
━ Two external interrupt inputs, INT0 and INT1

Two 16-bit timer/counters, Timer 0 and Timer 1.
━ X12 mode enabled for Timer 0/1

Programmable 16-bit counter/timer Array (PCA) with 2 channels PWM
━ Capture mode
━ 16-bit software timer mode
━ High speed output mode
━ 8-bit PWM mode

Enhanced UART (S0)
━ Framing Error Detection
━ Automatic Address Recognition

8-bit ADC
━ Programmable throughput up to 100 ksps
━ 8 channel single-ended inputs

Master/Slave SPI serial interface

Programmable Watchdog Timer, one time enabled by CPU or power-on

Maximum 15 GPIOs in 20-pin package.
━ Can be configured to quasi-bidirectional, push-pull output, open-drain output and input only.

Multiple power control modes: idle mode and power-down mode
━ All interrupts can wake up IDLE mode
━ 2 sources to wake up Power-Down mode

Low-Voltage Detector: VDD 3.7V for E-series and VDD 2.4V for L-series

Operating voltage range:
━ MPC82E52: 4.5V~5.5V, minimum 4.5V requirement in flash write operation (ISP/IAP)
━ MPC82L52: 2.4V~3.6V, minimum 2.7V requirement in flash write operation (ISP/IAP)

Operation frequency range: 25MHz(max)
━ MPC82E52: 0 – 25MHz @ 4.5V – 5.5V
━ MPC82L52: 0 – 12MHz @ 2.4V – 3.6V and 0 – 25MHz @ 2.7V – 3.6V

Clock Source
━ External crystal mode and Internal RC Oscillator (IRCO, 6MHz)

Operating Temperature:
━ Industrial (-40℃ to +85℃)*

Package Types:
━ PDIP20: MPC82E/L52AE
━ SOP20: MPC82E/L52AS
MEGAWIN
MPC82x52 Data Sheet
3
━
TSSOP20: MPC82E/L52AT
*: Tested by sampling.
4
MPC82x52 Data Sheet
MEGAWIN
MEGAWIN
MPC82x52 Data Sheet
5
Content
Features............................................................................................................. 3
Content .............................................................................................................. 6
1. General Description ..................................................................................... 10
2. Block Diagram ............................................................................................. 11
3. Special Function Register ............................................................................ 12
3.1.
3.2.
SFR Map ...................................................................................................................... 12
SFR Bit Assignment ..................................................................................................... 13
4. Pin Configurations ....................................................................................... 14
4.1.
4.2.
Package Instruction ...................................................................................................... 14
Pin Description ............................................................................................................. 15
5. 8051 CPU Function Description ................................................................... 16
5.1.
5.2.
5.3.
CPU Register ............................................................................................................... 16
CPU Timing .................................................................................................................. 17
CPU Addressing Mode ................................................................................................. 18
6. Memory Organization .................................................................................. 19
6.1.
6.2.
6.3.
On-Chip Program Flash ................................................................................................ 19
On-Chip Data RAM....................................................................................................... 20
Declaration Identifiers in a C51-Compiler ..................................................................... 23
7. Data Pointer Register (DPTR)...................................................................... 24
8. System Clock ............................................................................................... 25
8.1.
8.2.
8.3.
Clock Structure ............................................................................................................. 25
Clock Register .............................................................................................................. 26
Clock Sample Code ...................................................................................................... 27
9. Watch Dog Timer (WDT) ............................................................................. 28
9.1.
9.2.
9.3.
9.4.
9.5.
WDT Structure .............................................................................................................. 28
WDT During Idle and Power Down ............................................................................... 28
WDT Register ............................................................................................................... 29
WDT Hardware Option ................................................................................................. 30
WDT Sample Code....................................................................................................... 31
10. System Reset .............................................................................................. 32
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
Reset Source................................................................................................................ 32
Power-On Reset ........................................................................................................... 32
External Reset .............................................................................................................. 33
Software Reset ............................................................................................................. 33
Low-Voltage Reset ....................................................................................................... 33
WDT Reset ................................................................................................................... 34
Illegal Address Reset .................................................................................................... 34
Reset Sample Code ..................................................................................................... 35
11. Power Management ..................................................................................... 36
11.1.
11.2.
11.2.1.
11.2.2.
11.2.3.
11.2.4.
11.3.
11.4.
Low-Voltage Detector ................................................................................................... 36
Power Saving Mode ..................................................................................................... 37
Idle Mode ..............................................................................................................................37
Power-Down Mode ...............................................................................................................37
Interrupt Recovery from Power-down ...................................................................................38
Reset Recovery from Power-down .......................................................................................38
Power Control Register................................................................................................. 39
Power Control Sample Code ........................................................................................ 40
12. Configurable I/O Ports ................................................................................. 41
12.1.
6
IO Structure .................................................................................................................. 41
MPC82x52 Data Sheet
MEGAWIN
12.1.1.
12.1.2.
12.1.3.
12.1.4.
12.2.
12.2.1.
12.2.2.
12.3.
Quasi-Bidirectional IO Structure ...........................................................................................41
Push-Pull Output Structure ...................................................................................................42
Input-Only (High Impedance Input) Structure .......................................................................42
3 Open-Drain Output Structure .............................................................................................43
I/O Port Register ........................................................................................................... 44
Port 1 Register ......................................................................................................................44
Port 3 Register ......................................................................................................................44
GPIO Sample Code ...................................................................................................... 46
13. Interrupt ....................................................................................................... 47
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
Interrupt Structure......................................................................................................... 47
Interrupt Source ............................................................................................................ 49
Interrupt Enable ............................................................................................................ 50
Interrupt Priority ............................................................................................................ 50
Interrupt Process .......................................................................................................... 51
Interrupt Register .......................................................................................................... 52
Interrupt Sample Code.................................................................................................. 54
14. Timers/Counters .......................................................................................... 55
14.1.
14.1.1.
14.1.2.
14.1.3.
14.1.4.
14.1.5.
14.1.6.
Timer0 and Timer1 ....................................................................................................... 55
Mode 0 Structure ..................................................................................................................55
Mode 1 Structure ..................................................................................................................56
Mode 2 Structure ..................................................................................................................57
Mode 3 Structure ..................................................................................................................58
Timer0/1 Register .................................................................................................................59
Timer0/1 Sample Code .........................................................................................................61
15. Serial Port (UART) ....................................................................................... 63
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
15.7.
15.7.1.
15.7.2.
15.7.3.
15.8.
15.9.
Serial Port Mode 0 ........................................................................................................ 64
Serial Port Mode 1 ........................................................................................................ 66
Serial Port Mode 2 and Mode 3 .................................................................................... 67
Frame Error Detection .................................................................................................. 67
Multiprocessor Communications ................................................................................... 68
Automatic Address Recognition .................................................................................... 68
Baud Rate Setting ........................................................................................................ 70
Baud Rate in Mode 0 ............................................................................................................70
Baud Rate in Mode 2 ............................................................................................................70
Baud Rate in Mode 1 & 3 ......................................................................................................70
Serial Port Register ...................................................................................................... 73
Serial Port Sample Code .............................................................................................. 75
16. Programmable Counter Array (PCA) ........................................................... 77
16.1.
16.2.
16.3.
16.4.
16.4.1.
16.4.2.
16.4.3.
16.4.4.
16.5.
PCA Overview .............................................................................................................. 77
PCA Timer/Counter ...................................................................................................... 78
Compare/Capture Modules ........................................................................................... 80
Operation Modes of the PCA ........................................................................................ 82
Capture Mode .......................................................................................................................82
16-bit Software Timer Mode..................................................................................................83
High Speed Output Mode .....................................................................................................84
PWM Mode ...........................................................................................................................85
PCA Sample Code ....................................................................................................... 86
17. Serial Peripheral Interface (SPI) .................................................................. 87
17.1.
17.1.1.
17.1.2.
17.1.3.
17.2.
17.2.1.
17.2.2.
17.2.3.
17.2.4.
MEGAWIN
Typical SPI Configurations ........................................................................................... 88
Single Master & Single Slave................................................................................................88
Dual Device, where either can be a Master or a Slave ........................................................88
Single Master & Multiple Slaves ...........................................................................................89
Configuring the SPI ...................................................................................................... 90
Additional Considerations for a Slave ...................................................................................90
Additional Considerations for a Master .................................................................................90
Mode Change on nSS-pin.....................................................................................................91
Write Collision .......................................................................................................................91
MPC82x52 Data Sheet
7
17.2.5.
17.3.
17.4.
17.5.
SPI Clock Rate Select ...........................................................................................................91
Data Mode .................................................................................................................... 92
SPI Register ................................................................................................................. 94
SPI Sample Code ......................................................................................................... 96
18. 8-Bit ADC................................................................................................... 100
18.1.
18.2.
18.2.1.
18.2.2.
18.2.3.
18.2.4.
18.2.5.
18.3.
18.4.
ADC Structure ............................................................................................................ 100
ADC Operation ........................................................................................................... 100
ADC Input Channels ...........................................................................................................101
Starting a Conversion .........................................................................................................101
ADC Conversion Time ........................................................................................................101
I/O Pins Used with ADC Function .......................................................................................101
Idle and Power-Down Mode................................................................................................101
ADC Register ............................................................................................................. 102
ADC Sample Code ..................................................................................................... 103
19. ISP and IAP ............................................................................................... 105
19.1.
19.2.
19.2.1.
19.2.2.
19.2.3.
19.3.
19.3.1.
19.3.2.
19.3.3.
19.3.4.
19.4.
19.4.1.
19.4.2.
19.4.3.
19.5.
19.6.
MPC82E/L52 Flash Memory Configuration ................................................................. 105
MPC82E/L52 Flash Access in ISP/IAP ....................................................................... 106
ISP/IAP Flash Page Erase Mode ........................................................................................106
ISP/IAP Flash Program Mode .............................................................................................108
ISP/IAP Flash Read Mode ..................................................................................................110
ISP Operation ............................................................................................................. 112
Hardware approached ISP ..................................................................................................112
Software approached ISP ...................................................................................................113
Notes for ISP .......................................................................................................................114
Default ISP Code in MPC82E/L52 ......................................................................................115
In-Application-Programming (IAP) .............................................................................. 116
IAP-memory Boundary/Range ............................................................................................116
Update data in IAP-memory................................................................................................116
Notes for IAP .......................................................................................................................117
ISP/IAP Register......................................................................................................... 118
ISP/IAP Sample Code ................................................................................................ 120
20. Auxiliary SFRs ........................................................................................... 123
21. Hardware Option........................................................................................ 124
22. Application Notes ....................................................................................... 126
22.1.
22.2.
22.3.
22.4.
Power Supply Circuit .................................................................................................. 126
Reset Circuit ............................................................................................................... 126
XTAL Oscillating Circuit .............................................................................................. 127
ISP Interface Circuit .................................................................................................... 128
23. Electrical Characteristics............................................................................ 129
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
Absolute Maximum Rating .......................................................................................... 129
DC Characteristics...................................................................................................... 130
External Clock Characteristics .................................................................................... 132
IRCO Characteristics .................................................................................................. 133
Flash Characteristics .................................................................................................. 133
Serial Port Timing Characteristics ............................................................................... 134
SPI Timing Characteristics ......................................................................................... 135
24. Instruction Set ............................................................................................ 137
25. Package Dimension ................................................................................... 140
25.1.
25.2.
25.3.
DIP-20 ........................................................................................................................ 140
SOP-20 ...................................................................................................................... 141
TSSOP-20 .................................................................................................................. 142
26. Revision History ......................................................................................... 143
8
MPC82x52 Data Sheet
MEGAWIN
MEGAWIN
MPC82x52 Data Sheet
9
1. General Description
The MPC82E/L52 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
executes instructions in 1~6 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051
compatible instruction set. Therefore at the same performance as the standard 8051, the MPC82E/L52 can
operate at a much lower speed and thereby greatly reduce the power consumption.
The MPC82E/L52 has 8K bytes of embedded Flash memory for code and data. The Flash memory can be
programmed either in parallel writer mode or in ISP (In-System Programming) mode. And, it also provides the InApplication Programming (IAP) capability. ISP allows the user to download new code without removing the
microcontroller from the actual end product; IAP means that the device can write non-volatile data in the Flash
memory while the application program is running. There needs no external high voltage for programming due to
its built-in charge-pumping circuitry.
The MPC82E/L52 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, two I/O ports,
two external interrupts, a multi-source 4-level interrupt controller and two 16-bits timer/counters. In addition, the
MPC82E/L52 has one 8-btis ADC, a 2-channel PCA, SPI, Watchdog Timer, a Low-Voltage Detector, an on-chip
crystal oscillator, an internal oscillator (IRCO, 6MHz), and a more versatile serial channel that facilitates
multiprocessor communication (EUART).
The MPC82E/L52 has multiple operating modes to reduce the power consumption: idle mode and power down
mode. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the
Power-Down mode the RAM and SFRs‘ value are saved and all other functions are inoperative; most importantly,
in the Power-down mode the device can be waked up by many interrupt or reset sources.
10
MPC82x52 Data Sheet
MEGAWIN
2. Block Diagram
Figure 2–1. Block Diagram
XTAL1
XTAL2
XTAL
OSC
IRCO
6MHz
8051 CPU (1T)
RST
Flash
8K X 8
WDT
(P3.2) INT0
(P3.3) INT1
(P3.0) RXD
(P3.1) TXD
(P3.4) T0
(P3.5) T1
RAM
256 X 8
UART
Timer0
Timer1
ISP/IAP
(P3.4) ECI
CEX1~0
(P3.5, P3.7)
(PWM x 2)
AIN0~AIN7
(P1.0~P1.7)
8-bit ADC
(P1.4) nSS
(P1.5) MOSI
(P1.6) MISO
(P1.7) SPICLK
MEGAWIN
Ext. INT
Port1
P1.0~P1.7
Port3
P3.0~P3.5,
P3.7
PCA
LVD
SPI
MPC82x52 Data Sheet
11
3. Special Function Register
3.1. SFR Map
Table 3–1. SFR Map
0/8
1/9
F8
-CH
F0
B
-E8
-CL
E0
ACC
WDTCR
D8
CCON
CMOD
D0
PSW
-C8
--C0
--B8
IP
SADEN
B0
P3
P3M0
A8
IE
SADDR
A0
--98
SCON
SBUF
90
P1
P1M0
88
TCON
TMOD
80
-SP
0/8
1/9
12
2/A
CCAP0H
PCAPWM0
CCAP0L
IFD
CCAPM0
----P3M1
---P1M1
TL0
DPL
2/A
3/B
CCAP1H
PCAPWM1
CCAP1L
IFADRH
CCAPM1
---------TL1
DPH
3/B
4/C
---IFADRL
---------TH0
SPISDAT
4/C
MPC82x52 Data Sheet
5/D
---IFMT
---ADCTL
------TH1
SPICTL
5/D
6/E
---SCMD
---ADCV
------AUXR
SPIDAT
6/E
7/F
---ISPCR
---PCON2
-IPH
-----PCON
7/F
MEGAWIN
3.2. SFR Bit Assignment
Table 3–2. SFR Bit Assignment
SYMBOL
DESCRIPTION
ADDR
BIT ADDRESS AND SYMBOL
Bit-7
SP
DPL
DPH
SPISTAT
SPICON
SPIDAT
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
AUXR
P1
P1M0
P1M1
SCON
SBUF
Stack Pointer
Data Pointer Low
Data Pointer High
SPI Status Register
SPI Control Register
SPI Data Register
Power Control Reg.
Timer Control
Timer Mode
Timer Low 0
Timer Low 1
Timer High 0
Timer High 1
Auxiliary Register
Port 1
P1 Mode Register 0
P1 Mode Register 1
Serial Control
Serial Buffer
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
90H
91H
92H
98H
99H
IE
Interrupt Enable
A8H
EA
SADDR
P3
P3M0
P3M1
Slave Address
Port 3
P3 Mode Register 0
P3 Mode Register 1
A9H
B0H
B1H
B2H
P3.7
P3M0.7
P3M1.7
IPH
Interrupt Priority High
B7H
--
IP
Interrupt Priority Low
B8H
--
SADEN
ADCTL
ADCV
Slave Address Mask
ADC Control
ADC Result Register
Power Control 2
PCON2
Reg.
PSW
Program Status Word
CCON
PCA Control Reg.
CMOD
PCA Mode Reg.
CCAPM0
PCA Module0 Mode
CCAPM1
PCA Module1 Mode
ACC
Accumulator
Watch-dog-timer
WDTCR
Control register
IFD
ISP Flash data
ISP Flash address
IFADRH
High
ISP Flash Address
IFADRL
Low
IFMT
ISP Mode Table
SCMD
ISP Serial Command
ISPCR
ISP Control Register
CL
PCA base timer Low
PCA module0 capture
CCAP0L
Low
PCA module1 capture
CCAP1L
Low
B
B Register
PCAPWM0 PCA PWM0 Mode
PCAPWM1 PCA PWM1 Mode
CH
PCA base timer High
PCA Module0 capture
CCAP0H
High
PCA Module1 capture
CCAP1H
High
MEGAWIN
B9H
C5H
C6H
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
RESET
VALUE
00000111B
00000000B
00000000B
-00xxxxxxB
SPR0 00000100B
00000000B
IDL
00110000B
IT0
00000000B
M0
00000000B
00000000B
00000000B
00000000B
00000000B
-000000xxB
P1.0 11111111B
P1M0.0 00000000B
P1M1.0 00000000B
RI
00000000B
xxxxxxxxB
SPIF
SSIG
WCOL
SPEN
-DORD
-MSTR
-CPOL
-CPHA
-SPR1
SMOD
TF1
GATE
SMOD0
TR1
C/T
LVF
TF0
M1
POF
TR0
M0
GF1
IE1
GATE
GF0
IT1
C/T
PD
IE0
M1
ESPI
P1.3
P1M0.3
P1M1.3
TB8
ENLVFI
P1.2
P1M0.2
P1M1.2
RB8
-P1.1
P1M0.1
P1M1.1
TI
ES
ET1
EX1
ET0
P3.4
P3M0.4
P3M1.4
P3.3
P3M0.3
P3M1.3
P3.2
P3M0.2
P3M1.2
P3.1
P3M0.1
P3M1.1
PSH
PT1H
PX1H
PT0H
PX0H
x0000000B
PSL
PT1L
PX1L
PT0L
PX0L
x0000000B
T0X12
P1.7
P1M0.7
P1M1.7
SM0/FE
T1X12 URM0X6 EADCI
P1.6
P1.5
P1.4
P1M0.6 P1M0.5 P1M0.4
P1M1.6 P1M1.5 P1M1.4
SM1
SM2
REN
EPCA_
LVD
ESPI_
ADC
---PPCA_
LVD
PPCA_
LVD
P3.5
P3M0.5
P3M1.5
PSPI_
ADC
PSPI_
ADC
EX0
00000000B
00000000B
P3.0 1x111111B
P3M0.0 0x000000B
P3M1.0 0x000000B
00000000B
ADCON SPEED1 SPEED0 ADCI
ADCS
CHS2
CHS1
CHS0 00000000B
ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 ADCV.1 ADCV.0 xxxxxxxxB
C7H
--
--
--
--
--
CKS2
CKS1
CKS0
xxxxx000B
D0H
D8H
D9H
DAH
DBH
E0H
CY
CF
CIDL
--ACC.7
AC
CR
-ECOM0
ECOM1
ACC.6
F0
--CAPP0
CAPP1
ACC.5
RS1
--CAPN0
CAPN1
ACC.4
RS0
--MAT0
MAT1
ACC.3
OV
-CPS1
TOG0
TOG1
ACC.2
F1
CCF1
CPS0
PWM0
PWM1
ACC.1
P
CCF0
ECF
ECCF0
ECCF1
ACC.0
E1H
WRF
--
ENW
CLW
WIDL
PS2
PS1
PS0
E2H
00000000B
00xxxx00B
0xxxx000B
x0000000B
x0000000B
00000000B
0x000000B
xxx0xxxxB
11111111B
E3H
00000000B
E4H
00000000B
E5H
E6H
E7H
E9H
--
--
--
--
--
--
MS1
ISPEN
CL.7
SWBS
CL.6
SWRST
CL.5
CFAIL
CL.4
-CL.3
WAIT.2
CL.2
WAIT.1
CL.1
MS0
xxxxxx00B
xxxxxxxxB
WAIT.0 0000x000B
CL.0 00000000B
EAH
00000000B
EBH
00000000B
F0H
F2H
F3H
F9H
B.7
--CH.7
B.6
--CH.6
B.5
--CH.5
B.4
--CH.4
B.3
--CH.3
B.2
--CH.2
B.1
EPC0H
EPC1H
CH.1
B.0
EPC0L
EPC1L
CH.0
00000000B
xxxxxx00B
xxxxxx00B
00000000B
FAH
00000000B
FBH
00000000B
MPC82x52 Data Sheet
13
4. Pin Configurations
4.1. Package Instruction
Figure 4–1. MPC82E/L52 20-Pin Top View
RST
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
(INT0) P3.2
(INT1) P3.3
(ECI)(T0) P3.4
(CEX1)(T1) P3.5
VSS
14
1
2
3
4
5
6
7
8
9
10
PDIP20
SOP20
TSSOP20
20
19
18
17
16
15
14
13
12
11
MPC82x52 Data Sheet
VDD
P1.7 (AIN7)(SPICLK)
P1.6 (AIN6)(MISO)
P1.5 (AIN5)(MOSI)
P1.4 (AIN4)(nSS)
P1.3 (AIN3)
P1.2 (AIN2)
P1.1 (AIN1)
P1.0 (AIN0)
P3.7 (CEX0)
MEGAWIN
4.2. Pin Description
Table 4–1. Pin Description
PIN NUMBER
MNEMONIC
P1.0
(AIN0)
P1.1
(AIN1)
P1.2
(AIN2)
P1.3
(AIN3)
P1.4
(AIN4)
(nSS)
P1.5
(AIN5)
(MOSI)
P1.6
(AIN6)
(MISO)
P1.7
(AIN7)
(SPICLK)
P3.0
(RXD)
P3.1
(TXD)
P3.2
(INT0)
P3.3
(INT1)
P3.4
(T0)
(ECI)
P3.5
(T1)
(CEX1)
P3.7
(CEX0)
XTAL2
XTAL1
RST
VDD
VSS
MEGAWIN
I/O
TYPE
20-Pin
PDIP
20-Pin
SOP
20-Pin
12
12
12
I/O
13
13
13
I/O
14
14
14
I/O
15
15
15
I/O
16
16
16
I/O
17
17
17
I/O
18
18
18
I/O
19
19
19
I/O
2
2
2
I/O
3
3
3
I/O
6
6
6
I/O
7
7
7
I/O
8
8
8
I/O
9
9
9
I/O
11
11
11
I/O
4
5
1
20
10
4
5
1
20
10
4
5
1
20
10
O
I
I
P
G
TSSOP
DESCRIPTION
* Port 1.0.
* AIN0: ADC channel-0 analog input.
* Port 1.1.
* AIN1: ADC channel-1 analog input.
* Port 1.2.
* AIN2: ADC channel-2 analog input.
* Port 1.3.
* AIN3: ADC channel-3 analog input.
* Port 1.4.
* AIN4: ADC channel-4 analog input.
* nSS: SPI Slave select.
* Port 1.5.
* AIN5: ADC channel-5 analog input.
* MOSI: SPI master out & slave in.
* Port 1.6.
* AIN6: ADC channel-6 analog input.
* MISO: SPI master in & slave out.
* Port 1.7.
* AIN7: ADC channel-7 analog input.
* SPICLK: SPI clock, output for master and input for slave.
* Port 3.0.
* RXD: UART serial input port.
* Port 3.1.
* TXD: UART serial output port.
* Port 3.2.
* INT0: external interrupt 0 input.
* Port 3.3.
* INT1: external interrupt 1 input.
* Port 3.4.
* T0: Timer/Counter 0 external input.
* ECI: PCA external clock input.
* Port 3.5.
* T1: Timer/Counter 1 external input.
* CEX1: PCA module-1 external I/O.
* Port 3 bit-7.
* CEX0: PCA module-0 external I/O.
* XTAL2: Output of on-chip crystal oscillating circuit.
* XTAL1: Input of on-chip crystal oscillating circuit.
* RST: External RESET input, high active.
Power supply input. 5V input for E-type. 3.3V input for L-type.
Ground, 0 V reference.
MPC82x52 Data Sheet
15
5. 8051 CPU Function Description
5.1. CPU Register
PSW: Program Status Word
SFR Address = 0xD0
7
6
5
CY
AC
F0
R/W
R/W
R/W
4
RS1
R/W
RESET = 0000-0000
3
2
RS0
OV
R/W
R/W
1
F1
0
P
R/W
R/W
CY: Carry bit.
AC: Auxiliary carry bit.
F0: General purpose flag 0.
RS1: Register bank select bit 1.
RS0: Register bank select bit 0.
OV: Overflow flag.
F1: General purpose flag 1.
P: Parity bit.
The program status word(PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
―Accumulator‖ for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in Section ―6.2 On-Chip Data
RAM‖. A number of instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
SP: Stack Pointer
SFR Address = 0x81
7
6
SP.7
SP.6
R/W
R/W
5
SP.5
4
SP.4
R/W
R/W
RESET = 0000-0111
3
2
SP.3
SP.2
R/W
R/W
1
SP.1
0
SP.0
R/W
R/W
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH
operation. The SP register defaults to 0x07 after reset.
DPL: Data Pointer Low
SFR Address = 0x82
7
6
DPL.7
DPL.6
R/W
R/W
5
DPL.6
4
DPL.4
R/W
R/W
RESET = 0000-0000
3
2
DPL.3
DPL.2
R/W
R/W
1
DPL.1
0
DPL.0
R/W
R/W
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and
Flash memory.
DPH: Data Pointer High
SFR Address = 0x83
7
6
DPH.7
DPH.6
R/W
R/W
5
DPH.5
4
DPH.4
R/W
R/W
RESET = 0000-0000
3
2
DPH.3
DPH.2
R/W
R/W
1
DPH.1
0
DPH.0
R/W
R/W
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and
Flash memory.
16
MPC82x52 Data Sheet
MEGAWIN
ACC: Accumulator
SFR Address = 0xE0
7
6
ACC.7
ACC.6
R/W
R/W
5
ACC.5
4
ACC.4
R/W
R/W
RESET = 0000-0000
3
2
ACC.3
ACC.2
1
ACC.1
0
ACC.0
R/W
R/W
R/W
RESET = 0000-0000
3
2
B.3
B.2
1
B.1
0
B.0
R/W
R/W
R/W
This register is the accumulator for arithmetic operations.
B: B Register
SFR Address = 0xF0
7
6
B.7
B.6
R/W
R/W
5
B.5
4
B.4
R/W
R/W
R/W
R/W
This register serves as a second accumulator for certain arithmetic operations.
5.2. CPU Timing
The MPC82E/L52 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
has an 8051 compatible instruction set, and executes instructions in 1~6 clock cycles (about 6~7 times the rate of
a standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over
the standard 8051 architecture. The instruction timing is different than that of the standard 8051.
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine
cycles varying from 2 to 12 clock cycles in length. However, the 1T-80C51 implementation is based solely on
clock cycle timing. All instruction timings are specified in terms of clock cycles. For more detailed information
about the 1T-80C51 instructions, please refer Section ―24 Instruction Set‖ which includes the mnemonic, number
of bytes, and number of clock cycles for each instruction.
MEGAWIN
MPC82x52 Data Sheet
17
5.3. CPU Addressing Mode
Direct Addressing(DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM
and SFRs can be direct addressed.
Indirect Addressing(IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR.
Register Instruction(REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3bit register specification within the op-code of the instruction. Instructions that access the registers this way are
code efficient because this mode eliminates the need of an extra address byte. When such instruction is
executed, one of the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer, etc. No address byte is needed for such instructions. The op-code itself does it.
Immediate Constant(IMM)
The value of a constant can follow the op-code in the program memory.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode
is intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or PC) points to
the base of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.
18
MPC82x52 Data Sheet
MEGAWIN
6. Memory Organization
Like all 80C51 devices, the MPC82E/L52 has separate address spaces for program and data memory. The
logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses,
which can be quickly stored and manipulated by the 8-bit CPU.
Program memory (ROM) can only be read, not written to. There can be up to 8K bytes of program memory. In
the MPC82E/L52, all the program memory are on-chip Flash memory, and without the capability of accessing
external program memory because of no External Access Enable (/EA) and Program Store Enable (/PSEN)
signals designed.
Data memory occupies a separate address space from program memory. In the MPC82E/L52, there is only a
256 bytes of internal scratch-pad RAM.
6.1. On-Chip Program Flash
Program memory is the memory which stores the program codes for the CPU to execute, as shown in Figure 6–1.
After reset, the CPU begins execution from location 0000H, where should be the starting of the user‘s application
code. To service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the
program memory. Each interrupt is assigned a fixed location in the program memory. The interrupt causes the
CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must begin
at location 0003H. If the interrupt is not going to be used, its service location is available as general purpose
program memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for
Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as
is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines
can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
Figure 6–1. Program Memory
Program
Memory
1FFFH
Interrupt
Locations
001BH
0013H
000BH
8 bytes
0003H
Reset
MEGAWIN
0000H
MPC82x52 Data Sheet
19
6.2. On-Chip Data RAM
Figure 6–2 shows the internal data memory space available to the MPC82E/L52 user. Internal data memory can
be divided into three blocks, which are generally referred to as the lower 128 bytes of RAM, the upper 128 bytes
of RAM, and the 128 bytes of SFR space. Internal data memory addresses are always 8-bit wide, which implies
an address space of only 256 bytes. Direct addresses higher than 7FH access the SFR space; and indirect
addresses higher than 7FH access the upper 128 bytes of RAM. Thus the SFR space and the upper 128 bytes of
RAM occupy the same block of addresses, 80H through FFH, although they are physically separate entities.
The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Figure 6–3. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in
the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes
above the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a
wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128 can
only be accessed by indirect addressing.
20
MPC82x52 Data Sheet
MEGAWIN
Figure 6–4 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers,
peripheral controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR
space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
Figure 6–2. Data Memory
Internal 256 Bytes
SRAM
SFRs
FFH
FFH
Addressable by
Indirect Addressing
Only
Upper 128
Bytes
Addressable by
Direct Addressing
(SFRs)
80H
7FH
80H
Addressable by
Direct and Indirect
Addressing
Lower 128
Bytes
00H
Figure 6–3. Lower 128 Bytes of Internal RAM
Lower 128 Bytes of
internal SRAM
7FH
30H
2FH
Bit Addressable
20H
Four banks of 8
registers R0~R7
MEGAWIN
18H
Bank 3
1FH
10H
Bank 2
17H
08H
Bank 1
0FH
00H
Bank 0
07H
MPC82x52 Data Sheet
Reset value of
Stack Pointer
21
Figure 6–4. SFR Space
FFH
E0H
ACC
D0H
PSW
B0H
Port 3
90H
Port 1
1. I/O ports are register mapping
2. Addresses that end in 0H or
8H are also bit-addressable
- I/O ports
- PSW
- Accumulator
(etc.)
80H
22
MPC82x52 Data Sheet
MEGAWIN
6.3. Declaration Identifiers in a C51-Compiler
The declaration identifiers in a C51-compiler for the various MPC82E/L52 memory spaces are as follows:
data
128 bytes of internal data memory space (00h~7Fh); accessed via direct or indirect addressing, using instructions
other than MOVX and MOVC. All or part of the Stack may be in this area.
idata
Indirect data; 256 bytes of internal data memory space (00h~FFh) accessed via indirect addressing using
instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the data
area and the 128 bytes immediately above it.
sfr
Special Function Registers; CPU registers and peripheral control/status registers, accessible only via direct
addressing.
xdata
There is no on-chip XRAM or XRAM interface for xdata access.
pdata
There is no on-chip XRAM or XRAM interface for pdata access.
code
8K bytes of program memory space; accessed as part of program execution and via the ―MOVC @A+DTPR‖
instruction.
MEGAWIN
MPC82x52 Data Sheet
23
7. Data Pointer Register (DPTR)
There is only one set DPTR in MPC82E/L52. MPC82E/L52 does not support external memory access.
24
MPC82x52 Data Sheet
MEGAWIN
8. System Clock
There are two clock sources for the system clock: external crystal oscillator and Internal RC Oscillator (IRCO).
Figure 8–1 shows the structure of the system clock in MPC82E/L52.
The MPC82E/L52 can boot from external crystal oscillator or IRCO on 6MHz which is selected by hardware
option control bit, ENROSC. The ENROSC is enabled or disabled by general writer or Megawin proprietary writer.
The built-in IRCO provides 6MHz frequency. To find the detailed IRCO performance, please refer Section ―23.4
IRCO Characteristics‖).
The system clock in IDLE mode is obtained from one of these two clock sources through the clock divider, as
shown in Figure 8–1. The user can program the divider control bits CKS2~CKS0 (in PCON2 register) to get the
desired system clock. That is, the CKS2~CKS0 control bits are only active in IDLE mode.
8.1. Clock Structure
Figure 8–1 presents the principal clock systems in the MPC82E/L52. The system clock can be sourced by the
external oscillator circuit or either internal oscillator.
Figure 8–1. System Clock
XTAL1
XTAL2
WAIT[2:0]
Oscillating
Circuit
0
IROC
(6MHz)
ISP/IAP Logic
(ISPCR.2~0)
OSCin
0
1
CKS[2:0]
(PCON2.2~0)
1
SYSCLK
(System Clock)
Hardware Option: ENROSC
PCON.IDL
MEGAWIN
MPC82x52 Data Sheet
25
8.2. Clock Register
PCON2: Power Control Register 2
SFR Address = 0xC7
7
6
5
4
0
0
0
0
W
W
W
W
RESET = xxxx-x000
3
2
0
CKS2
W
R/W
1
CKS1
0
CKS0
R/W
R/W
Bit 7~3: Reserved. Software must write ―0‖ on these bits when PCON2 is written.
Bit 2~0: CKS2 ~ CKS0, programmable System Clock Selection in IDLE mode. The default value of CKS[2:0] is
set to ―000‖ to select system clock on OSCin/1.
CKS[2:0]
System Clock in idle mode
0 0 0
OSCin/1
0 0 1
OSCin /2
0 1 0
OSCin /4
0 1 1
OSCin /8
1 0 0
OSCin /16
1 0 1
OSCin /32
1 1 0
OSCin /64
1 1 1
OSCin /128
26
MPC82x52 Data Sheet
MEGAWIN
8.3. Clock Sample Code
(1). Required Function: Switch SYSCLK to OSCin/128 for IDLE mode (default is OSCin/1)
Assembly Code Example:
CKS0
EQU
CKS1
EQU
CKS2
EQU
ORL
01h
02h
04h
PCON2,#( CKS2 + CKS1 + CKS0) ; Set CKS[2:0] = ―111‖ to select OSCin/128
C Code Example:
#define CKS0
#define CKS1
#define CKS2
0x01
0x02
0x04
PCON2 &= (CKS2 | CKS1 | CKS0);
// System clock divider /128
// CKS[2:0], system clock divider
// 0 | OSCin/1
// 1 | OSCin/2
// 2 | OSCin/4
// 3 | OSCin/8
// 4 | OSCin/16
// 5 | OSCin/32
// 6 | OSCin/64
// 7 | OSCin/128
MEGAWIN
MPC82x52 Data Sheet
27
9. Watch Dog Timer (WDT)
9.1. WDT Structure
The Watch-dog Timer (WDT) is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 15-bit free-running counter, a 8-bit prescaler and a control register
(WDTCR). Figure 9–1 shows the WDT structure in MPC82E/L52.
When WDT is enabled, it derives its time base from the SYSCLK/12. The WDT overflow will trigger a system
reset and set the WRF on WDTCR.7. To prevent WDT overflow, software needs to clear it by writing ―1‖ to the
CLRW bit (WDTCR.4) before WDT overflows.
Once the WDT is enabled by setting ENW bit, there is no way to disable it except through power-on reset. The
WDTCR register will keep the previous programmed value unchanged after external reset (RST-pin), software
reset and WDT reset.
ENW is implemented to one-time-enabled function, only writing ―1‖ valid. Please refer Section ―9.3 WDT Register‖
for more detail information.
Figure 9–1. Watch Dog Timer
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
SYSCLK/12
PCON.IDL
15-bits WDT
WDT Reset
8-bits prescaler
WDTCR Register
WRF
--
ENW
CLRW
WIDL
PS2
PS1
PS0
9.2. WDT During Idle and Power Down
In the Idle mode, the WIDL bit (WDTCR.3) determines whether WDT counts or not. Set this bit to let WDT keep
counting in the Idle mode. If the hardware option WDTRCO is enabled, the WDT always keeps counting
regardless of WIDL bit.
In the Power-Down mode, WDT is frozen which is caused by stopped SYSCLK. After MCU wake-up, WDT
continues the counting by SYSCLK resumed.
28
MPC82x52 Data Sheet
MEGAWIN
9.3. WDT Register
WDTCR: Watch-Dog-Timer Control Register
SFR Address = 0xE1
POR = 0000-0111 (xxx0_xxxx by Hardware Option)
7
6
5
4
3
2
1
0
WRF
-ENW
CLRW
WIDL
PS2
PS1
PS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.
Bit 6: Reserved. Software must write ―0‖ on this bit when WDTCR is written.
Bit 5: ENW. Enable WDT.
0: Disable WDT running.
1: Enable WDT while it is set. Once ENW has been set, it can not be cleared by software.
Bit 4: CLRW. Clear WDT counter.
0: Writing ―0‖ to this bit is no operation in WDT.
1: Writing ―1‖ to this bit will clear the 15-bit WDT counter to 000H. Note this bit has no need to be cleared by
writing ―0‖.
Bit 3: WIDL. WDT idle control.
0: WDT stops counting while the MCU is in idle mode.
1: WDT keeps counting while the MCU is in idle mode.
Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input.
PS[2:0]
Prescaler Value
WDT period (if SYSCLK= 12MHz)
0 0 0
2
65.5ms
0 0 1
4
131ms
0 1 0
8
262ms
0 1 1
16
524ms
1 0 0
32
1.05S
1 0 1
64
2.10S
1 1 0
128
4.19S
1 1 1
256
8.39S
MEGAWIN
MPC82x52 Data Sheet
29
9.4. WDT Hardware Option
In addition to being initialized by software, the WDTCR register can also be automatically initialized at power-up
by the hardware options HWENW, HWWIDL, HWPS[2:0] and WDSFWP, which should be programmed by a
universal Writer or Programmer, as described below.
If HWENW is programmed to ―enabled‖, then hardware will automatically do the following initialization for the
WDTCR register at power-up: (1) set ENW bit, (2) load HWWIDL into WIDL bit, and (3) load HWPS[2:0] into
PS[2:0] bits.
If both of HWENW and WDSFWP are programmed to ―enabled‖, hardware still initializes the WDTCR register
content by WDT hardware option at power-up. Then, any CPU writing on WDTCR bits will be inhibited except
writing ―1‖ on WDTCR.4 (CLRW), clear WDT.
HWENW: Hardware loaded for ―ENW‖ of WDTCR.
: Enabled. Enable WDT and load the content of HWWIDL and HWPS2~0 to WDTCR after power-on.
: Disabled. WDT is not enabled automatically after power-on.
HWWIDL, HWPS2, HWPS1, HWPS0:
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on.
WDSFWP:
: Enabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected.
: Disabled. The WDT SFRs, WREN, NSW, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of
software.
30
MPC82x52 Data Sheet
MEGAWIN
9.5. WDT Sample Code
(1) Required function: Enable WDT and select WDT prescalar to 1/32
Assembly Code Example:
PS0
PS1
PS2
WIDL
CLRW
ENW
WRF
ANL
MOV
EQU
EQU
EQU
EQU
EQU
EQU
EQU
01h
02h
04h
08h
10h
20h
80h
WDTCR,#(0FFh - WRF)
; Clear WRF flag (write ―0‖)
WDTCR,#(ENW + CLRW + PS2) ; Enable WDT counter and set WDT prescaler to 1/32
C Code Example:
#define PS0
#define PS1
#define PS2
#define WIDL
#define CLRW
#define ENW
#define WRF
0x01
0x02
0x04
0x08
0x10
0x20
0x80
WDTCR &= ~WRF;
// Clear WRF flag (write ―0‖)
WDTCR = (ENW | CLRW | PS2);
// Enable WDT counter and set WDT prescaler to 1/32
// PS[2:0] | WDT prescaler selection
// 0 | 1/2
// 1 | 1/4
// 2 | 1/8
// 3 | 1/16
// 4 | 1/32
// 5 | 1/64
// 6 | 1/128
// 7 | 1/256
MEGAWIN
MPC82x52 Data Sheet
31
10. System Reset
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset
Vector, 0000H, or ISP start address by Hardware Option setting. The MPC82E/L52 has six sources of reset:
power-on reset, external reset, software reset, illegal address reset, WDT reset and low-voltage reset. Figure 10–
1 shows the system reset source in MPC82E/L52.
The following sections describe the reset happened source and corresponding control registers and indicating
flags.
10.1. Reset Source
Figure 10–1 presents the reset systems in the MPC82E/L52 and all of its reset sources.
Figure 10–1. System Reset Source
POF
(PCON.4)
Power-On Reset
External Reset
Software Reset
Internal Reset
Illegal Addr Reset
LVF
(PCON.5)
LVR
Reset
LVD Triggered
ENLVR
(Hardware Option)
WRF
(WDTCR.7)
WDT Reset
WDT Overflow
10.2. Power-On Reset
Power-on reset (POR) is used to internally reset the CPU during power-up. The CPU will keep in reset state and
will not start to work until the VDD power rises above the voltage of Power-On Reset. And, the reset state is
activated again whenever the VDD power falls below the POR voltage. During a power cycle, VDD must fall
below the POR voltage before power is reapplied in order to ensure a power-on reset
PCON: Power Control Register
SFR Address = 0x87
7
6
5
SMOD
SMOD0
LVF
4
POF
R/W
R/W
R/W
R/W
POR = 0011-0000, RESET = 000X-0000
3
2
1
0
GF1
GF0
PD
IDL
R/W
R/W
R/W
R/W
Bit 4: POF. Power-On Flag.
0: The flag must be cleared by software to recognize next reset type.
1: Set by hardware when VDD rises from 0 to its nominal voltage. POF can also be set by software.
The Power-on Flag, POF, is set to ―1‖ by hardware during power up or when VDD power drops below the POR
voltage. It can be clear by firmware and is not affected by any warm reset such as external reset, Low-Voltage
reset, software reset (ISPCR.5) and WDT reset. It helps users to check if the running of the CPU begins from
power up or not. Note that the POF must be cleared by firmware.
32
MPC82x52 Data Sheet
MEGAWIN
10.3. External Reset
A reset is accomplished by holding the RESET pin HIGH for at least 24 oscillator periods while the oscillator is
running. To ensure a reliable power-up reset, the hardware reset from RST pin is necessary.
10.4. Software Reset
Software can trigger the CPU to restart by software reset, writing ―1‖ on SWRST (ISPCR.5). SWBS decides the
CPU is boot from ISP or AP region after the reset action
ISPCR: ISP Control Register
SFR Address = 0xE5
7
6
5
SWBS
SWRST
ISPEN
4
CFAIL
R/W
R/W
R/W
R/W
RESET = 0000-x000
3
2
WAIT.2
W
R/W
1
WAIT.1
0
WAIT.0
R/W
R/W
Bit 6: SWBS, software boot selection control.
0: Boot from AP-memory after reset.
1: Boot from ISP memory after reset.
Bit 5: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
10.5. Low-Voltage Reset
In MPC82E/L52, there is a Low-Voltage Detectors (LVD) to monitor VDD power. BOD0 services the fixed
detection level at VDD=3.7V for E-series and 2.3V for L-series. If VDD power drops below LVD monitor level.
Associated flag, LVF, is set when LVD meets the detection level. If ENLVR (hardware option) is enabled, the LVD
will trigger a system reset and a set LVF indicates a LVD Reset occurred.
PCON: Power Control Register
SFR Address = 0x87
7
6
5
LVF
SMOD
SMOD0
4
POF
R/W
R/W
R/W
R/W
POR = 0011-0000, RESET = 000X-0000
3
2
1
0
GF1
GF0
PD
IDL
R/W
R/W
R/W
R/W
Bit 4: LVF, Low-Voltage Flag.
0: The flag must be cleared by software after power-up for further detecting.
1: This bit is only set by hardware when VDD meets LVD monitored level.
MEGAWIN
MPC82x52 Data Sheet
33
10.6. WDT Reset
When WDT is enabled to start the counter, WRF will be set by WDT overflow and trigger a system reset that
causes CPU to restart. Software can read the WRF to recognize the WDT reset occurred.
WDTCR: Watch-Dog-Timer Control Register
SFR Address = 0xE1
POR = 0000-0111 (xxx0_xxxx by Hardware Option)
7
6
5
4
3
2
1
0
WRF
-ENW
CLRW
WIDL
PS2
PS1
PS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.
10.7. Illegal Address Reset
In MPC82E/L52, if software program runs to illegal address such as over program ROM limitation, it triggers a
RESET to CPU.
34
MPC82x52 Data Sheet
MEGAWIN
10.8. Reset Sample Code
(1) Required function: Trigger a software reset
Assembly Code Example:
SWRST
EQU
ORL
ISPCR,#SWRST
C Code Example:
#define SWRST
ISPCR |= SWRST;
MEGAWIN
20h
; Trigger Software Reset
0x20
// Trigger Software Reset
MPC82x52 Data Sheet
35
11. Power Management
The MPC82E/L52 supports one power monitor module, Low-Voltage Detector (LVD), and 2 power-reducing
modes: Idle mode and Power-down mode.
LVD reports the chip power status on the flag, LVF, which provides the capability to interrupt CPU by software
configured or to reset CPU by hardware option. The three power-reducing modes provide the different powersaving scheme for chip application. These modes are accessed through the PCON and PCON2 register.
11.1. Low-Voltage Detector
In MPC82E/L52, there is a Low-Voltage Detector (LVD) to monitor VDD power. Figure 11–1 shows the functional
diagram of LVD. LVD services the fixed detection level at VDD=3.7V for 5V device and 2.3V on 3.3V device.
Associated flag, LVF (PCON.5), is set when LVD meets the detection level. If ENLVFI (AUXR.2) is enabled, a set
LVF will generate a low-voltage detection interrupt. It can interrupt CPU either CPU in normal mode or idle mode.
If ENLVR (hardware option) is enabled, the LVD event will trigger a system reset and a set LVF indicates a LVD
Reset occurred. The LVD reset restart the CPU either CPU in normal mode or idle mode.
SPECIAL NOTE ON LOW-VOLTAGE-DETECTOR: The Low-Voltage-Detector is not a precise detector. The
threshold voltage depends on temperature change. Lower the temperature goes, higher the threshold
voltage rises. During temperature scope (-40℃, 85℃), the threshold voltage falls between scope (2.7V,
1.8V) for MPC82L52, and (4.2V, 3.2V) for MPC82E52. To control the low-voltage detection and reset, also
the use must read another document “Initial Configuration.pdf” from Megawin which describes the initial
option register settings.
Figure 11–1. Low-Voltage Detector
VDD
ENLVR
LVD Reset
(hardware option)
“1”
Voltage
Comparator
E: 3.7V
L: 2.3V
Load
ENLVFI
+
(AUXR.2)
LVF Interrupt
PD
(PCON.1)
36
LVF
(PCON.5)
MPC82x52 Data Sheet
MEGAWIN
11.2. Power Saving Mode
11.2.1. Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is
preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and
accumulator. The Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves
the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer
1, UART, SPI and the LVD will continue to function during Idle mode. The PCA Timer and WDT are conditional
enabled during Idle mode to wake up CPU. Any enabled interrupt source or reset may terminate Idle mode.
When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI, the next
instruction to be executed will be the one following the instruction that put the device into Idle.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external memory.
The alternative to save the Idle mode power is to slow the MCU‘s operating speed by programming CKS2~CKS0
bits (in PCON2 register, see Section ―8 System Clock‖) to a non-0/0/0 value. The user should examine which
program segments are suitable for lower operating speed. In principle, the lower operating speed should not
affect the system‘s normal function. Then, restore its normal speed by hardware in the normal operating mode.
11.2.2. Power-Down Mode
Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the oscillator and powers down
the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw
power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive
voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been
reduced. Power-down may be exited by external reset, power-on reset and enabled external interrupts.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of
the following conditions has occurred: Start of code execution (after any type of reset), or Exit from power-down
mode.
Figure 11–2 shows the wakeup mechanism of power-down mode in MPC82E/L52.
Figure 11–2. Wakeup structure of Power Down mode
TCON.IT0=0
INT0 input
IE0
INT0 Wakeup
IE.EX0
force to level-sensitive in PD
TCON.IT1=0
INT1 input
IE1
INT1 Wakeup
IE.EX1
force to level-sensitive in PD
External Reset
MEGAWIN
MPC82x52 Data Sheet
Clear PCON.PD
& Wakeup CPU
37
11.2.3. Interrupt Recovery from Power-down
Two external interrupts may be configured to terminate Power-down mode. External interrupts INT0 (P3.2), INT1
(P3.3) may be used to exit Power-down. To wake up by external interrupt INT0, INT1, the interrupt must be
enabled and configured for level-sensitive operation. If the enabled external interrupts are configured to edgesensitive operation (Falling), they will be forced to level-sensitive operation (Low level) by hardware in powerdown mode.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate and the CPU will not resume execution until after the timer has reached
internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the interrupt from
re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the
device has timed out and begun executing.
11.2.4. Reset Recovery from Power-down
For RST input pin, wakeup from Power-down through an external reset is similar to the interrupt. At the rising
edge of RST, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate to the CPU until after the timer has reached internal counter full. The RST
pin must be held high for longer than the timeout period to ensure that the device is reset properly. The device
will begin executing once RST is brought low.
38
MPC82x52 Data Sheet
MEGAWIN
11.3. Power Control Register
PCON: Power Control Register
SFR Address = 0x87
7
6
5
SMOD
SMOD0
LVF
4
POF
R/W
R/W
R/W
R/W
POR = 0011-0000, RESET = 000x-0000
3
2
1
0
GF1
GF0
PD
IDL
R/W
R/W
R/W
R/W
1
CKS1
0
CKS0
R/W
R/W
Bit 1: PD, Power-Down control bit.
0: This bit could be cleared by CPU or any exited power-down event.
1: Setting this bit activates power down operation.
Bit 0: IDL, Idle mode control bit.
0: This bit could be cleared by CPU or any exited Idle mode event.
1: Setting this bit activates idle mode operation.
PCON2: Power Control Register 2
SFR Address = 0xC7
7
6
5
4
0
0
0
0
W
W
W
W
RESET = xxxx-x000
3
2
0
CKS2
W
R/W
Bit 7~3: Reserved. Software must write ―0‖ on these bits when PCON2 is written.
Bit 2~0: CKS2 ~ CKS0, programmable System Clock Selection in IDLE mode. The default value of CKS[2:0] is
set to ―000‖ to select system clock on OSCin/1.
CKS[2:0]
System Clock in idle mode
0 0 0
OSCin/1
0 0 1
OSCin /2
0 1 0
OSCin /4
0 1 1
OSCin /8
1 0 0
OSCin /16
1 0 1
OSCin /32
1 1 0
OSCin /64
1 1 1
OSCin /128
MEGAWIN
MPC82x52 Data Sheet
39
11.4. Power Control Sample Code
(1) Required function: Switch SYSCLK to OSCin/128 for IDLE mode (default is OSCin/1)
Assembly Code Example:
CKS0
EQU
CKS1
EQU
CKS2
EQU
ORL
01h
02h
04h
PCON2,#( CKS2 + CKS1 + CKS0) ; Set CKS[2:0] = ―111‖ to select OSCin/128
C Code Example:
#define CKS0
#define CKS1
#define CKS2
0x01
0x02
0x04
PCON2 |= (CKS2 | CKS1 | CKS0);
// System clock divider /128
// CKS[2:0], system clock divider
// 0 | OSCin/1
// 1 | OSCin/2
// 2 | OSCin/4
// 3 | OSCin/8
// 4 | OSCin/16
// 5 | OSCin/32
// 6 | OSCin/64
// 7 | OSCin/128
40
MPC82x52 Data Sheet
MEGAWIN
12. Configurable I/O Ports
The MPC82E/L52 has following I/O ports: P1.0~P1.7, P3.0~P3.5 and P3.7. The exact number of I/O pins
available depends upon the package types. See Table 12–1.
Table 12–1. Number of I/O Pins Available
Package Type
I/O Pins
20-pin
P1.0~P1.7, P3.0~P3.5, P3.7
PDIP/SOP/TSSOP
Number of I/O ports
15
12.1. IO Structure
The I/O operating modes in MPC82E/L52 support four configurations on I/O operating. These are: quasibidirectional (standard 8051 I/O port), push-pull output, input-only (high-impedance input) and open-drain output.
Followings describe the configuration of the all types I/O mode.
12.1.1. Quasi-Bidirectional IO Structure
All port pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can
be used as an input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin outputs low,
it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional
output that serve different purposes.
One of these pull-ups, called the ―very weak‖ pull-up, is turned on whenever the port register for the pin contains
a logic ―1‖. This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A
second pull-up, called the ―weak‖ pull-up, is turned on when the port register for the pin contains a logic ―1‖ and
the pin itself is also at a logic ―1‖ level. This pull-up provides the primary source current for a quasi-bidirectional
pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off, and only the
very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink
enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage. The third
pull-up is referred to as the ―strong‖ pull-up. This pull-up is used to speed up low-to-high transitions on a quasibidirectional port pin when the port register changes from a logic ―0‖ to a logic ―1‖. When this occurs, the strong
pull-up turns on for two CPU clocks, quickly pulling the port pin high.
The quasi-bidirectional port configuration is shown in Figure 12–1.
MEGAWIN
MPC82x52 Data Sheet
41
Figure 12–1. Quasi-Bidirectional I/O
VDD
2 clock
delay
VDD
Strong
VDD
Very
weak
Weak
Port
Pin
Port latch data
Input data
12.1.2. Push-Pull Output Structure
The push-pull output configuration has the same pull-down structure as both the open-drain and the quasibidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic ―1‖.
The push-pull mode may be used when more source current is needed from a port output. In addition, the input
path of the port pin in this configuration is also the same as quasi-bidirectional mode.
The push-pull port configuration is shown in Figure 12–2.
Figure 12–2. Push-Pull Output
VDD
Strong
Port
Pin
Port latch data
Input data
12.1.3. Input-Only (High Impedance Input) Structure
The input-only configuration is an input without any pull-up resistors on the pin, as shown in Figure 12–3.
Figure 12–3. Input-Only
Port
Pin
Input data
42
MPC82x52 Data Sheet
MEGAWIN
12.1.4. 3 Open-Drain Output Structure
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin
when the port register contains a logic ―0‖. To use this configuration in application, a port pin must have an
external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasibidirectional mode. In addition, the input path of the port pin in this configuration is also the same as quasibidirectional mode.
The open-drain port configuration is shown in Figure 12–4.
Figure 12–4. Open-Drain Output
Port
Pin
Port latch data
Input data
MEGAWIN
MPC82x52 Data Sheet
43
12.2. I/O Port Register
All I/O port pins on the MPC82E/L52 may be individually and independently configured by software to one of four
types on a bit-by-bit basis, as shown in Table 12–2. Two mode registers select the output type for each I/O pin.
Table 12–2. I/O Port Configuration Settings
PxM0.y
PxM1.y
Port Mode
0
0
Quasi-Bidirectional (default)
0
1
Push-Pull Output
1
0
Input Only (High Impedance Input)
1
1
Open-Drain Output
Where x=1 or 3 (port number), and y=0~7 (port pin). The registers PxM0 and PxM1 are listed in each port
description.
12.2.1. Port 1 Register
P1: Port 1 Register
SFR Address = 0x90
7
6
P1.7
P1.6
5
P1.5
4
P1.4
R/W
R/W
R/W
R/W
RESET = 1111-1111
3
2
P1.3
P1.2
R/W
R/W
1
P1.1
0
P1.0
R/W
R/W
Bit 7~0: P1.7~P1.0 could be only set/cleared by CPU.
P1M0: Port 1 Mode Register 0
SFR Address = 0x91
7
6
5
P1M0.7
P1M0.6
P1M0.5
4
P1M0.4
R/W
R/W
R/W
P1M1: Port 1 Mode Register 1
SFR Address = 0x92
7
6
5
P1M1.7
P1M1.6
P1M1.5
4
P1M1.4
POR+RESET = 0000-0000
3
2
1
P1M1.3
P1M1.2
P1M1.1
0
P1M1.0
R/W
R/W
R/W
R/W
R/W
1
P3.1
0
P3.0
R/W
R/W
R/W
R/W
R/W
R/W
POR+RESET = 0000-0000
3
2
1
P1M0.3
P1M0.2
P1M0.1
R/W
R/W
R/W
0
P1M0.0
R/W
12.2.2. Port 3 Register
P3: Port 3 Register
SFR Address = 0xB0
7
6
5
P3.7
-P3.5
4
P3.4
R/W
R/W
W
R/W
RESET = 1x11-1111
3
2
P3.3
P3.2
R/W
R/W
Bit 7: P3.7 could be only set/cleared by CPU.
Bit 6: Reserved. Software must write ―1‖ on this bit when P3 is written.
Bit 5~0: P3.7~P3.0 could be only set/cleared by CPU.
44
MPC82x52 Data Sheet
MEGAWIN
P3M0: Port 3 Mode Register 0
SFR Address = 0xB1
7
6
5
P3M0.7
-P3M0.5
4
P3M0.4
R/W
R/W
W
R/W
RESET = 0x00-0000
3
2
P3M0.3
P3M0.2
R/W
R/W
1
P3M0.1
0
P3M0.0
R/W
R/W
1
P3M1.1
0
P3M1.0
R/W
R/W
Bit 5: Reserved. Software must write ―0‖ on this bit when P3M0 is written.
P3M1: Port 3 Mode Register 1
SFR Address = 0xB2
7
6
5
P3M1.7
-P3M1.5
4
P3M1.4
R/W
R/W
W
R/W
RESET = 0000-0000
3
2
P3M1.3
P3M1.2
R/W
R/W
Bit 5: Reserved. Software must write ―0‖ on this bit when P3M1 is written.
MEGAWIN
MPC82x52 Data Sheet
45
12.3. GPIO Sample Code
(1). Required Function: Set P1.0 to input-only mode
Assembly Code Example:
P1Mn0
EQU
01h
ORL P1M0, #P1Mn0
ANL P1M1, #(0FFh + P1Mn0)
; Configure P1.0 to input only mode
SETB P1.0
; Set P1.0 data latch to ―1‖ to enable input mode
C Code Example:
#define P1Mn0
0x01
P1M0 |= P1Mn0;
P1M1 &= ~P1Mn0;
P10 = 1;
// Configure P1.0 to input only mode
// Set P1.0 data latch to ―1‖ to enable input mode
(2). Required Function: Set P1.0 to push-pull output mode
Assembly Code Example:
P1Mn0
EQU
01h
ANL P1M0, #(0FFh - P1Mn0)
ORL P1M1, #P1Mn0
; Configure P1.0 to push pull mode
SETB P1.0
C Code Example:
#define P1Mn0
0x01
P1M0 &= ~P1Mn0;
P1M1 |= P1Mn0;
P10 = 1;
// Configure P1.0 to push pull mode
// Set P1.0 data latch to ―1‖ to enable push pull mode
(3). Required Function: Set P1.0 to open-drain output mode
Assembly Code Example:
P1Mn0
EQU
01h
ORL P1M0, #P1Mn0
ORL P1M1, #P1Mn0
SETB P1.0
C Code Example:
#define P1Mn0
P1M0 |= P1Mn0;
P1M1 |= P1Mn0;
P10 = 1;
46
; Configure P1.0 to open drain mode
; Set P1.0 data latch to ―1‖ to enable open drain mode
0x01
// Configure P1.0 to open drain mode
// Set P1.0 data latch to ―1‖ to enable open drain mode
MPC82x52 Data Sheet
MEGAWIN
13. Interrupt
The MPC82E/L52 has 7 interrupt sources with a four-level interrupt structure. There are several SFRs associated
with the four-level interrupt. They are the IE, IP, IPH, and AUXR. The IPH (Interrupt Priority High) register makes
the four-level interrupt structure possible. The four priority level interrupt structure allows great flexibility in
handling these interrupt sources.
13.1. Interrupt Structure
Table 13–1 lists all the interrupt sources. The ‗Request Bits‘ are the interrupt flags that will generate an interrupt if
it is enabled by setting the ‗Enable Bit‘. Of course, the global enable bit EA (in IE register) should have been set
previously. The ‗Request Bits‘ can be set or cleared by software, with the same result as though it had been set
or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
The ‗Priority Bits‘ determine the priority level for each interrupt. The ‗Priority within Level‘ is the polling sequence
used to resolve simultaneous requests of the same priority level. The ‗Vector Address‘ is the entry point of an
interrupt service routine in the program memory.
Figure 13–1 shows the interrupt system. Each of these interrupts will be briefly described in the following sections.
Table 13–1. Interrupt Sources
No
Source Name
#4
#5
External Interrupt 0,
INT0
Timer 0
External Interrupt 1,
INT1
Timer 1
Serial Port
#6
SPI/ADC
#7
PCA/LVF
#1
#2
#3
MEGAWIN
Enable
Bit
Request
Bits
Priority
Bits
Polling
Priority
Vector
Address
EX0
IE0
[ PX0H, PX0 ]
(Highest)
0003H
ET0
TF0
[ PT0H, PT0 ]
…
000Bh
EX1
IE1
[ PX1H, PX1 ]
…
0013H
ET1
ES
ESPI_ADC
&
(ESPI,
EADCI)
EPCA_LVD
& (ECF,
ECCFn,
ENLVFI)
TF1
RI, TI
[ PT1H, PT1 ]
[ PSH, PS ]
…
…
001BH
0023H
SPIF, WCOL,
ADCI
[
PSPIH_ADC,
PSPI_ADC ]
…
002BH
CF
CCFn n=0~1)
LVF
[
PPCAH_LVD,
PPCA_LVD ]
(Lowest)
0033H
MPC82x52 Data Sheet
47
Figure 13–1. Interrupt System
Global Enable
(IE.EA)
Highest Priority Level
Interrupt
IP,IPH
Registers
Interrupt Polling
Sequence
TCON.IT0
IE.EX0
INT0
IE0
IE.ET0
TCON.TF0
TCON.IT1
IE.EX1
INT1
IE1
IE.ET1
TCON.TF1
SCON.RI
SCON.TI
SPISTAT.SPIF
SPISTAT.WCOL
AUXR.ESPI
IE.ES
IE.ESPI_ADC
ADCTL.ADCI
AUXR.EADCI
LVF
AUXR.ENLVFI
IE.EPCA_LVD
CF
ECF
CCF0
ECCF0
Lowest Priority
Level Interrupt
CCF1
ECCF1
48
MPC82x52 Data Sheet
MEGAWIN
13.2. Interrupt Source
Table 13–2. Interrupt flags
No
Source Name
#1
External Interrupt, INT0
#2
Timer 0
#3
External Interrupt, INT1
#4
Timer 1
#5
Serial Port
#6
SPI/ADC
#7
PCA/LVF
Request Bits
IE0
TF0
IE1
TF1
RI
TI
SPIF, WCOL,
ADCI
CF,
CCFn (n=0~1),
LVF
Bit Location
TCON.1
TCON.5
TCON.3
TCON.7
SCON.0
SCON.1
SPISTAT.7~6
ADCTL.4
CCON.7
CCON.1~0
PCON.5
The external interrupt INT0 and INT1 can each be either level-activated or transition-activated, depending on bits
IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service
routine is vectored to only if the interrupt was transition –activated, then the external requesting source is what
controls the request flag, rather than the on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. The service routine should poll RI and TI to determine which one to
request service and it will be cleared by software.
The SPI/ADC interrupt is shared by the logical OR of SPI interrupt (SPIF and WCOL) and ADC interrupt (ADCI).
Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should
poll them to determine which one to request service and it will be cleared by software.
The PCA/LVF interrupt is shared by the logical OR of PCA interrupt (CF, CCF0 and CCF1) and LVD (LowVoltage Detector) interrupt (LVF on PCON.5). Neither of these flags is cleared by hardware when the service
routine is vectored to. The service routine should poll them to determine which one to request service and it will
be cleared by software.
MEGAWIN
MPC82x52 Data Sheet
49
13.3. Interrupt Enable
Table 13–3. Interrupt enable control
No
Source Name
#1
External Interrupt, INT0
#2
Timer 0
#3
External Interrupt, INT1
#4
Timer 1
#5
Serial Port
#6
SPI/ADC
#7
PCA/LVF
Request Bits
IE0
TF0
IE1
TF1
RI
TI
SPIF,
WCOL
ADCI
CF,
CCF0,
CCF1,
LVF
Enable Bit
EX0
ET0
EX1
ET1
Bit Location
IE.0
IE.1
IE.2
IE.3
ES
IE.4
ESPI_ADC &
(ESPI,
EADCI)
EPCA_LVD &
(ECF,
ECCF0,
ECCF1,
ENLVFI)
IE.5,
AUXR.3,
AUXR.4
IE.6,
CMOD.0,
CCAPM0.0,
CCAPM1.0,
AUXR.2
There are 7 interrupt sources available in MPC82E/L52. Each of these interrupt sources can be individually
enabled or disabled by setting or clearing an interrupt enable bit in the register IE. IE also contains a global
disable bit, EA, which can be cleared to disable all interrupts at once. If EA is set to ‗1‘, the interrupts are
individually enabled or disabled by their corresponding enable bits. If EA is cleared to ‗0‘, all interrupts are
disabled.
13.4. Interrupt Priority
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt
levels rather than two as on the 80C51. The Priority Bits (see Table 13–1) determine the priority level of each
interrupt. IP and IPH are combined to 4-level priority interrupt. Table 13–4 shows the bit values and priority levels
associated with each combination.
Table 13–4. Interrupt priority level
{IPH.x , IP.x}
Priority Level
11
1 (highest)
10
2
01
3
00
4
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and
the other in IP register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine
which request is serviced. Table 13–2 shows the internal polling sequence in the same priority level and the
interrupt vector address.
50
MPC82x52 Data Sheet
MEGAWIN
13.5. Interrupt Process
Each interrupt flag is sampled at every system clock cycle. The samples are polled during the next system clock.
If one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interrupt
system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked by any of
the following conditions.
Block conditions:



An interrupt of equal or higher priority level is already in progress.
The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE, IP and IPH registers.
Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE, IP or IPH, then at least one or
more instruction will be executed before any interrupt is vectored to.
MEGAWIN
MPC82x52 Data Sheet
51
13.6. Interrupt Register
TCON: Timer/Counter Control Register
SFR Address = 0x88
7
6
5
4
TF1
TR1
TF0
TR0
R/W
R/W
R/W
R/W
RESET = 0000-0000
3
2
IE1
IT1
R/W
R/W
1
IE0
0
IT0
R/W
R/W
Bit 3: IE1, Interrupt 1 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1.
1: Set by software to specify falling edge triggered external interrupt 1.
Bit 1: IE0, Interrupt 0 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 0 edge is detected (transmitted or level-activated).
Bit 0: IT0: Interrupt 0 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 0.
1: Set by software to specify falling edge triggered external interrupt 0.
IE: Interrupt Enable Register
SFR Address = 0xE8
7
6
5
4
EA
EPCA_LVD ESPI_ADC ES
R/W
R/W
R/W
RESET = 0000-0000
3
2
ET1
EX1
R/W
R/W
R/W
1
ET0
0
EX0
R/W
R/W
Bit 7: EA, All interrupts enable register.
0: Global disables all interrupts.
1: Global enables all interrupts.
Bit 6: EPCA_LVD, group interrupt enable register of PCA and Low-Voltage Detector (LVD).
0: Disable group interrupt of PCA and LVD.
1: Enable group interrupt of PCA and LVD.
Bit 5: ESPI_ADC, group interrupt enable register of SPI and ADC.
0: Disable group interrupt SPI and ADC.
1: Enable group interrupt SPI and ADC.
Bit 4: ES, Serial port interrupt enable register.
0: Disable serial port interrupt.
1: Enable serial port interrupt.
Bit 3: ET1, Timer 1 interrupt enable register.
0: Disable Timer 1 interrupt.
1: Enable Timer 1 interrupt.
Bit 2: EX1, External interrupt 1 enable register.
0: Disable external interrupt 1.
1: Enable external interrupt 1.
Bit 1: ET0, Timer 0 interrupt enable register.
0: Disable Timer 0 interrupt.
1: Enable Timer 1 interrupt.
Bit 0: EX0, External interrupt 0 enable register.
0: Disable external interrupt 0.
1: Enable external interrupt 1.
52
MPC82x52 Data Sheet
MEGAWIN
AUXR: Auxiliary Register
SFR Address = 0x8E
7
6
5
T0X12
T1X12
URM0X6
4
EADCI
R/W
R/W
R/W
R/W
RESET = 0000-00xx
3
2
ESPI
ENLVFI
R/W
R/W
1
--
0
--
W
W
1
PT0
0
PX0
R/W
R/W
Bit 4: EADCI, ADC interrupt enable register.
0: Disable ADC interrupt.
1: Enable ADC interrupt.
Bit 3: ESPI, Enable SPI interrupt.
0: Disable SPI interrupt.
1: Enable SPI interrupt.
Bit 2: ENLVFI, Enable LVD Interrupt.
0: Disable LVD (LVF) interrupt.
1: Enable LVD (LVF) interrupt.
IP: Interrupt Priority low Register
SFR Address = 0xB8
7
6
5
4
-PPCA_LVD PSPI_ADC PS
W
R/W
R/W
R/W
RESET = xx00-0000
3
2
PT1
PX1
R/W
R/W
Bit 7: Reserved. Software must write ―0‖ on this bit when IP is written.
Bit 6: PPCA_LVD, interrupt priority-L register of PCA and LVD.
Bit 5: PSPI_ADC, interrupt priority-L register of SPI and ADC.
Bit 4: PS, Serial port interrupt priority-L register.
Bit 3: PT1, Timer 1 interrupt priority-L register.
Bit 2: PX1, external interrupt 1 priority-L register.
Bit 1: PT0, Timer 0 interrupt priority-L register.
Bit 0: PX0, external interrupt 0 priority-L register.
IPH: Interrupt Priority High Register
SFR Address = 0xB7
7
6
5
4
-PPCAH_LVD PSPIH_ADC PSH
W
R/W
R/W
R/W
RESET = xx00-0000
3
2
PT1H
PX1H
R/W
R/W
1
PT0H
0
PX0H
R/W
R/W
Bit 7: Reserved. Software must write ―0‖ on this bit when IPH is written.
Bit 6: PPCAH_LVD, interrupt priority-H register of PCA and LVD.
Bit 5: PSPIH_ADC, interrupt priority-H register of SPI and ADC.
Bit 4: PSH, Serial port interrupt priority-H register.
Bit 3: PT1H, Timer 1 interrupt priority-H register.
Bit 2: PX1H, external interrupt 1 priority-H register.
Bit 1: PT0H, Timer 0 interrupt priority-H register.
Bit 0: PX0H, external interrupt 0 priority-H register.
MEGAWIN
MPC82x52 Data Sheet
53
13.7. Interrupt Sample Code
(1). Required Function: Set INT0 wake-up MCU in power-down mode
Assembly Code Example:
PX0
EQU
PX0H
EQU
PD
EQU
01h
01h
02h
ORG 0000h
JMP main
ORG 00003h
ext_int0_isr:
to do.....
RETI
main:
SETB
P3.2
;
ORL
ORL
IP,#PX0
IPH,#PX0H
; Select INT0 interrupt priority
;
JB
P3.2, $
SETB EX0
CLR IE0
SETB EA
ORL
PCON,#PD
JMP
$
; Confirm P3.2 input low?????
; Enable INT0 interrupt
; Clear INT0 flag
; Enable global interrupt
; Set MCU into Power Down mode
C Code Example:
#define PX0
#define PX0H
#define PD
0x01
0x01
0x02
void ext_int0_isr(void) interrupt 0
{
To do……
}
void main(void)
{
P32 = 1;
IP |= PX0;
IPH |= PX0H;
// Select INT0 interrupt priority
while(P32);
// Confirm P3.2 input low??????
EX0 = 1;
IE0 = 0;
EA = 1;
PCON |= PD;
// Enable INT0 interrupt
// Clear INT0 flag
// Enable global interrupt
// Set MCU into Power Down mode
while(1);
}
54
MPC82x52 Data Sheet
MEGAWIN
14. Timers/Counters
MPC82E/L52 has two Timers/Counters: Timer 0 and Timer 1. Timer0/1 can be configured as timers or event
counters.
In the ―timer‖ function, the timer rate is prescaled by 12 clock cycle to increment register value. In other words, it
is to count the standard C51 machine cycle. AUXR.T0X12 and AUXR.T1X12 are the function for Timer 0/1 to set
the timer rate on every clock cycle.
In the ―counter‖ function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin, T0 or T1. In this function, the external input is sampled by every timer rate cycle. When the
samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value
appears in the register at the end of the cycle following the one in which the transition was detected.
14.1. Timer0 and Timer1
14.1.1. Mode 0 Structure
The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer
interrupt flag TFx. The counted input is enabled to the timer when TRx = 1 and either GATE=0 or INTx = 1. Mode
0 operation is the same for Timer0 and Timer1. The mode 0 function of Timer 0/1 is shown in Figure 14–1.
Figure 14–1. Timer 0/1 Mode 0 Structure
SYSCLK /12
0
SYSCLK
1
AUXR.TxX12
0
Tx Pin
TLx[4:0]
THx[7:0]
Overflow
TFx
Interrupt
1
C/T
TRx
x = 0 or 1
GATE
INTx Pin
MEGAWIN
MPC82x52 Data Sheet
55
14.1.2. Mode 1 Structure
Timer 0/1 in Mode1 is configured as a 16 bit timer or counter. The function of GATE, INTx and TRx is same as
mode 0. Figure 14–2 shows the mode 1 structure of Timer 0 and Timer 1.
Figure 14–2. Timer 0/1 Mode 1 Structure
SYSCLK /12
0
SYSCLK
1
AUXR.TxX12
0
Tx Pin
TLx[7:0]
THx[7:0]
Overflow
TFx
Interrupt
1
C/T
TRx
x = 0 or 1
GATE
INTx Pin
56
MPC82x52 Data Sheet
MEGAWIN
14.1.3. Mode 2 Structure
Mode 2 configures the timer register as an 8-bit counter(TLx) with automatic reload. Overflow from TLx not only
set TFx, but also reload TLx with the content of THx, which is determined by software. The reload leaves THx
unchanged. Mode 2 operation is the same for Timer0 and Timer1.
Figure 14–3. Timer 0/1 Mode 2 Structure
SYSCLK /12
0
SYSCLK
1
AUXR.TxX12
0
Tx Pin
Overflow
TLx[7:0]
TFx
Interrupt
1
C/T
Reload
TRx
GATE
x = 0 or 1
THx[7:0]
nINTx Pin
MEGAWIN
MPC82x52 Data Sheet
57
14.1.4. Mode 3 Structure
Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0
and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, INT0 and
TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1
from Timer1. TH0 now controls the Timer1 interrupt.
Figure 14–4. Timer 0 Mode 3 Structure
SYSCLK /12
0
SYSCLK
1
AUXR.T0X12
0
T0 Pin
TL0[7:0]
Overflow
TF0
T0 Interrupt
TF1
T1 Interrupt
1
C/T
TR0
GATE
INT0 Pin
SYSCLK /12
0
SYSCLK
1
AUXR.T0X12
58
TH0[7:0]
Overflow
TR1
MPC82x52 Data Sheet
MEGAWIN
14.1.5. Timer0/1 Register
TCON: Timer/Counter Control Register
SFR Address = 0x88
7
6
5
4
TF1
TR1
TF0
TR0
R/W
R/W
R/W
RESET = 0000-0000
3
2
IE1
IT1
R/W
R/W
R/W
1
IE0
0
IT0
R/W
R/W
Bit 7: TF1, Timer 1 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 1 overflow, or set by software.
Bit 6: TR1, Timer 1 Run control bit.
0: Cleared by software to turn Timer/Counter 1 off.
1: Set by software to turn Timer/Counter 1 on.
Bit 5: TF0, Timer 0 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 0 overflow, or set by software.
Bit 4: TR0, Timer 0 Run control bit.
0: Cleared by software to turn Timer/Counter 0 off.
1: Set by software to turn Timer/Counter 0 on.
TMOD: Timer/Counter Mode Control Register
SFR Address = 0x89
RESET = 0000-0000
7
6
5
4
3
2
GATE
C/T
M1
M0
GATE
C/T
1
M1
0
M0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
|----------------------- Timer1 -------------------------|--------------------------Timer0 ------------------------|
Bit 7/3: Gate, Gating control for Timer1/0.
0: Disable gating control for Timer1/0.
1: Enable gating control for Timer1/0. When set, Timer1/0 or Counter1/0 is enabled only when /INT1 or /INT0 pin
is high and TR1 or TR0 control bit is set.
Bit 6/2: C/T, Timer for Counter function selector.
0: Clear for Timer operation, input from internal system clock.
1: Set for Counter operation, input form T1 input pin.
Bit 5~4/1~0: Operating mode selection.
M1 M0
Operating Mode
0 0
13-bit timer/counter for Timer0 and Timer1
0 1
16-bit timer/counter for Timer0 and Timer1
1 0
8-bit timer/counter with automatic reload for Timer0 and Timer1
1 1 (Timer0) TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer
1 1 (Timer1) Timer/Counter1 Stopped
TL0: Timer Low 0 Register
SFR Address = 0x8A
7
6
5
TL0.7
TL0.6
TL0.5
4
TL0.4
R/W
R/W
R/W
R/W
TH0: Timer High 0 Register
SFR Address = 0x8C
7
6
5
TH0.7
TH0.6
TH0.5
4
TH0.4
R/W
R/W
R/W
MEGAWIN
R/W
RESET = 0000-0000
3
2
TL0.3
TL02
R/W
R/W
RESET = 0000-0000
3
2
TH0.3
TH0.2
R/W
R/W
MPC82x52 Data Sheet
1
TL0.1
0
TL0.0
R/W
R/W
1
TH0.1
0
TH0.0
R/W
R/W
59
TL1: Timer Low 1 Register
SFR Address = 0x8B
7
6
5
TL1.7
TL1.6
TL1.5
4
TL1.4
R/W
R/W
R/W
R/W
TH1: Timer High 1 Register
SFR Address = 0x8D
7
6
5
TH1.7
TH1.6
TH1.5
4
TH1.4
R/W
R/W
R/W
R/W
AUXR: Auxiliary Register
SFR Address = 0x8E
7
6
5
T0X12
T1X12
URM0X6
4
EADCI
R/W
R/W
R/W
R/W
RESET = 0000-0000
3
2
TL1.3
TL1.2
R/W
R/W
RESET = 0000-0000
3
2
TH1.3
TH1.2
R/W
R/W
RESET = 0000-00xx
3
2
ESPI
ENLVFI
R/W
R/W
1
TL1.1
0
TL1.0
R/W
R/W
1
TH1.1
0
TH1.0
R/W
R/W
1
--
0
--
W
W
Bit 7: T0X12, Timer 0 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
60
MPC82x52 Data Sheet
MEGAWIN
14.1.6. Timer0/1 Sample Code
(1). Required Function: IDLE mode with T0 wake-up frequency 10KHz, SYSCLK = 12MHz Crystal
Assembly Code Example:
T0M0
EQU
T0M1
EQU
PT0
EQU
PT0H
EQU
IDL
EQU
01h
02h
02h
02h
01h
ORG 0000h
JMP main
ORG 0000Bh
time0_isr:
to do…
RETI
main:
; (unsigned short value)
MOV
MOV
ANL
ORL
CLR
TH0,#(256-100)
TL0,#(256-100)
TMOD,#0F0h
TMOD,#T0M1
TF0
ORL
ORL
IP,#PT0
IPH,#PT0H
SETB
SETB
ET0
EA
; Enable Timer 0 interrupt
; Enable global interrupt
SETB
TR0
; Start Timer 0 running
ORL
JMP
; Set Timer 0 overflow rate = SYSCLK x 100
;
; Set Timer 0 to Mode 2
;
; Clear Timer 0 Flag
; Select Timer 0 interrupt priority
;
PCON,#IDL
$
; Set MCU into IDLE mode
C Code Example:
#define T0M0
#define T0M1
#define PT0
#define PT0H
#define IDL
0x01
0x02
0x02
0x02
0x01
void time0_isr(void) interrupt 1
{
To do…
}
void main(void)
{
TH0 = TL0 = (256-100);
TMOD &= 0xF0;
TMOD |= T0M1;
TF0 = 0;
IP |= PT0;
IPH |= PT0H;
// Set Timer 0 overflow rate = SYSCLK x 100
// Set Timer 0 to Mode 2
// Clear Timer 0 Flag
// Select Timer 0 interrupt priority
ET0 = 1;
EA = 1;
// Enable Timer 0 interrupt
// Enable global interrupt
TR0 = 1;
// Start Timer 0 running
PCON =IDL;
while(1);
// Set MCU into IDLE mode
}
MEGAWIN
MPC82x52 Data Sheet
61
(2). Required Function: Select Timer 0 clock source from SYSCLK (enable T0X12)
Assembly Code Example:
T0M0
EQU
T0M1
EQU
PT0
EQU
PT0H
EQU
T0X12
EQU
01h
02h
02h
02h
80h
ORG 0000h
JMP main
ORG 0000Bh
time0_isr:
to do…
RETI
main:
ORL
CLR
AUXR, #T0X12
TF0
ORL
ORL
IP,#PT0
IPH,#PT0H
SETB
SETB
ET0
EA
MOV
MOV
TH0, #(256 - 240)
TL0, #(256 - 240)
ANL
ORL
TMOD,#0F0h
TMOD,#T0M1
SETB TR0
JMP $
C Code Example:
#define T0M0
#define T0M1
#define PT0
#define PT0H
#define T0X12
; Select SYSCLK/1 for Timer 0 clock input
; Clear Timer 0 Flag
; Select Timer 0 interrupt priority
;
; Enable Timer 0 interrupt
; Enable global interrupt
;interrupt interval 20us
;
; Set Timer 0 to Mode 2
;
; Start Timer 0 running
0x01
0x02
0x02
0x02
0x80
AUXR |= T0X12
TF0 = 0;
IP |= PT0;
IPH |= PT0H;
ET0 = 1;
EA = 1;
// Select Timer 0 interrupt priority
// Enable Timer 0 interrupt
// Enable global interrupt
TH0 = TL0 = (256 - 240);
TMOD &= 0xF0;
TMOD |= T0M1;
TR0 = 1;
62
// Set Timer 0 to Mode 2
// Start Timer 0 running
MPC82x52 Data Sheet
MEGAWIN
15. Serial Port (UART)
The serial port of MPC82E/L52 support full-duplex transmission, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a
previously received byte has been read from the register. However, if the first byte still hasn‘t been read by the
time reception of the second byte is complete, one of the bytes will be lost. The serial port receive and transmit
registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and
reading from SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes: Mode 0 provides synchronous communication while Modes 1, 2, and 3
provide asynchronous communication. The asynchronous communication operates as a full-duplex Universal
Asynchronous Receiver and Transmitter (UART), which can transmit and receive simultaneously and at different
baud rates.
Mode 0: 8 data bits (LSB first) are transmitted or received through RXD(P3.0). TXD(P3.1) always outputs the
shift clock. The baud rate can be selected to 1/12 or 1/2 the system clock frequency by URM0X6 setting in AUXR
register.
Mode 1: 10 bits are transmitted through TXD or received through RXD. The frame data includes a start bit (0), 8
data bits (LSB first), and a stop bit (1), as shown in Figure 15–1. On receive, the stop bit would be loaded into
RB8 in SCON register. The baud rate is variable.
Figure 15–1. Mode 1 Data Frame
Mode 1
8-bit data
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Mode 2: 11 bits are transmitted through TXD or received through RXD. The frame data includes a start bit (0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (1), as shown in Figure 15–2. On Transmit, the
9th data bit comes from TB8 in SCON register can be assigned the value of 0 or 1. On receive, the 9th data bit
would be loaded into RB8 in SCON register, while the stop bit is ignored. The baud rate can be configured to
1/32 or 1/64 the system clock frequency.
Figure 15–2. Mode 2, 3 Data Frame
Mode 2, 3
9-bit data
Start
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
Mode 3: Mode 3 is the same as Mode 2 except the baud rate is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. In Mode 0,
reception is initiated by the condition RI=0 and REN=1. In the other modes, reception is initiated by the incoming
start bit with 1-to-0 transition if REN=1.
In addition to the standard operation, the UART can perform framing error detection by looking for missing stop
bits, and automatic address recognition.
MEGAWIN
MPC82x52 Data Sheet
63
15.1. Serial Port Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits
(LSB first). The shift clock source can be selected to 1/12 or 1/2 the system clock frequency by URM0X6 setting
in AUXR register. Figure 15–3 shows a simplified functional diagram of the serial port in Mode 0.
Transmission is initiated by any instruction that uses SBUF as a destination register. The ―write to SBUF‖ signal
triggers the UART engine to start the transmission. The data in the SBUF would be shifted into the RXD(P3.0) pin
by each raising edge shift clock on the TXD(P3.1) pin. After eight raising edge of shift clocks passing, TI would be
asserted by hardware to indicate the end of transmission. Figure 15–4 shows the transmission waveform in Mode
0.
Reception is initiated by the condition REN=1 and RI=0. At the next instruction cycle, the Serial Port Controller
writes the bits 11111110 to the receive shift register, and in the next clock phase activates Receive.
Receive enables Shift Clock which directly comes from RX Clock to the alternate output function of P3.1 pin.
When Receive is active, the contents on the RXD(P3.0) pin would be sampled and shifted into shift register by
falling edge of shift clock. After eight falling edge of shift clock, RI would be asserted by hardware to indicate the
end of reception. Figure 15–5 shows the reception waveform in Mode 0.
Figure 15–3. Serial Port Mode 0
SYSCLK
80C51 Internal BUS
12
“0”
2
Write
SBUF
“1”
URM0X6
TX Clock
TXBUF
RXD Alternated
for Input/output
Function
RX Clock
RXBUF
UART engine
REN
Shift-clock
RXSTART
TXD Alternated
for output
Function
RI
RI
TI
Serial Port Interrupt
Read
SBUF
80C51 Internal BUS
64
MPC82x52 Data Sheet
MEGAWIN
Figure 15–4. Mode 0 Transmission Waveform
Write to
SBUF
P3.1/TXD
P3.0/RXD
D0
D1
D2
D3
D4
D5
D6
D7
TI
RI
Figure 15–5. Mode 0 Reception Waveform
Write to
SCON
Set REN, Clear RI
P3.1/TXD
P3.0/RXD
D0
D1
D2
D3
D4
D5
D6
D7
TI
RI
MEGAWIN
MPC82x52 Data Sheet
65
15.2. Serial Port Mode 1
10 bits are transmitted through TXD, or received through RXD: a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB8 in SCON. The baud rate is determined by the Timer 1 overflow rate.
Figure 15–1 shows the data frame in Mode 1 and Figure 15–6 shows a simplified functional diagram of the serial
port in Mode 1.
Transmission is initiated by any instruction that uses SBUF as a destination register. The ―write to SBUF‖ signal
requests the UART engine to start the transmission. After receiving a transmission request, the UART engine
would start the transmission at the raising edge of TX Clock. The data in the SBUF would be serial output on the
TXD pin with the data frame as shown in Figure 15–1 and data width depend on TX Clock. After the end of 8th
data transmission, TI would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when Serial Port Controller detected 1-to-0 transition at RXD sampled by RCK. The data on
the RXD pin would be sampled by Bit Detector in Serial Port Controller. After the end of STOP-bit reception, RI
would be asserted by hardware to indicate the end of data reception and load STOP-bit into RB8 in SCON
register.
Figure 15–6. Serial Port Mode 1, 2, 3
Mode 2
clock source
SYSCLK/2
Mode 1, 3
clock source
Timer 1
Overflow
80C51 Internal BUS
Write
SBUF
2
“0”
2
“1”
“0”
SM0
“1”
SM1
SMOD
TXBUF
TXD
RXBUF
RXD
TB8
RI
1
16
TX Clock
UART engine
0
Serial Port
Interrupt
TI
SM1
1
RCK
16
STOP-Bit
RX Clock
0
RB8
1
0
9th-Bit
SM1
SM0
Read
SBUF
80C51 Internal BUS
66
MPC82x52 Data Sheet
MEGAWIN
15.3. Serial Port Mode 2 and Mode 3
11 bits are transmitted through TXD, or received through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0
or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to select either 1/32 or
1/64 the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.
Figure 15–2 shows the data frame in Mode 2 and Mode 3. Figure 15–6 shows a functional diagram of the serial
port in Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs
from Mode 1 only in the 9th bit of the transmit shift register.
The ―write to SBUF‖ signal requests the Serial Port Controller to load TB8 into the 9th bit position of the transmit
shit register and starts the transmission. After receiving a transmission request, the UART engine would start the
transmission at the raising edge of TX Clock. The data in the SBUF would be serial output on the TXD pin with
the data frame as shown in Figure 15–2 and data width depend on TX Clock. After the end of 9th data
transmission, TI would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when the UART engine detected 1-to-0 transition at RXD sampled by RCK. The data on the
RXD pin would be sampled by Bit Detector in UART engine. After the end of 9th data bit reception, RI would be
asserted by hardware to indicate the end of data reception and load the 9th data bit into RB8 in SCON register.
In all four modes, transmission is initiated by any instruction that use SBUF as a destination register. Reception is
initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming
start bit with 1-to-0 transition if REN=1.
15.4. Frame Error Detection
When used for framing error detection, the UART looks for missing stop bits in the communication. A missing
stop bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of
SCON.7 is determined by SMOD0 bit (PCON.6). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When SCON.7 functions as FE, it can only be cleared by firmware.
Refer to Figure 15–7.
Figure 15–7. UART Frame Error Detection
9-bit data
Start
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
SET FE bit if STOP=0
SM0 to UART mode control
PCON.SMOD0
SCON
MEGAWIN
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
MPC82x52 Data Sheet
67
15.5. Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications as shown in Figure 15–8. In these
two modes, 9 data bits are received. The 9th bit goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8=1. This
feature is enabled by setting bit SM2 (in SCON register). A way to use this feature in multiprocessor systems is
as follows:
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an
address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2=1, no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the received byte and check if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren‘t being addressed leave their SM2 set and go on about their business, ignoring the coming
data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1
reception, if SM2=1, the receive interrupt will not be activated unless a valid stop bit is received.
Figure 15–8. UART Multiprocessor Communications
VCC
Pull-up
R
Slave 3
Slave 2
Slave 1
Master
RX
RX
RX
RX
TX
TX
TX
TX
15.6. Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of firmware overhead by
eliminating the need for the firmware to examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON.
In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the
received byte contains either the ―Given‖ address or the ―Broadcast‖ address. The 9-bit mode requires that the
9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address
recognition is shown in Figure 15–9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is
enabled and the information received has a valid stop bit following the 8 address bits and the information is either
a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the
Broadcast address. Two special Function Registers are used to define the slave‘s address, SADDR, and the
address mask, SADEN.
SADEN is used to define which bits in the SADDR are to be used and which bits are ―don‘t care‖. The SADEN
mask can be logically ANDed with the SADDR to create the ―Given‖ address which the master will use for
addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding
others.
68
MPC82x52 Data Sheet
MEGAWIN
The following examples will help to show the versatility of this scheme:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0
Slave 1
SADDR = 1100 0000
SADEN = 1111 1110
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves.
Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique
address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would
be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address
which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1
SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
Slave 2
SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that
bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely
addressed by 1110 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this
result are treated as don‘t-cares. In most cases, interpreting the don‘t-cares as ones, the broadcast address will
be FF hexadecimal.
Upon reset SADDR (SFR address 0xA9) and SADEN (SFR address 0xB9) are loaded with 0s. This produces a
given address of all ―don‘t cares‖ as well as a Broadcast address of all ―don‘t cares‖. This effectively disables the
Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do
not make use of this feature.
Figure 15–9. Auto-Address Recognition
9-bit data
Start
D0
D1
SCON
D2
SM0/FE
D3
SM1
Receive Address D0~D7
Comparator
SM2
D4
REN
D5
TB8
D6
D7
RB8
TI
D8
Stop
RI
addr_match
Programmed Address
Note:
(1) After address matching (addr_match=1), Clear SM2 to receive data bytes
(2) After all data bytes have been received, Set SM2 to wait for next address.
MEGAWIN
MPC82x52 Data Sheet
69
15.7. Baud Rate Setting
Bits T1X12 and URM0X6 in AUXR register provide a new option for the baud rate setting, as listed below.
15.7.1. Baud Rate in Mode 0
Figure 15–10. Mode 0 baud rate equation
Mode 0 Baud Rate =
FSYSCLK
n
; n=12, if URM0X6=0
; n=2, if URM0X6=1
Note:
If URM0X6=0, the baud rate formula is as same as standard 8051.
Table 15–1. Serial Port Mode 0 baud rate example
SYSCLK URM0X6 Mode 0 Baud Rate
12MHz
0
1M bps
12MHz
1
6M bps
24MHz
0
2M bps
24MHz
1
12M bps
15.7.2. Baud Rate in Mode 2
Figure 15–11. Mode 2 baud rate equation
Mode 2 Baud Rate =
2SMOD
64
X (FSYSCLK)
Table 15–2. Serial Port Mode 2 baud rate example
SYSCLK
SMOD
Mode 2 Baud Rate
22.1184MHz 0
345.6K bps
22.1184MHz 1
172.8K bps
24MHz
0
750K bps
24MHz
1
375K bps
15.7.3. Baud Rate in Mode 1 & 3
Using Timer 1 as the Baud Rate Generator
Figure 15–12. Mode 1/3 baud rate equation
Mode 1, 3 Baud Rate =
2SMOD
32
X
FSYSCLK
n x (256 – TH1)
; n=12, if T1X12=0
; n=1, if T1X12=1
―Table 15–3 ~ Table 15–6― list various commonly used baud rates and how they can be obtained from Timer 1 in
its 8-Bit Auto-Reload Mode.
70
MPC82x52 Data Sheet
MEGAWIN
Table 15–3. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=11.0592MHz
TH1, the Reload Value
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
230400
T1X12=0
T1X12=1
SMOD=0
SMOD=1
Error
SMOD=0
SMOD=1
Error
232
244
250
253
254
-255
-----
208
232
244
250
252
253
254
-255
---
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
-0.0%
---
-112
184
220
232
238
244
247
250
253
--
--112
184
208
220
232
238
244
250
253
-0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
Table 15–4. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=22.1184MHz
TH1, the Reload Value
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
230400
460800
MEGAWIN
T1X12=0
T1X12=1
SMOD=0
SMOD=1
Error
SMOD=0
SMOD=1
Error
208
232
244
250
252
253
254
-255
----
160
208
232
244
248
250
252
253
254
255
---
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
---
--112
184
208
220
232
238
244
250
253
--
---112
160
184
208
220
232
244
250
253
-0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
MPC82x52 Data Sheet
71
Table 15–5. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=12.0MHz
TH1, the Reload Value
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
T1X12=0
T1X12=1
SMOD=0
SMOD=1
Error
SMOD=0
SMOD=1
Error
230
243
---------
204
230
243
--------
0.16%
0.16%
0.16%
--------
-100
178
217
230
-243
246
---
--100
178
204
217
230
236
243
--
-0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
2.34%
0.16%
--
Table 15–6. Timer 1 Generated Commonly Used Baud Rates @ FSYSCLK=24.0MHz
TH1, the Reload Value
Baud Rate
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
72
T1X12=0
T1X12=1
SMOD=0
SMOD=1
Error
SMOD=0
SMOD=1
Error
204
230
243
--------
152
204
230
243
-------
0.16%
0.16%
0.16%
0.16%
-------
--100
178
204
217
230
-243
--
---100
152
178
204
217
230
243
--0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
MPC82x52 Data Sheet
MEGAWIN
15.8. Serial Port Register
All the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate
setting. Two registers, PCON and AUXR, are related to the baud rate setting:
SCON: Serial port Control Register
SFR Address = 0x98
7
6
5
4
SM0/FE
SM1
SM2
REN
R/W
R/W
R/W
RESET = 0000-0000
3
2
TB8
RB8
R/W
R/W
R/W
1
TI
0
RI
R/W
R/W
Bit 7: FE, Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit.
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit is set by the receiver when an invalid stop bit is detected.
Bit 7: SM0, Serial port mode bit 0, (SMOD0 must = 0 to access bit SM0)
Bit 6: SM1, Serial port mode bit 1.
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
SYSCLK/12 or SYSCLK/2
variable
SYSCLK/64, /32
variable
Bit 5: SM2, Serial port mode bit 2.
0: Disable SM2 function.
1: Enable the automatic address recognition feature in Modes 2 and 3. If SM2=1, RI will not be set unless the
received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In
mode1, if SM2=1 then RI will not be set unless a valid stop Bit was received, and the received byte is a Given
or Broadcast address. In Mode 0, SM2 should be 0.
Bit 4: REN, Enable serial reception.
0: Clear by software to disable reception.
1: Set by software to enable reception.
Bit 3: TB8, The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
th
Bit 2: RB8, In Modes 2 and 3, the 9 data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that
was received. In Mode 0, RB8 is not used.
Bit 1: TI. Transmit interrupt flag.
0: Must be cleared by software.
th
1: Set by hardware at the end of the 8 bit time in Mode 0, or at the beginning of the stop bit in the other modes,
in any serial transmission.
Bit 0: RI. Receive interrupt flag.
0: Must be cleared by software.
th
1: Set by hardware at the end of the 8 bit time in Mode 0, or halfway through the stop bit time in the other modes,
in any serial reception (except see SM2).
SBUF: Serial Buffer Register
SFR Address = 0x99
7
6
5
SBUF.7
SBUF.6
SBUF.5
4
SBUF.4
R/W
R/W
R/W
R/W
RESET = XXXX-XXXX
3
2
SBUF.3
SBUF.2
R/W
R/W
1
SBUF.1
0
SBUF.0
R/W
R/W
Bit 7~0: It is used as the buffer register in transmission and reception.
MEGAWIN
MPC82x52 Data Sheet
73
SADDR: Slave Address Register
SFR Address = 0xA9
7
6
5
4
R/W
R/W
R/W
R/W
RESET = 0000-0000
3
2
SADEN: Slave Address Mask Register
SFR Address = 0xB9
7
6
5
4
R/W
R/W
R/W
R/W
R/W
RESET = 0000-0000
3
2
R/W
R/W
R/W
1
0
R/W
R/W
1
0
R/W
R/W
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address
recognition. In fact, SADEN functions as the ―mask‖ register for SADDR register. The following is the example for
it.
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00x0
The Given slave address will be checked except
bit 1 is treated as ―don‘t care‖
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in this
result is considered as ―don‘t care‖. Upon reset, SADDR and SADEN are loaded with all 0s. This produces a
Given Address of all ―don‘t care‖ and a Broadcast Address of all ―don‘t care‖. This disables the automatic address
detection feature.
PCON: Power Control Register
SFR Address = 0x87
7
6
5
SMOD
SMOD0
LVF
4
POF
R/W
R/W
R/W
R/W
POR = 0011-0000, RESET = 0000-0000
3
2
1
0
GF1
GF0
PD
IDL
R/W
R/W
R/W
R/W
Bit 7: SMOD, double Baud rate control bit.
0: Disable double Baud rate of the UART.
1: Enable double Baud rate of the UART in mode 1, 2, or 3.
Bit 6: SMOD0, Frame Error select.
0: SCON.7 is SM0 function.
1: SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.
AUXR: Auxiliary Register
SFR Address = 0x8E
7
6
5
T0X12
T1X12
URM0X6
4
EADCI
R/W
R/W
R/W
R/W
RESET = 0000-00xx
3
2
ESPI
ENLVFI
R/W
R/W
1
--
0
--
W
W
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 5: URM0X6, Serial Port mode 0 baud rate selector.
0: Clear to select SYSCLK/12 as the baud rate for UART Mode 0.
1: Set to select SYSCLK/2 as the baud rate for UART Mode 0.
74
MPC82x52 Data Sheet
MEGAWIN
15.9. Serial Port Sample Code
(1). Required Function: IDLE mode with RI wake-up capability
Assembly Code Example:
PS
EQU
PSH
EQU
ORG 00023h
uart_ri_idle_isr:
JB
RI,RI_ISR
JB
TI,TI_ISR
RETI
;
RI_ISR:
; Process
CLR RI
RETI
;
;
TI_ISR:
; Process
CLR TI
RETI
;
10h
10h
;
;
;
main:
CLR TI
CLR RI
SETB SM1
SETB REN
;
;
;
; 8bit Mode2, Receive Enable
CALL
UART_Baud_Rate_Setting
MOV
MOV
IP,#PSL
IPH,#PSH
SETB
SETB
ES
EA
ORL
PCON,#IDL;
;refer to ―Table 15–3 ~ Table 15–6― for detailed information
; Select UART interrupt priority
;
; Enable S0 interrupt
; Enable global interrupt
; Set MCU into IDLE mode
C Code Example:
#define PS
#define PSH
0x10
0x10
void uart_ri_idle_isr(void) interrupt 4
{ if(RI)
{
RI=0;
// to do ...
}
if(TI)
{
TI=0;
// to do ...
}
}
void main(void)
{
TI = RI = 0;
SM1 = REN = 1;
UART_Baud_Rate_Setting()
IP = PSL;
MEGAWIN
// 8bit Mode2, Receive Enable
// refer to ―Table 15–3 ~ Table 15–6― for detailed information
// Select S0 interrupt priority
MPC82x52 Data Sheet
75
IPH = PSH;
ES = 1;
EA = 1;
PCON |= IDL;
//
// Enable S0 interrupt
// Enable global interrupt
// Set MCU into IDLE mode
}
76
MPC82x52 Data Sheet
MEGAWIN
16. Programmable Counter Array (PCA)
The MPC82E/L52 is equipped with a Programmable Counter Array (PCA), which provides more timing
capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software
overhead and improved accuracy.
16.1. PCA Overview
The PCA consists of a dedicated timer/counter which serves as the time base for an array of two
compare/capture modules. Figure 16–1 shows a block diagram of the PCA. Notice that the PCA timer and
modules are all 16-bits. If an external event is associated with a module, that function is shared with the
corresponding Port pin. If the module is not using the port pin, the pin can still be used for standard I/O.
Each of the four modules can be programmed in any one of the following modes:
- Rising and/or Falling Edge Capture
- Software Timer
- High Speed Output
- Pulse Width Modulator (PWM) Output
All of these modes will be discussed later in detail. However, let's first look at how to set up the PCA timer and
modules.
Figure 16–1. PCA Block Diagram
16 Bit Each
Module 0
CEX0 (P3.7)
Module 1
CEX1 (P3.5)
PCA Timer/Counter
16 Bit
MEGAWIN
MPC82x52 Data Sheet
77
16.2. PCA Timer/Counter
The timer/counter for the PCA is a free-running16-bit timer consisting of registers CH, CL (the high and low bytes
of the count values), as shown in Figure 16–2. It is the common time base for all modules and its clock input can
be selected from the following source:
- 1/12 the system clock frequency,
- 1/2 the system clock frequency,
- the Timer 0 overflow, which allows for a range of slower clock inputs to the timer.
- external clock input, 1-to-0 transitions, on ECI pin (P3.4),
Special Function Register CMOD contains the Count Pulse Select bits (CPS1 and CPS0) to specify the PCA
timer input. This register also contains the ECF bit which enables an interrupt when the counter overflows. In
addition, the user has the option of turning off the PCA timer during Idle Mode by setting the Counter Idle bit
(CIDL). This can further reduce power consumption during Idle mode.
Figure 16–2. PCA Timer/Counter
To PCA Module 0~1
SYSCLK/12
(0,0)
SYSCLK/2
(0,1)
Timer0 Overflow
(1,0)
External Input ECI (P3.4)
(1,1)
16-bits Up Counter
CH
8 bits
overflow
CL
8 bits
CF
Control
PCA Interrupt
Enable
CPS[1:0] Indexed
PCON.IDL
CF
CMOD: PCA Counter Mode Register
SFR Address = 0xD9
7
6
5
4
CIDL
---R/W
W
W
W
CIDL
--
--
--
--
CPS1
CPS0
ECF
CR
--
--
--
--
CCF1
CCF0
CCON
RESET = 0xxx-x000
3
2
-CPS1
W
R/W
CMOD
1
CPS0
0
ECF
R/W
R/W
Bit 7: CIDL, PCA counter Idle control.
0: Lets the PCA counter continue functioning during Idle mode.
1: Lets the PCA counter be gated off during Idle mode.
Bit 6~3: Reserved. Software must write ―0‖ on these bits when CMOD is written.
Bit 3~1: CPS2-CPS0, PCA counter clock source select bits.
CPS1
CPS0
PCA Clock Source
0
0
Internal clock, SYSCLK/12
0
1
Internal clock, SYSCLK/2
1
0
Timer 0 overflow
1
1
External clock at the ECI pin
Bit 0: ECF, Enable PCA counter overflow interrupt.
0: Disables an interrupt when CF bit (in CCON register) is set.
1: Enables an interrupt when CF bit (in CCON register) is set.
78
MPC82x52 Data Sheet
MEGAWIN
The CCON register shown below contains the run control bit for the PCA and the flags for the PCA timer and
each module. To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this
bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit
in the CMOD register is set. The CF bit can only be cleared by software. CCF0 and CCF1 are the interrupt flags
for module 0 and module 1, respectively, and they are set by hardware when either a match or a capture occurs.
These flags also can only be cleared by software. The PCA interrupt system is shown Figure 16–3.
CCON: PCA Counter Control Register
SFR Address = 0xD8
7
6
5
4
CF
CR
--R/W
R/W
W
W
RESET = 00xx-xx00
3
2
--W
W
1
CCF1
0
CCF0
R/W
R/W
Bit 7: CF, PCA Counter Overflow flag.
0: Only be cleared by software.
1: Set by hardware when the counter rolls over. CF flag can generate an interrupt if bit ECF in CMOD is set. CF
may be set by either hardware or software.
Bit 6: CR, PCA Counter Run control bit.
0: Must be cleared by software to turn the PCA counter off.
1: Set by software to turn the PCA counter on.
Bit 5~2: Reserved. Software must write ―0‖ on these bits when CCON is written.
Bit 1: CCF1, PCA Module 1 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
Bit 0: CCF0, PCA Module 0 interrupt flag.
0: Must be cleared by software.
1: Set by hardware when a match or capture occurs.
MEGAWIN
MPC82x52 Data Sheet
79
Figure 16–3. PCA Interrupt System
CF
CR
--
--
--
--
CCF1
CCON
CCF0
PCA Timer/Counter
CH
CL
overflow
CMOD.ECF
IE.EPCA_LVD
IE.EA
Module 0
To PCA Interrupt
Module 1
CCAPMn.0 (n=0~1)
ECCF0, ECCF1
16.3. Compare/Capture Modules
Each of the four compare/capture modules has a mode register called CCAPMn (n= 0 or 1) to select which
function it will perform. Note the ECCFn bit which enables an interrupt to occur when a module's interrupt flag is
set.
CCAPMn: PCA Module Compare/Capture Register, n=0~1
SFR Address = 0xDA~0xDB
RESET = x000-0000
7
6
5
4
3
2
-ECOMn
CAPPn
CAPNn
MATn
TOGn
1
PWMn
0
ECCFn
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: Reserved. Software must write ―0‖ on this bit when the CCAPMn is written.
Bit 6: ECOMn, Enable Comparator
0: Disable the digital comparator function.
1: Enables the digital comparator function.
Bit 5: CAPPn, Capture Positive enabled.
0: Disable the PCA capture function on CEXn positive edge detected.
1: Enable the PCA capture function on CEXn positive edge detected.
Bit 4: CAPNn, Capture Negative enabled.
0: Disable the PCA capture function on CEXn positive edge detected.
1: Enable the PCA capture function on CEXn negative edge detected.
Bit 3: MATn, Match control.
0: Disable the digital comparator match event to set CCFn.
1: A match of the PCA counter with this module‘s compare/capture register causes the CCFn bit in CCON to be
set.
Bit 2: TOGn, Toggle control.
0: Disable the digital comparator match event to toggle CEXn.
1: A match of the PCA counter with this module‘s compare/capture register causes the CEXn pin to toggle.
Bit 1: PWMn, PWM control.
0: Disable the PWM mode in PCA module.
1: Enable the PWM function and cause CEXn pin to be used as a pulse width modulated output.
80
MPC82x52 Data Sheet
MEGAWIN
Bit 0: ECCFn, Enable CCFn interrupt.
0: Disable compare/capture flag CCFn in the CCON register to generate an interrupt.
1: Enable compare/capture flag CCFn in the CCON register to generate an interrupt.
Note: The bits CAPNn (CCAPMn.4) and CAPPn (CCAPMn.5) determine the edge on which a capture input will
be active. If both bits are set, both edges will be enabled and a capture will occur for either transition.
Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These
registers are used to store the time when a capture event occurred or when a compare event should occur.
When a module is used in the PWM mode, in addition to the above two registers, an extended register
PCAPWMn is used to improve the range of the duty cycle of the output. The improved range of the duty cycle
starts from 0%, up to 100%, with a step of 1/256.
CCAPnH: PCA Module n Capture High Register, n=0~1
SFR Address = 0xFA~0xFD
RESET = 0000-0000
7
6
5
4
3
2
1
0
CCAPnH.7 CCAPnH.6 CCAPnH.5 CCAPnH.4 CCAPnH.3 CCAPnH.2 CCAPnH.1 CCAPnH.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CCAPnL: PCA Module n Capture Low Register, n=0~1
SFR Address = 0xEA~0xED
RESET = 0000-0000
7
6
5
4
3
2
1
0
CCAPnL.7 CCAPnL.6 CCAPnL.5 CCAPnL.4 CCAPnL.3 CCAPnL.2 CCAPnL.1 CCAPnL.0
R/W
R/W
R/W
R/W
PCAPWMn: PWM Mode Auxiliary Register, n=0~1
SFR Address = 0xF2~0xF5
RESET = xxxx-xx00
7
6
5
4
3
2
-------
1
ECAPnH
0
ECAPnL
W
R/W
R/W
W
R/W
W
R/W
W
R/W
W
R/W
W
Bit 7~2: Reserved. Software must write ―0‖ on these bits when PCAPWMn is written.
Bit 1: ECAPnH, Extended 9th bit (MSB bit), associated with CCAPnH to become a 9-bit register used in PWM
mode.
Bit 0: ECAPnL, Extended 9th bit (MSB bit), associated with CCAPnL to become a 9-bit register used in PWM
mode.
MEGAWIN
MPC82x52 Data Sheet
81
16.4. Operation Modes of the PCA
Table 16–1 shows the CCAPMn register settings for the various PCA functions.
Table 16–1. PCA Module Modes
ECOMn CAPPn CAPNn MATn
TOGn
PWMn ECCFn Module Function
0
0
0
0
0
0
0
No operation
X
1
0
0
0
0
X
16-bit capture by a positive-edge trigger on CEXn
X
0
1
0
0
0
X
16-bit capture by a negative-edge trigger on CEXn
X
1
1
0
0
0
X
16-bit capture by a transition on CEXn
1
0
0
1
0
0
X
16-bit Software Timer
1
0
0
1
1
0
X
16-bit High Speed Output
1
0
0
0
0
1
0
8-bit Pulse Width Modulator (PWM)
16.4.1. Capture Mode
To use one of the PCA modules in the capture mode, either one or both of the bits CAPN and CAPP for that
module must be set. The external CEX input for the module is sampled for a transition. When a valid transition
occurs, the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module‘s capture
registers (CCAPnL and CCAPnH). If the CCFn and the ECCFn bits for the module are both set, an interrupt will
be generated.
Figure 16–4. PCA Capture Mode
CF
CR
--
--
--
--
CCF1
CCF0
CCON
PCA Interrupt
(To CCFn)
CCAPnH
CCAPnL
CH
CL
Capture
CEXn
PCA Timer/Counter
CCAPMn
n= 0~1
--
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
0
1
1
0
0
0
ECCFn
CAPPn or CAPNn =1
82
MPC82x52 Data Sheet
MEGAWIN
16.4.2. 16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the module‘s
CCAPMn register. The PCA timer will be compared to the module‘s capture registers, and when a match occurs
an interrupt will occur if the CCFn and the ECCFn bits for the module are both set.
Figure 16–5. PCA Software Timer Mode
Write to
CCAPnL
CF
CR
--
Write to
CCAPnH
CCAPnH
1
0
--
--
--
CCF1
CCF0
CCON
Reset
Enable
CCAPnL
(To CCFn)
Match
16-Bit Comparator
CH
PCA Interrupt
CL
PCA Timer/Counter
--
MEGAWIN
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
0
0
1
0
0
MPC82x52 Data Sheet
ECCFn
CCAPMn, n= 0~1
83
16.4.3. High Speed Output Mode
In this mode the CEX output associated with the PCA module will toggle each time a match occurs between the
PCA counter and the module‘s capture registers. To activate this mode, the TOG, MAT and ECOM bits in the
module‘s CCAPMn register must be set.
Figure 16–6. PCA High Speed Output Mode
Write to
CCAPnL
CF
CR
--
Write to
CCAPnH
CCAPnH
1
0
--
--
--
CCF1
CCF0
CCON
Reset
Enable
CCAPnL
(To CCFn)
Match
16-Bit Comparator
PCA Interrupt
Toggle
PCA Timer/Counter
CH
CL
--
84
ECOMn
CEXn
CAPPn
CAPNn
MATn
TOGn
PWMn
0
0
1
1
0
MPC82x52 Data Sheet
ECCFn
CCAPMn, n= 0~1
MEGAWIN
16.4.4. PWM Mode
All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the clock source
for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA
timer.
th
The duty cycle of each module is determined by the module‘s capture register CCAPnL and the extended 9 bit,
ECAPnL. When the 9-bit value of { 0, [CL] } is less than the 9-bit value of { ECAPnL, [CCAPnL] } the output will
be low, and if equal to or greater than the output will be high.
When CL overflows from 0xFF to next clock input, { ECAPnL, [CCAPnL] } is reloaded with the value of { ECAPnH,
[CCAPnH] }. This allows updating the PWM without glitches. The PWMn and ECOMn bits in the module‘s
CCAPMn register must be set to enable the PWM mode.
Using the 9-bit comparison, the duty cycle of the output can be improved to really start from 0%, and up to 100%.
The formula for the duty cycle is:
Duty Cycle = 1 – { ECAPnH, [CCAPnH] } / 256.
Where, [CCAPnH] is the 8-bit value of the CCAPnH register, and ECAPnH (bit-1 in the PCAPWMn register) is 1bit value. So, { ECAPnH, [CCAPnH] } forms a 9-bit value for the 9-bit comparator. For examples,
a.
b.
c.
d.
If ECAPnH=0 & CCAPnH=0x00 (i.e., 0x000), the duty cycle is 100%.
If ECAPnH=0 & CCAPnH=0x40 (i.e., 0x040) the duty cycle is 75%.
If ECAPnH=0 & CCAPnH=0xC0 (i.e., 0x0C0), the duty cycle is 25%.
If ECAPnH=1 & CCAPnH=0x00 (i.e., 0x100), the duty cycle is 0%.
Figure 16–7. PCA PWM Mode
9 Bits
ECAPnH
CCAPnH
9 Bits
ECAPnL
CCAPnL
0
Enable
{0,[CL]} < {ECAPnL, [CCAPnL]}
9-Bit
Comparator
CEXn
{0,[CL]} >= {ECAPnL, [CCAPnL]}
1
9 Bits
CL
Overflow
(Fixed 0)
CL
PCA Timer/Counter
--
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
1
0
0
0
0
1
0
MEGAWIN
CCAPMn, n= 0~1
MPC82x52 Data Sheet
85
16.5. PCA Sample Code
(1). Required Function: Set Module 0 for CEX0 rising capture function and Module 1 for PWM output with 25%
duty cycle
Assembly Code Example:
PWM1
CAPP0
ECOM1
EQU
EQU
EQU
PWM2_PWM3:
MOV
MOV
02h
20h
40h
CCON,#00H
CMOD,#02H
; stop CR
; PCA clock source = system clock / 2
ORL
CCAPM0, #CAPP0
; capture rising edge
ORL
MOV
SETB
CCAPM1, #(ECOM1 + PWM1)
CCAP3H, #0C0h
CR
;module 1
; 25 %
; start PCA's PWM output
C Code Example:
#define PWM1
#define CAPP0
#define ECOM1
EQU
EQU
EQU
void main(void)
{
// set PCA
CCON = 0x00;
CMOD = 0x02;
CCAPM0 |= CAPP0;
0x02
0x20
0x40
// disable PCA & clear CCF0, CCF1, CF flag
// PCA clock source = system clock / 2
// capture rising edge
CCAPM1 |= (ECOM1 | PWM1);
CCAP3H = 0xC0;
// module 1
// 25 %
CR = 1;
// start PCA's PWM output
while (1);
}
86
MPC82x52 Data Sheet
MEGAWIN
17. Serial Peripheral Interface (SPI)
The MPC82E/L52 provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex,
high-speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up
to 3 Mbps can be supported in either Master or Slave mode under a 12MHz system clock. It has a Transfer
Completion Flag (SPIF) and Write Collision Flag (WCOL) in the SPI status register (SPSTAT).
Figure 17–1. SPI Block Diagram
SPICLK
(P1.7)
Output Shift Register
SYSCLK
Divider
by
4
16
64
128
MISO
(P1.6)
Input Shift Register
I/O
Control
MOSI
(P1.5)
SPI Control
nSS
(P1.4)
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPIF
WCOL
--
--
--
--
--
--
SPCTL
SPSTAT
The SPI interface has four pins: MISO (P1.6), MOSI (P1.5), SPICLK (P1.7) and nSS (P1.4):
• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master
to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the MISO pin (Master In /
Slave Out). The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal I/O pins.
• nSS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to
select one SPI device as the current slave. An SPI slave device uses its nSS pin to determine whether it is
selected. The nSS is ignored if any of the following conditions are true:
- If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value).
- If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P1.4 (nSS) is configured as an output.
- If the nSS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions.
Note that even if the SPI is configured as a master (MSTR=1), it can still be converted to a slave by driving the
nSS pin low (if SSIG=0). Should this happen, the SPIF bit (SPSTAT.7) will be set. (See Section ―17.2.3 Mode
Change on nSS-pin‖)
MEGAWIN
MPC82x52 Data Sheet
87
17.1. Typical SPI Configurations
17.1.1. Single Master & Single Slave
For the master: any port pin, including P1.4 (nSS), can be used to drive the nSS pin of the slave.
For the slave: SSIG is ‗0‘, and nSS pin is used to determine whether it is selected.
Figure 17–2. SPI single master & single slave configuration
SPICLK
Master
SPICLK
MISO
MISO
MOSI
MOSI
Port Pin
Slave
nSS
17.1.2. Dual Device, where either can be a Master or a Slave
Two devices are connected to each other and either device can be a master or a slave. When no SPI operation is
occurring, both can be configured as masters with MSTR=1, SSIG=0 and P1.4 (nSS) configured in quasibidirectional mode. When any device initiates a transfer, it can configure P1.4 as an output and drive it low to
force a ―mode change to slave‖ in the other device. (See Section ―17.2.3 Mode Change on nSS-pin‖)
Figure 17–3. SPI dual device configuration, where either can be a master or a slave
SPICLK
Master/
Slave
MISO
MISO
MOSI
MOSI
nSS
88
SPICLK
MPC82x52 Data Sheet
Slave/
Master
nSS
MEGAWIN
17.1.3. Single Master & Multiple Slaves
For the master: any port pin, including P1.4 (nSS), can be used to drive the nSS pins of the slaves.
For all the slaves: SSIG is ‗0‘, and nSS pin are used to determine whether it is selected.
Figure 17–4. SPI single master multiple slaves configuration
SPICLK
SPICLK
MISO
MISO
MOSI
MOSI
Port Pin 1
Slave #1
nSS
Master
SPICLK
MISO
MOSI
Port Pin 2
MEGAWIN
Slave #2
nSS
MPC82x52 Data Sheet
89
17.2. Configuring the SPI
Table 17–1 shows configuration for the master/slave modes as well as usages and directions for the modes.
Table 17–1. SPI Master and Slave Selection
SPEN
SSIG
nSS
MSTR
(SPCTL.6) (SPCTL.7) -pin
(SPCTL.4)
0
X
X
X
1
0
0
0
1
0
1
0
1
0
0
10
Mode
MISO
-pin
MOSI
-pin
SPICLK
Remarks
-pin
input
input
P1.4~P1.7 are used as general
port pins.
output input
input
Selected as slave.
Hi-Z
input
Not selected.
input
Mode change to slave
if nSS pin is driven low, and
MSTR will be cleared to ‗0‘ by
H/W automatically.
Hi-Z
MOSI and SPICLK are at high
impedance
to
avoid
bus
contention when the Master is
idle.
SPI disabled input
Salve
(selected)
Slave
(not selected)
Slave
(by
mode output input
change)
Master
1
0
1
1
input
(idle)
Hi-Z
input
Master
output output
(active)
1
1
X
0
Slave
output input
1
1
X
1
Master
input
MOSI and SPICLK are push-pull
when the Master is active.
input
output output
―X‖ means ―don‘t care‖.
17.2.1. Additional Considerations for a Slave
When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each successive serial
byte transfer. Note the SPDAT register cannot be written while nSS pin is active (low), and the operation is
undefined if CPHA is 0 and SSIG is 1.
When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the nSS pin may remain active low between successive
transfers (can be tied low at all times). This format is sometimes preferred for use in systems having a single
fixed master and a single slave configuration.
17.2.2. Additional Considerations for a Master
In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as master,
writing to the SPI data register (SPDAT) by the master starts the SPI clock generator and data transfer. The data
will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.
Before starting the transfer, the master may select a slave by driving the nSS pin of the corresponding device low.
Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the MOSI pin of the
slave. And, at the same time the data in SPDAT register of the selected slave is shifted out on MISO pin to the
MISO pin of the master.
After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt
will be created if the SPI interrupt is enabled. The two shift registers in the master CPU and slave CPU can be
considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data
is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master
and the slave are interchanged.
90
MPC82x52 Data Sheet
MEGAWIN
17.2.3. Mode Change on nSS-pin
If SPEN=1, SSIG=0, MSTR=1 and nSS pin=1, the SPI is enabled in master mode. In this case, another master
can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus contention,
the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be
an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an
SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a slave select
and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will
stay in slave mode.
17.2.4. Write Collision
The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for
transmission can not be written to the shift register until the previous transaction is complete. The WCOL
(SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case,
the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the
collision, will be lost.
While write collision is detected for both a master or a slave, it is uncommon for a master because the master has
full control of the transfer in progress. The slave, however, has no control over when the master will initiate a
transfer and therefore collision can occur.
For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to
accept a second character. However, the received character must be read from the Data Register (SPDAT)
before the next character has been completely shifted in. Otherwise, the previous data is lost.
WCOL can be cleared in software by writing ‗1‘ to the bit.
17.2.5. SPI Clock Rate Select
The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCTL register, as shown in
Table 17–2.
Table 17–2. SPI Serial Clock Rates
SPI
Clock
SPR1
SPR0
SYSCLK=12MHz
0
0
3 MHz
0
1
750 KHz
1
0
187.5 KHz
1
1
93.75 KHz
Where, SYSCLK is the system clock.
MEGAWIN
Rate
@
SYSCLK divided by
4
16
64
128
MPC82x52 Data Sheet
91
17.3. Data Mode
Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit,
CPOL, allows the user to set the clock polarity. The following figures show the different settings of Clock Phase
Bit, CPHA.
Figure 17–5. SPI Slave Transfer Format with CPHA=0
1
Clock Cycle
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
MSB
6
5
4
3
2
1
LSB
DORD=1
LSB
1
2
3
4
5
6
MSB
Not
defined
MISO
Slave Output
1st bit out
data sampled
nSS (if SSIG=0)
This edge is used by the slave to shift out the 1st bit
of each data byte while CPHA=0
Figure 17–6. SPI Slave Transfer Format with CPHA=1
1
Clock Cycle
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit in
MOSI
Slave Intput
DORD=0
MSB
6
5
4
3
2
1
LSB
DORD=1
LSB
1
2
3
4
5
6
MSB
Not
defined
MISO
Slave Output
1st bit out
Not defined
data sampled
nSS (if SSIG=0)
92
MPC82x52 Data Sheet
MEGAWIN
Figure 17–7. SPI Master Transfer Format with CPHA=0
Clock Cycle
Enable SPI
1
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit out
MOSI
Master Output
DORD=0
MSB
6
5
4
3
2
1
LSB
DORD=1
LSB
1
2
3
4
5
6
MSB
MISO
Master Input
1st bit in
data sampled
nSS (if SSIG=0)
Figure 17–8. SPI Master Transfer Format with CPHA=1
1
Clock Cycle
2
3
4
5
6
7
8
SPICLK (CPOL=0)
SPICLK (CPOL=1)
1st bit out
MOSI
Master Output
DORD=0
MSB
6
5
4
3
2
1
LSB
DORD=1
LSB
1
2
3
4
5
6
MSB
MISO
Master Input
1st bit in
data sampled
nSS (if SSIG=0)
MEGAWIN
MPC82x52 Data Sheet
93
17.4. SPI Register
The following special function registers are related to the SPI operation:
SPCON: SPI Control Register
SFR Address = 0x85
7
6
5
SSIG
SPEN
DORD
4
MSTR
R/W
R/W
R/W
R/W
RESET= 0000-0100
3
2
CPOL
CPHA
R/W
R/W
1
SPR1
0
SPR0
R/W
R/W
Bit 7: SSIG, nSS is ignored.
0: The nSS pin decides whether the device is a master or slave.
1: MSTR decides whether the device is a master or slave.
Bit 6: SPEN, SPI enable.
0: The SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
1: The SPI is enabled.
Bit 5: DORD, SPI data order.
0: The MSB of the data byte is transmitted first.
1: The LSB of the data byte is transmitted first.
Bit 4: MSTR, Master/Slave mode select
0: Selects slave SPI mode.
1: Selects master SPI mode.
Bit 3: CPOL, SPI clock polarity select
0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling
edge.
1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising
edge.
Bit 2: CPHA, SPI clock phase select
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is sampled on
the leading edge of SPICLK.
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
(Note: If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.)
Bit 1~0: SPR1-SPR0, SPI clock rate select (in master mode)
00: SYSCLK/4
01: SYSCLK/16
10: SYSCLK/64
11: SYSCLK/128 (Where, SYSCLK is the system clock.)
SPSTAT: SPI Status Register
SFR Address = 0x84
7
6
5
SPIF
WCOL
--
4
--
R/W
R
R/W
R
RESET= 00XX-XXXX
3
2
--R
R
1
--
0
--
R
R
Bit 7: SPIF, SPI transfer completion flag
0: The SPIF is cleared in software by writing „1‟ to this bit. Software writing ―:0‖ is no operation.
1: When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If
nSS pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the ―mode
change‖.
Bit 6: WCOL, SPI write collision flag.
0: The WCOL flag is cleared in software by writing „1‟ to this bit. Software writing ―:0‖ is no operation.
1: The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer (see Section 15.2.4:
Write Collision).
94
MPC82x52 Data Sheet
MEGAWIN
Bit 5~0: Reserved. Software must write ―0‖ on these bits when SPSTAT is written.
SPDAT: SPI Data Register
SFR Address = 0x86
7
6
5
(MSB)
R/W
R/W
R/W
4
R/W
RESET= 0000-0000
3
2
R/W
R/W
1
0
(LSB)
R/W
R/W
SPDAT has two physical buffers for writing to and reading from during transmit and receive, respectively.
MEGAWIN
MPC82x52 Data Sheet
95
17.5. SPI Sample Code
(1). Required Function: SPI Master Read and Write, sample data at rising edge and clock leading edge is rising.
Assembly Code Example:
CPHA
EQU
CPOL
EQU
MSTR
EQU
SPEN
EQU
SSIG
EQU
SPIF
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
ORL SPICTL, #(SSIG + SPEN + MSTR)
RET
;initial SPI
;enable SPI and Master mode
SPI_Write:
MOV SPIDAT, R7
wait_write:
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;write arg R7
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
;trigger SPI read
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR);
}
// enable SPI and Master mode
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
96
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MPC82x52 Data Sheet
MEGAWIN
(2). Required Function: SPI Master Read and Write, sample data at rising edge and clock leading edge is falling.
Assembly Code Example:
CPHA
EQU
CPOL
EQU
MSTR
EQU
SPEN
EQU
SSIG
EQU
SPIF
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
ORL SPICTL, #(SSIG + SPEN + MSTR + CPOL)
RET
SPI_Write:
MOV SPIDAT, R7
wait_write:
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;write arg R7
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
;trigger SPI read
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPOL);
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
MEGAWIN
;initial SPI
;enable SPI and Master mode
// enable SPI and Master mode
//write arg
//wait transfer finishes
//clear SPI interrupt flag
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MPC82x52 Data Sheet
97
(3). Required Function: SPI Master Read and Write, sample data at falling edge and clock leading edge is rising.
Assembly Code Example:
CPHA
EQU
CPOL
EQU
MSTR
EQU
SPEN
EQU
SSIG
EQU
SPIF
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
ORL SPICTL, #(SSIG + SPEN + MSTR + CPHA)
RET
SPI_Write:
MOV SPIDAT, R7
wait_write:
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;write arg R7
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
;trigger SPI read
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPHA);
}
// enable SPI and Master mode
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
//write arg
//wait transfer finishes
//clear SPI interrupt flag
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
98
;initial SPI
;enable SPI and Master mode
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MPC82x52 Data Sheet
MEGAWIN
(4). Required Function: SPI Master Read and Write, sample data at falling edge and clock leading edge is falling.
Assembly Code Example:
CPHA
EQU
CPOL
EQU
MSTR
EQU
SPEN
EQU
SSIG
EQU
SPIF
EQU
04h
08h
10h
40h
80h
80h
Initial_SPI:
ORL SPICTL, #(SSIG + SPEN + MSTR + CPOL + CPHA)
RET
SPI_Write:
MOV SPIDAT, R7
wait_write:
MOV A, SPISTAT
JNB ACC.7, wait_write
ANL SPISTAT, #(0FFh - SPIF)
RET
;write arg R7
;wait transfer finishes
;clear SPI interrupt flag
SPI_Read:
MOV SPIDAT, #0FFh
wait_read:
MOV A, SPISTAT
JNB ACC.7, wait_read
ANL SPISTAT, #(0FFh - SPIF)
MOV A, SPIDAT
RET
C Code Example:
#define CPHA
#define CPOL
#define MSTR
#define SPEN
#define SSIG
#define SPIF
;trigger SPI read
;wait read finishes
;clear SPI interrupt flag
;move read data to accumulator
0x04
0x08
0x10
0x40
0x80
0x80
void Initial_SPI(void)
{
SPICTL |= (SSIG | SPEN | MSTR | CPOL | CPHA);
}
void SPI_Write(unsigned char arg)
{
SPIDAT = arg;
while(!(SPISTAT & SPIF));
SPISTAT &= ~SPIF;
}
unsigned char SPI_Read(void)
{
SPIDAT = 0xFF;
while(!SPISTAT & SPIF);
SPISTAT &= ~SPIF;
return SPIDAT;
}
MEGAWIN
;initial SPI
;enable SPI and Master mode
// enable SPI and Master mode
//write arg
//wait transfer finishes
//clear SPI interrupt flag
//trigger SPI read
//wait transfer finishes
//clear SPI interrupt flag
MPC82x52 Data Sheet
99
18. 8-Bit ADC
The ADC subsystem for the MPC82E/L52 consists of an analog multiplexer (AMUX), and a 100 ksps, 8-bit
successive-approximation-register ADC. The AMUX can be configured via the Special Function Registers shown
in Figure 18–1. ADC operates in Single-ended modes, and may be configured to measure any of the pins on Port
1. The ADC subsystem is enabled only when the ADCON bit in the ADC Control register (ADCTL) is set to logic 1.
The ADC subsystem is in low power shutdown when this bit is logic 0.
18.1. ADC Structure
Figure 18–1. ADC Block Diagram
AMUX
B9
B8
B7
B6
B5
B4
B3
(P1.0) AIN0
B2
ADCV
(P1.1) AIN1
(P1.2) AIN2
(P1.3) AIN3
AIN
8
8-Bit ADC
(100 ksps)
(P1.4) AIN4
(P1.5) AIN5
(P1.6) AIN6
Load
(P1.7) AIN7
SYSCLK
/1080
/810
/540
/270
ADCON SPEED1 SPEED0
ADCI
ADCS
CH2
CH1
CH0
ADCTL
Software writes "1" to
start ADC conversion
18.2. ADC Operation
ADC has a maximum conversion speed of 100 ksps. The ADC conversion clock is a divided version of the
system clock, determined by the SPEED1~0 bits in the ADCTL register.
After the conversion is complete (ADCI is high), the conversion result can be found in the ADC Result Registers
(ADCV). For single ended conversion, the result is
ADC Result =
100
VIN x 256
VDD Voltage
MPC82x52 Data Sheet
MEGAWIN
18.2.1. ADC Input Channels
The analog multiplexer (AMUX) selects the inputs to the ADC, allowing any of the pins on Port 1 to be measured
in single-ended mode. The ADC input channels are configured and selected by CHS.2~0 in the ADCTL register
as described in Figure 18–1. The selected pin is measured with respect to GND.
18.2.2. Starting a Conversion
Prior to using the ADC function, the user should:
1)
2)
3)
4)
Turn on the ADC hardware by setting the ADCON bit,
Configure the ADC input clock by bits SPEED1 and SPEED0,
Select the analog input channel by bits CHS2, CHS1 and CHS0,
Configure the selected input (shared with P1) to the Input-Only mode by P1M0 and P1M1 registers, and
Now, user can set the ADCS bit to start the A-to-D conversion. The conversion time is controlled by bits SPEED1
and SPEED0. Once the conversion is completed, the hardware will automatically clear the ADCS bit, set the
interrupt flag ADCI and load the 8 bits of conversion result into ADCV simultaneously.
As described above, the interrupt flag ADCI, when set by hardware, shows a completed conversion. Thus two
ways may be used to check if the conversion is completed: (1) Always polling the interrupt flag ADCI by software;
(2) Enable the ADC interrupt by setting bits EADCI (in AUXR register), ESPI_ADC (in IE register) and EA (in IE
register), and then the CPU will jump into its Interrupt Service Routine when the conversion is completed.
Regardless of (1) or (2), the ADCI flag should be cleared by software before next conversion.
18.2.3. ADC Conversion Time
The user can select the appropriate conversion speed according to the frequency of the analog input signal. User
can configure the SPEED1~0 in ADCTL to specify the conversion rate. For example, if SYSCLK =25MHz and the
SPEED[1:0] = SYSCLK/270 is selected, then the frequency of the analog input should be no more than 92.6KHz
to maintain the conversion accuracy. (Conversion rate = 25MHz/270 = 92.6KHz.)
18.2.4. I/O Pins Used with ADC Function
The analog input pins used for the A/D converters also have its I/O port ‗s digital input and output function. In
order to give the proper analog performance, a pin that is being used with the ADC should have its digital output
as disabled. It is done by putting the port pin into the input-only mode as described in the Section ―12
Configurable I/O Ports‖.
18.2.5. Idle and Power-Down Mode
In Power-Down mode, the ADC does not function. If the A/D is turned on, it will consume a little power. So, power
consumption can be reduced by turning off the ADC hardware (ADCON=0) before entering Idle mode and PowerDown mode.
MEGAWIN
MPC82x52 Data Sheet
101
18.3. ADC Register
ADCTL: ADC Control Register
SFR Address = 0xC5
7
6
5
ADCON
SPEED1
SPEED0
4
ADCI
R/W
R/W
R/W
R/W
RESET = 0000-0000
3
2
ADCS
CHS2
R/W
R/W
1
CHS1
0
CHS0
R/W
R/W
Bit 7: ADCON, ADC Enable.
0: Clear to turn off the ADC block.
1: Set to turn on the ADC block. At least 5us ADC enabled time is required before set ADCS.
Bit 6~5: SPEED1 and SPEED0, ADC conversion speed control.
SPEED[1:0]
ADC Clock Selection
0 0
SYSCLK/1080
0 1
SYSCLK/810
1 0
SYSCLK/540
1 1
SYSCLK/270
The recommended ADC clock is no more than 12MHz.
Bit 4: ADCI, ADC Interrupt Flag.
0: The flag must be cleared by software.
1: This flag is set when an A/D conversion is completed. An interrupt is invoked if it is enabled.
Bit 3: ADCS. ADC Start of conversion.
0: ADCS cannot be cleared by software.
1: Setting this bit by software starts an A/D conversion. On completion of the conversion, the ADC hardware will
clear ADCS and set the ADCI. A new conversion may not be started while either ADCS or ADCI is high.
Bit 2~0: CHS2 ~ CHS1, Input Channel Selection for ADC analog multiplexer.
CHS[2:0]
Selected Channel
0 0 0
AIN0 (P1.0)
0 0 1
AIN1 (P1.1)
0 1 0
AIN2 (P1.2)
0 1 1
AIN3 (P1.3)
1 0 0
AIN4 (P1.4)
1 0 1
AIN5 (P1.5)
1 1 0
AIN6 (P1.6)
1 1 1
AIN7 (P1.7)
ADCV: ADC Result Register
SFR Address = 0xC6
7
6
5
ADCV.7
ADCV.6
ADCV.5
4
ADCV.4
R
R
R
R
RESET = xxxx-xxxx
3
2
ADCV.3
ADCV.2
R
R
1
ADCV.1
0
ADCV.0
R
R
In MPC82E/L52, conversion codes are represented as 8-bit unsigned integers. Inputs are measured from ‗0‘ to
VDD x 255/256. Example codes are shown below.
Input Voltage
VDD x 255/256
VDD x 128/256
VDD x 64/256
0
102
ADCV
0xFF
0x80
0x40
0x00
MPC82x52 Data Sheet
MEGAWIN
18.4. ADC Sample Code
(1). Required Function: ADC sample code for SYSCLK=24MHz, transfer analog input on P1.0/P1.1/P1.2 with
SPEED[1:0]=SYSCLK/270 for 88.9KHz conversion rate.
Assembly Code Example:
CHS0
EQU
CHS1
EQU
ADCS
EQU
ADCI
EQU
SPEED0
EQU
SPEED1
EQU
ADCON
EQU
01h
02h
08h
10h
20h
40h
80h
INITIAL_ADC_PIN:
ORL P1M0, #00000111B
ANL P1M1,#11111000B
; P1.0, P1.1, P1.2 = input only
MOV ADCTL,#ADCON
; delay 5us
; call ....
Get_P10:
MOV
; Enable ADC block
ADCTL, #(ADCON + SPEED1 + SPEED0)
; Enable ADC block & start conversion
; Speed at 114.3k @ 24MHz, select P1.0 for ADC input pin
CALL delay_5us
ORL ADCTL, #ADCS
MOV A, ADCTL
JNB ACC.4,$-3
ANL ADCTL,#(0FFh - ADCI - ADCS)
MOV AIN0_data_V,ADCV
; to do ...
; check ready?
; clear ADCI & ADCS
; reserve P1.0 ADC data
Get_P11:
MOV ADCTL,#(ADCON + SPEED1 + SPEED0 + CHS0) ; select P1.1
CALL delay_5us
ORL ADCTL, #ADCS
MOV
JNB
ANL
MOV
; to do ...
A, ADCTL
ACC.4,$-3
ADCTL,# (0FFh - ADCI - ADCS)
AIN1_data_V,ADCV
; check ready?
; clear ADCI & ADCS
Get_P12:
MOV ADCTL,#(ADCON + SPEED1 + SPEED0 + CHS1) ; select P1.2
CALL delay_5us
ORL ADCTL, #ADCS
MOV
JNB
ANL
MOV
ACC,ADCTL
ACC.4,$-3
ADCTL,# (0FFh - ADCI - ADCS)
AIN2_data_V,ADCV
; check ready?
; clear ADCI & ADCS
; to do ...
RET
C Code Example:
#define CHS0
#define CHS1
#define ADCS
#define ADCI
#define SPEED0
#define SPEED1
MEGAWIN
0x01
0x02
0x08
0x10
0x20
0x40
MPC82x52 Data Sheet
103
#define ADCON
0x80
void main(void)
{
unsigned char AIN0_data_V, AIN1_data_V, AIN2_data_V;
P1M0 |= 0x07;
P1M1 &= ~0x07;
// P1.0, P1.1, P1.2 = input only
ADCTL = ADCON;
// delay 5us
// ...
// Enable ADC block
// select P1.0
ADCTL = (ADCON | SPEED1 | SPEED0);
// Enable ADC block & start conversion
// Speed at 114.3k @ 24MHz, select P1.0 for ADC input pin
Delay_5us();
ADCTL |= ADCS;
while ((ADCTL & ADCI) == 0x00);
ADCTL &= ~(ADCI | ADCS);
AIN0_data_V = ADCV;
//wait for complete
// to do ...
// select P1.1
ADCTL = (ADCON | SPEED1 | SPEED0 | CHS0);
Delay_5us();
ADCTL |= ADCS;
// select P1.1
while ((ADCTL & ADCI) == 0x00);
ADCTL &= ~(ADCI | ADCS);
AIN1_data_V = ADCV;
//wait for complete
// to do ...
// select P1.2
ADCTL = (ADCON | SPEED1 | SPEED0 | CHS1);
Delay_5us();
ADCTL |= ADCS;
while ((ADCTL & ADCI) == 0x00);
ADCTL &= ~(ADCI | ADCS);
AIN2_data_V = ADCV;
// select P1.2
//wait for complete
// to do ...
while (1);
}
104
MPC82x52 Data Sheet
MEGAWIN
19. ISP and IAP
The flash memory of MPC82E/L52 is partitioned into AP-memory, IAP-memory and ISP-memory. AP-memory is
used to store user‘s application program; IAP-memory is used to store the non-volatile application data; and, ISPmemory is used to store the boot loader program for In-System Programming. When MCU is running in ISP
region, MCU could modify the AP and IAP memory for software upgraded. If MCU is running in AP region,
software could only modify the IAP memory for storage data updated.
19.1. MPC82E/L52 Flash Memory Configuration
There are total 8K bytes of Flash Memory in MPC82E/L52 and Figure 19–1 shows the device flash configuration
of MPC82E/L52. The ISP-memory can be configured as disabled or up to 3K bytes space by hardware option.
The flash size of IAP memory is located between the IAP low boundary and IAP high boundary. The IAP low
boundary is defined by the value of IAPLB register. The IAP high boundary is associated with ISP start address
which decides ISP memory size by hardware option. The IAPLB register value is configured by hardware option.
All of the AP, IAP and ISP memory are shared the total 8K bytes flash memory.
Figure 19–1. MPC82E/L52 Flash Memory Configuration
Note:
(1) If ISP space is enabled
ISP Start address can be configured to:
0x1400 if ISP Space = 3.0KB
0x1800 if ISP Space = 2.0KB
0x1C00 if ISP Space = 1.0KB
AP Start Address 0x0000
And, the IAP space is configured to:
IAP High Boundary = ISP Start Address – 1
IAP Low Boundary = ISP Start Address – IAP Size
(2) If ISP Space is disabled:
IAP High Boundary = 0x1FFF
IAP Low Boundary = 0x1FFF – IAP Size + 1
Application Code
AP-memory
Flash Memory
Total: 8KB
IAP Low Boundary
IAP Data
IAP-memory
ISP Code
ISP-memory
IAP High Boundary
ISP Start Address
0x1FFF
Note:
In default, the MPC82E/L52 that Megawin shipped had configured the flash memory for 1K ISP, 1K IAP and
Lock enabled. The 1K ISP region is inserted Megawin proprietary ISP code to perform In-SystemProgramming through Megawin 1-Line ISP protocol. The IAP size can be re-configured by writer to modify
IAPLB.
MEGAWIN
MPC82x52 Data Sheet
105
19.2. MPC82E/L52 Flash Access in ISP/IAP
There are 3 flash access modes are provided in MPC82E/L52 for ISP and IAP application: page erase mode,
program mode and read mode. MCU software uses these three modes to update new data into flash storage and
get flash content. This section shows the flow chart and demo code for the various flash modes.
19.2.1. ISP/IAP Flash Page Erase Mode
The any bit in flash data of MPC82E/L52 only can be programmed to ―0‖. If user would like to write a ―1‖ into flash
data, the flash erase is necessary. But the flash erase in MPC82E/L52 ISP/IAP operation only support ―page
erase‖ mode, a page erase will write all data bits to ―1‖ in one page. There are 512 bytes in one page of
MPC82E/L52 and the page start address is aligned to A8~A0 = 0x000. The targeted flash address is defined in
IFADRH and IFADRL. So, in flash page erase mode, the IFADRH.0(A8) and IFADRL.7~0(A7~A0) must be
written to ―0‖ for right page address selection. Figure 19–2 shows the flash page erase flow in ISPIAP operation.
Figure 19–2. ISP/IAP Page Erase Flow
Start
Define ISP/IAP
time base
==> Configure ISPCR.WAIT.2~0
Enable ISP/IAP
engine
==> Set ISPCR.ISPEN = "1"
Set "Page Erase"
Mode
NO
==> Write IFMT.MS4~0 = "00011"
Define targeted
flash page address
==> Define IFADRH & IFADRL
Trigger engine for
"Erase"
==> Write SCMD = 0x46, then
==> Write SCMD = 0xB9
end of page
YES
Set Standby and
disable engine
==> Write IFMT.MS4~0 = "00000"
==> Set ISPCR.ISPEN = "0"
End
106
MPC82x52 Data Sheet
MEGAWIN
Figure 19–3 shows the demo code of the ISP/IAP page erase operation.
Figure 19–3. Assemble code example for ISP/IAP Page Erase
MOV
ISPCR,#00010111b ; XCKS4~0 = decimal 23 when OSCin = 24MHz
MOV
ISPCR,#10000000b ; ISPCR.7 = 1, enable ISP
MOV
IFMT,#03h
; select Page Erase Mode
MOV
MOV
IFADRH,??
IFADRL,??
; fill [IFADRH,IFADRL] with page address
;
MOV
MOV
SCMD,#46h
SCMD,#0B9h
; trigger ISP/IAP processing
;
;Now, MCU will halt here until processing completed
MOV
MOV
IFMT,#00h
; select Standby Mode
ISPCR,#00000000b ; ISPCR.7 = 0, disable ISP
MEGAWIN
MPC82x52 Data Sheet
107
19.2.2. ISP/IAP Flash Program Mode
The ―program‖ mode of MPC82E/L52 provides the byte write operation into flash memory for new data updated.
The IFADRH and IFADRL point to the physical flash byte address. IFD stores the content which will be
programmed into the flash. Figure 19–4 shows the flash byte program flow in ISP/IAP operation.
Figure 19–4. ISP/IAP byte Program Flow
Start
NO
Define ISP/IAP
time base
==> Configure ISPCR.WAIT.2~0
Enable ISP/IAP
engine
==> Set ISPCR.ISPEN = "1"
Set byte "Program"
mode
==> Write IFMT.MS4~0 = "00010"
Define targeted
flash byte address
==> Define IFADRH & IFADRL
Ready for
new stored data
==> Write updated data to IFD
Trigger engine for
"Program"
==> Write SCMD = 0x46, then
==> Write SCMD = 0xB9
end of address
YES
Set Standby and
disable engine
==> Write IFMT.MS4~0 = "00000"
==> Set ISPCR.ISPEN = "0"
End
108
MPC82x52 Data Sheet
MEGAWIN
Figure 19–5 shows the demo code of the ISP/IAP byte program operation.
Figure 19–5. Assemble code example for ISP/IAP byte Program
MOV
ISPCR,#00010111b ; XCKS4~0 = decimal 23 when OSCin = 24MHz
MOV
ISPCR,#10000011b ; ISPCR.7=1, enable ISP
MOV
IFMT,#02h
; select Program Mode
MOV
MOV
IFADRH,??
IFADRL,??
; fill [IFADRH,IFADRL] with byte address
;
MOV
IFD,??
MOV
MOV
SCMD,#46h
SCMD,#0B9h
; fill IFD with the data to be programmed
;trigger ISP/IAP processing
;
;Now, MCU will halt here until processing completed
MOV
MOV
IFMT,#00h
; select Standby Mode
ISPCR,#00000000b ; ISPCR.7 = 0, disable ISP
MEGAWIN
MPC82x52 Data Sheet
109
19.2.3. ISP/IAP Flash Read Mode
The ―read‖ mode of MPC82E/L52 provides the byte read operation from flash memory to get the stored data. The
IFADRH and IFADRL point to the physical flash byte address. IFD stores the data which is read from the flash
content. It is recommended to verify the flash data by read mode after data programmed or page erase.
Figure 19–6 shows the flash byte read flow in ISP/IAP operation.
Figure 19–6. ISP/IAP byte Read Flow
Start
NO
Define ISP/IAP
time base
==> Configure ISPCR.WAIT.2~0
Enable ISP/IAP
engine
==> Set ISPCR.ISPEN = "1"
Set byte "Read"
mode
==> Write IFMT.MS4~0 = "00001"
Define targeted
flash byte address
==> Define IFADRH & IFADRL
Trigger engine for
"Read"
==> Write SCMD = 0x46, then
==> Write SCMD = 0xB9
Get data
==> Read stored data from IFD
end of address
YES
Set Standby and
disable engine
==> Write IFMT.MS4~0 = "00000"
==> Set ISPCR.ISPEN = "0"
End
110
MPC82x52 Data Sheet
MEGAWIN
Figure 19–7 shows the demo code of the ISP/IAP byte read operation.
Figure 19–7. Assemble code example for ISP/IAP byte Read
MOV
ISPCR,#00010111b ; XCKS4~0 = decimal 23 when OSCin = 24MHz
MOV
ISPCR,#10000011b ; ISPCR.7=1, enable ISP
MOV
IFMT,#01h
; select Read Mode
MOV
MOV
IFADRH,??
IFADRL,??
; fill [IFADRH,IFADRL] with byte address
;
MOV
MOV
SCMD,#46h
SCMD,#0B9h
; trigger ISP/IAP processing
;
;Now, MCU will halt here until processing completed
MOV
A,IFD
MOV
MOV
IFMT,#00h
; select Standby Mode
ISPCR,#00000000b ; ISPCR.7 = 0, disable ISP
MEGAWIN
; now, the read data exists in IFD
MPC82x52 Data Sheet
111
19.3. ISP Operation
ISP means In-System-Programming which makes it possible to update the user‘s application program (in APmemory) and non-volatile application data (in IAP-memory) without removing the MCU chip from the actual end
product. This useful capability makes a wide range of field-update applications possible. The ISP mode is used in
the loader program to program both the AP-memory and IAP-memory.
Note:
(1) Before using the ISP feature, the user should configure an ISP-memory space and pre-program the ISP
code (loader program) into the ISP-memory by a universal Writer/Programmer or Megawin proprietary
Writer/Programmer.
(2) ISP code in the ISP-memory can only program the AP-memory and IAP-memory.
After ISP operation has been finished, software writes ―001‖ on ISPCR.7 ~ ISPCR.5 which triggers an software
RESET and makes CPU reboot into application program memory (AP-memory) on the address 0x0000.
As we have known, the purpose of the ISP code is to program both AP-memory and IAP-memory. Therefore, the
MCU must boot from the ISP-memory in order to execute the ISP code. There are two methods to implement
In-System Programming according to how the MCU boots from the ISP-memory.
19.3.1. Hardware approached ISP
To make the MCU directly boot from the ISP-memory when it is just powered on, the MCU‘s hardware options
HWBS and ISP Memory must be enabled. The ISP entrance method by hardware option is named hardware
approached. Once HWBS and ISP Memory are enabled, the MCU will always boot from the ISP-memory to
execute the ISP code (loader program) when it is just powered on. The first thing the ISP code should do is to
check if there is an ISP request. If there is no ISP requested, the ISP code should trigger a software reset (setting
ISPCR.7~5 to ―101‖ simultaneously) to make the MCU re-boot from the AP-memory to run the user‘s application
program.
The following sample code describes how to leave hardware approach ISP memory to launch AP software:
Code example for ISP reset to AP or AP reset to AP
Assembly Code Example:
SWRST
EQU
SWBS
EQU
ANL
ORL
20h
40h
ISPCR, #(0FFh - SWBS)
ISPCR, #SWRST
C Code Example:
#define SWRST
#define SWBS
;clear SWBS
;trigger software reset
0x20
0x40
ISPCR &= ~SWBS;
ISPCR |= SWRST;
112
// clear SWBS
// trigger software reset
MPC82x52 Data Sheet
MEGAWIN
19.3.2. Software approached ISP
The software approached ISP to make the MCU boot from the ISP-memory is to trigger a software reset while the
MCU is running in the AP-memory. In this case, neither HWBS nor HWBS2 is enabled. The only way for the
MCU to boot from the ISP-memory is to trigger a software reset, setting ISPCR.7~5 to ―111‖ simultaneously,
when running in the AP-memory. Note: the ISP memory must be configured a valid space by hardware option to
reserve ISP mode for software approached ISP application.
The following sample code describes how to leave AP memory to launch software approached ISP:
Code example for AP reset to ISP
Assembly Code Example:
SWRST
EQU
SWBS
EQU
ORL
20h
40h
ISPCR, #( SWBS + SWRST)
;set SWBS and trigger software
reset
C Code Example:
#define SWRST
#define SWBS
0x20
0x40
ISPCR |=(SWBS + SWRST);
software reset
MEGAWIN
//
MPC82x52 Data Sheet
set
SWBS
and
trigger
113
19.3.3. Notes for ISP
Developing of the ISP Code
Although the ISP code is programmed in the ISP-memory that has an ISP Start Address in the MCU‘s Flash (see
Figure 19–1), it doesn‘t mean you need to put this offset (= ISP Start Address) in your source code. The code
offset is automatically manipulated by the hardware. User just needs to develop it like an application program in
the AP-memory.
Interrupts during ISP
After triggering the ISP/IAP flash processing, the MCU will halt for a while for internal ISP processing until the
processing is completed. At this time, the interrupt will queue up for being serviced if the interrupt is enabled
previously. Once the processing is completed, the MCU continues running and the interrupts in the queue will be
serviced immediately if the interrupt flag is still active. The user, however, should be aware of the following:
(1) Any interrupt can not be in-time serviced when the MCU halts for ISP processing.
(2) The low/high-level triggered external interrupts, INTx, should keep activated until the ISP is completed, or
they will be neglected.
ISP and Idle mode
MPC82E/L52 does not make use of idle-mode to perform ISP function. Instead, it freezes CPU running to release
the flash memory for ISP/IAP engine operating. Once ISP/IAP operation finished, CPU will be resumed and
advanced to the instruction which follows the previous instruction that invokes ISP/AP activity.
Accessing Destination of ISP
As mentioned previously, the ISP is used to program both the AP-memory and the IAP-memory. Once the
accessing destination address is beyond that of the last byte of the IAP-memory, the hardware will automatically
neglect the triggering of ISP processing. That is the triggering of ISP is invalid and the hardware does nothing.
Flash Endurance for ISP
The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles
shouldn‘t exceed 20,000 times. Thus the user should pay attention to it in the application which needs to
frequently update the AP-memory and IAP-memory.
114
MPC82x52 Data Sheet
MEGAWIN
19.3.4. Default ISP Code in MPC82E/L52
Although the user may design self ISP, MPC82E/L52 has been inserted the Megawin proprietary ISP code before
shipping. Megawin provides a tool, Megawin 8051 ISP Programmer, to perform In-System-Programming for AP
program code upgraded. This section shows a brief description for the Megawin ISP behavior.
Features




The standard ‗ISP code‘ is pre-programmed in factory before shipping.
Only one port pin (P3.1) used for the ISP interface.
Operation independent of the oscillator frequency.
Capable of stand-alone working without host‘s intervention.
The above valuable features make the ISP Programmer very friendly to the user. Particularly, it is capable of
stand-alone working after the programming data is downloaded. This is especially useful in the field without a PC.
The system diagram of the ―Megawin 8051 ISP Programmer‖ is shown in Figure 19–8. Only three pins are used
for the ISP interface: the DTA line transmits the programming data from the ISP Programmer to the target MCU;
the VCC & GND are the power supply entry of the ISP Programmer. Section ―22.4 ISP Interface Circuit‖
describes the ISP interface circuit of the MCU applied in user system. The USB connector of the ISP tool can be
directly plugged into the PC‘s USB port to download the programming data from PC to the ISP Programmer.
Figure 19–8. System Diagram for the ISP Function
Target System
START button: for code programming
MCU
ISP Interface
USB
VDD
P3.1
VSS
Megawin standard
"ISP Code"
Inserted
MEGAWIN
VCC
SDA
GND
(less than 20cm)
VCC
SDA
GND
MEGAWIN
MAKE YOU WIN
ISP Programmer
Program code
download path
"Megawin 8051 ISP Programmer"
MPC82x52 Data Sheet
115
19.4. In-Application-Programming (IAP)
The MPC82E/L52 has built a function as In Application Programmable (IAP), which allows some region in the
Flash memory to be used as non-volatile data storage while the application program is running. This useful
feature can be applied to the application where the data must be kept after power off. Thus, there is no need to
use an external serial EEPROM (such as 93C46, 24C01, .., and so on) for saving the non-volatile data.
In fact, the operating of IAP is the same as that of ISP except the Flash range to be programmed is different. The
programmable Flash range for ISP operating is located within the AP and IAP memory, while the range for IAP
operating is only located within the configured IAP-memory.
Note:
(1) For MPC82E/L52 IAP feature, the software should specify an IAP-memory space by writing IAPLB in
Page-P SFR space. The IAP-memory space can be also configured by a universal Writer/Programmer or
Megawin proprietary Writer/Programmer which configuration is corresponding to IAPLB initial value.
(2) The program code to execute IAP is located in the AP-memory and just only program IAP-memory not
ISP-memory.
19.4.1. IAP-memory Boundary/Range
If ISP-memory is specified, the range of the IAP-memory is determined by IAP and the ISP starts address as
listed below.
IAP high boundary = ISP start address –1.
IAP low boundary = ISP start address - IAP.
If ISP-memory is not specified, the range of the IAP-memory is determined by the following formula.
IAP high boundary = 0x1FFF.
IAP low boundary = 0x1FFFF – IAP + 1.
For example, if ISP-memory is 1K, so that ISP start address is 0x1C00, and IAP-memory is 1K, then the IAPmemory range is located at 0x1800 ~ 0x1BFF. The IAP low boundary in MPC82E/L52 is defined by IAPLB
register which can only be modified by writer.
19.4.2. Update data in IAP-memory
The special function registers are related to ISP/IAP would be shown in Section ―19.5 ISP/IAP Register―.
Because the IAP-memory is a part of Flash memory, only Page Erase, no Byte Erase, is provided for Flash
erasing. To update ―one byte‖ in the IAP-memory, users can not directly program the new datum into that byte.
The following steps show the proper procedure:
Step 1: Save the whole page flash data (with 512 bytes) into XRAM buffer which contains the data to be updated.
Step 2: Erase this page (using ISP/IAP Flash Page Erase mode).
Step 3: Modify the new data on the byte(s) in the XRAM buffer.
Step 4: Program the updated data out of the XRAM buffer into this page (using ISP/IAP Flash Program mode).
To read the data in the IAP-memory, users can use the ISP/IAP Flash Read mode to get the targeted data.
116
MPC82x52 Data Sheet
MEGAWIN
19.4.3. Notes for IAP
Interrupts during IAP
After triggering the ISP/IAP flash processing for In-Application Programming, the MCU will halt for a while for
internal IAP processing until the processing is completed. At this time, the interrupt will queue up for being
serviced if the interrupt is enabled previously. Once the processing is completed, the MCU continues running and
the interrupts in the queue will be serviced immediately if the interrupt flag is still active. Users, however, should
be aware of the following:
(1) Any interrupt cannot be in-time serviced during the MCU halts for IAP processing.
(2) The low/high-level triggered external interrupts, INTx, should keep activated until the IAP is completed, or
they will be neglected.
IAP and Idle mode
MPC82E/L52 does not make use of idle-mode to perform IAP function. Instead, it freezes CPU running to release
the flash memory for ISP/IAP engine operating. Once ISP/IAP operation finished, CPU will be resumed and
advanced to the instruction which follows the previous instruction that invokes ISP/AP activity.
Accessing Destination of IAP
As mentioned previously, the IAP is used to program only the IAP-memory. Once the accessing destination is not
within the IAP-memory, the hardware will automatically neglect the triggering of IAP processing. That is the
triggering of IAP is invalid and the hardware does nothing.
An Alternative Method to Read IAP Data
To read the Flash data in the IAP-memory, in addition to using the Flash Read Mode, the alternative method is
using the instruction ―MOVC A,@A+DPTR‖. Where, DPTR and ACC are filled with the wanted address and the
offset, respectively. And, the accessing destination must be within the IAP-memory, or the read data will be
indeterminate. Note that using ‗MOVC‘ instruction is much faster than using the Flash Read Mode.
Flash Endurance for IAP
The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles
shouldn‘t exceed 20,000 times. Thus the user should pay attention to it in the application which needs to
frequently update the IAP-memory.
MEGAWIN
MPC82x52 Data Sheet
117
19.5. ISP/IAP Register
The following special function registers are related to the access of ISP and IAP operation:
IFD: ISP/IAP Flash Data Register
SFR Address = 0xE2
7
6
5
4
R/W
R/W
R/W
R/W
RESET = 1111-1111
3
2
R/W
R/W
1
0
R/W
R/W
IFD is the data port register for ISP/IAP operation. The data in IFD will be written into the desired address in
operating ISP/IAP write and it is the data window of readout in operating ISP/IAP read.
IFADRH: ISP/IAP Address for High-byte addressing
SFR Address = 0xE3
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
IFADRL: ISP/IAP Address for Low-byte addressing
SFR Address = 0xE4
RESET = 0000-0000
7
6
5
4
3
2
1
0
R/W
R/W
R/W
1
MS.1
0
MS.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IFADRH is the high-byte address port for all ISP/IAP modes.
R/W
R/W
R/W
R/W
R/W
IFADRL is the low byte address port for all ISP/IAP modes.
IFMT: ISP/IAP Flash Mode Table
SFR Page
= Normal
SFR Address = 0xE5
7
6
5
----
4
MS.4
W
W
W
W
RESET = xxxx-xx00
3
2
MS.3
MS.2
W
W
Bit 7~5: Reserved. Software must write ―0000_0‖ on these bits when IFMT is written.
Bit 3~0: ISP/IAP/Page-P operating mode selection
MS[4:0]
Mode
0 0 0 0 0
Standby
0 0 0 0 1
Flash byte read of AP/IAP-memory
0 0 0 1 0
Flash byte program of AP/IAP-memory
0 0 0 1 1
Flash page erase of AP/IAP-memory
Others
Reserved
IFMT is used to select the flash mode for performing numerous ISP/IAP function.
SCMD: Sequential Command Data register
SFR Address = 0xE6
7
6
5
4
SCMD
R/W
R/W
R/W
R/W
RESET = xxxx-xxxx
3
2
R/W
R/W
1
0
R/W
R/W
SCMD is the command port for triggering ISP/IAP activity. If SCMD is filled with sequential 0x46h, 0xB9h and if
ISPCR.7 = 1, ISP/IAP activity will be triggered.
118
MPC82x52 Data Sheet
MEGAWIN
ISPCR: ISP Control Register
SFR Address = 0xE7
7
6
5
ISPEN
SWBS
SWRST
4
CFAIL
R/W
R/W
R/W
R/W
RESET = 0000-0xxx
3
2
-WAIT.2
W
R/W
1
WAIT.1
0
WAIT.0
R/W
R/W
Bit 7: ISPEN, ISP/IAP/Page-P operation enable.
0: Global disable all ISP/IAP/Page-P program/ read function.
1: Enable ISP/IAP/Page-P program/ read function.
Bit 6: SWBS, software boot selection control.
0: Boot from main-memory after reset.
1: Boot from ISP memory after reset.
Bit 5: SWRST, software reset trigger control.
0: No operation
1: Generate software system reset. It will be cleared by hardware automatically.
Bit 4: CFAIL, Command Fail indication for ISP/IAP operation.
0: The last ISP/IAP command has finished successfully.
1: The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited.
Bit 3: Reserved. Software must write ―0‖ on this bit when ISPCR is written.
Bit 2~0: WAIT.2~0, Configure ISP timing according to the oscillator frequency.
WAIT[2:0]
OSCin Frequency (MHz)
0 0 0
> 24
0 0 1
20 ~ 24
0 1 0
12 ~ 20
0 1 1
6 ~ 12
1 0 0
3~6
1 0 1
2~3
1 1 0
1~2
1 1 1
<1
MEGAWIN
MPC82x52 Data Sheet
119
19.6. ISP/IAP Sample Code
(1). Required Function: General function call for ISP/IAP flash read
Assembly Code Example:
IxP_Flash_Read EQU
ISPEN
EQU
01h
80h
_ixp_read:
ixp_read:
MOV
MOV
ISPCR,#ISPEN
IFMT,# IxP_Flash_Read
MOV
MOV
IFADRH,??
IFADRL,??
MOV
MOV
SCMD,#046h
SCMD,#0B9h
MOV
MOV
ANL
A,IFD
; Enable Function
; ixp_read=0x01
; fill [IFADRH,IFADRL] with byte address
;
;
; now, the read data exists in IFD
IFMT,#000h
; Flash_Standby=0x00
ISPCR,#(0FFh – ISPEN)
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Read
#define ISPEN
0x00
0x01
0x80
unsigned char ixp_read (void)
{
unsigned char arg;
ISPCR = ISPEN;
IFMT = IxP_Flash_Read;
// Enable Function
// IxP_Read=0x01
IFADRH = ??
IFADRL = ??
SCMD = 0x46;
SCMD = 0xB9;
//
//
arg = IFD;
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
// Flash_Standby=0x00
return arg;
}
120
MPC82x52 Data Sheet
MEGAWIN
(2). Required Function: General function call for ISP/IAP flash Erase
Assembly Code Example:
IxP_Flash_ Erase EQU
ISPEN
EQU
03h
80h
_ixp_erase:
ixp_erase:
MOV
MOV
ISPCR,#ISPEN
; Enable Function
IFMT,# IxP_Flash_Erase
; ixp_erase=0x03
MOV
MOV
IFADRH,??
IFADRL,??
MOV
MOV
SCMD,#046h
SCMD,#0B9h
MOV
ANL
; fill [IFADRH,IFADRL] with byte address
;
;
IFMT,#000h
; Flash_Standby=0x00
ISPCR,#(0FFh – ISPEN)
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Erase
#define ISPEN
0x00
0x03
0x80
void ixp_erase (unsigned char Addr_H, unsigned char Addr_L)
{
ISPCR = ISPEN;
// Enable Function
IFMT = IxP_Flash_Erase;
// IxP_Erase=0x03
IFADRH = Addr_H;
IFADRL = Addr_L;
SCMD = 0x46;
SCMD = 0xB9;
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
//
//
// Flash_Standby=0x00
}
MEGAWIN
MPC82x52 Data Sheet
121
(3). Required Function: General function call for ISP/IAP flash program
Assembly Code Example:
IxP_Flash_Program
EQU
ISPEN
EQU
02h
80h
_ixp_program:
ixp_program:
MOV
MOV
ISPCR,#ISPEN
; Enable Function
IFMT,# IxP_Flash_Program
; ixp_program=0x03
MOV IFADRH,??
MOV IFADRL,??
MOV IFD, A
MOV
MOV
MOV
ANL
; fill [IFADRH,IFADRL] with byte address
; now, the program data exists in Accumulator
SCMD,#046h
SCMD,#0B9h
;
;
IFMT,#000h
; Flash_Standby=0x00
ISPCR,#(0FFh – ISPEN)
; Disable Function
RET
C Code Example:
#define Flash_Standby
#define IxP_Flash_Program
#define ISPEN
0x00
0x02
0x80
void ixp_program(unsigned char Addr_H, unsigned char Addr_L, unsigned char dta)
{
ISPCR = ISPEN;
// Enable Function
IFMT = IxP_Flash_Program;
// IxP_Program=0x02
IFADRH = Addr_H;
IFADRL = Addr_L;
IFD = dta;
SCMD = 0x46;
SCMD = 0xB9;
IFMT = Flash_Standby;
ISPCR &= ~ISPEN;
//
//
// Flash_Standby=0x00
}
122
MPC82x52 Data Sheet
MEGAWIN
20. Auxiliary SFRs
AUXR: Auxiliary Register
SFR Address = 0x8E
7
6
5
T0X12
T1X12
URM0X6
4
EADCI
R/W
R/W
R/W
R/W
RESET = 0000-00xx
3
2
ESPI
ENLVFI
R/W
R/W
1
--
0
--
W
W
Bit 7: T0X12, Timer 0 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 5: URM0X6, Serial Port mode 0 baud rate selector.
0: Clear to select SYSCLK/12 as the baud rate for UART Mode 0.
1: Set to select SYSCLK/2 as the baud rate for UART Mode 0.
Bit 4: EADCI, ADC interrupt enable register.
0: Disable ADC interrupt.
1: Enable ADC interrupt.
Bit 3: ESPI, Enable SPI interrupt.
0: Disable SPI interrupt.
1: Enable SPI interrupt.
Bit 2: ENLVFI, Enable LVD Interrupt.
0: Disable LVD (LVF) interrupt.
1: Enable LVD (LVF) interrupt.
Bit 1~0: Reserved. Software must write ―0‖ on these bits when AUXR is written.
MEGAWIN
MPC82x52 Data Sheet
123
21. Hardware Option
The MCU‘s Hardware Option defines the device behavior which cannot be programmed or controlled by software.
The hardware options can only be programmed by a Universal Programmer or the ―Megawin 8051 Writer U1‖.
After whole-chip erased, all the hardware options are left in ―disabled‖ state and there is no ISP-memory and IAPmemory configured. The MPC82E/L52 has the following Hardware Options:
LOCK:
: Enabled. Code dumped on a universal Writer or Programmer is locked to 0xFF for security.
: Disabled. Not locked.
SB:
: Enabled. Code dumped on a universal Writer or Programmer is scrambled for security.
: Disabled. Not scrambled.
ISP-memory Space:
The ISP-memory space is specified by its starting address. And, its higher boundary is limited by the Flash end
address, i.e., 0x1FFF. The following table lists the ISP space option in this chip. In default setting, MPC82E/L52
ISP space is configured to 1K that had been embedded Megawin proprietary ISP code to perform In-SystemProgramming through Megawin 1-Line ISP protocol.
ISP-memory Size
ISP Start Address
3K bytes
0x1400
2K bytes
1K bytes
0x1800
0x1C00
No ISP Space
--
HWBS:
: Enabled. When powered up, MCU will boot from ISP-memory if ISP-memory is configured.
: Disabled. MCU always boots from AP-memory.
IAP-memory Space:
The IAP-memory space specifies the user defined IAP space. The IAP-memory Space can be configured by
hardware option. In default, it is configured to 1K bytes.
ENLVR:
: Enabled. LVD will trigger a RESET event to CPU on AP program start address. (3.7V for 5V device and
2.3V for 3.3V device)
: Disabled. LVD can not trigger a RESET to CPU.
LVFWP:
: Enabled. LVF inhibits the flash write action in ISP/IAP operation. (3.7V for 5V device and 2.3V for 3.3V
device)
: Disabled. No inhibition on the flash-writing action.
OSCDN:
: Enabled. Low gain option on crystal oscillating circuit to reduce power consumption and EMI radiation. It is
applied for crystal < 12MHz.
: Disabled. Typical gain setting is up to 25MHz crystal supporting.
ENROSC:
: Enabled. Set MCU running internal 6MHz RC-oscillator after power-on.
: Disabled. Set MCU running crystal mode after power-on.
HWENW: Hardware loaded for ―ENW‖ of WDTCR.
: Enabled. Enable WDT and load the content of HWWIDL and HWPS2~0 to WDTCR after power-on.
: Disabled. WDT is not enabled automatically after power-on.
124
MPC82x52 Data Sheet
MEGAWIN
HWWIDL, HWPS2, HWPS1, HWPS0:
When HWENW is enabled, the content on these four fused bits will be loaded to WDTCR SFR after power-on.
WDSFWP:
: Enabled. The WDT SFRs, WIDL, PS2, PS1 and PS0 in WDTCR, will be write-protected.
: Disabled. The WDT SFRs, WIDL, PS2, PS1 and PS0 in WDTCR, are free for writing of software.
MEGAWIN
MPC82x52 Data Sheet
125
22. Application Notes
22.1. Power Supply Circuit
To have the MPC82E/L52 work with power supply varying from 4.5V to 5.5V for E-type and from 2.4V to 3.6V for
L-type, adding some external decoupling and bypass capacitors is necessary, as shown in Figure 22–1.
Figure 22–1. Power Supplied Circuit
Power Supply
MCU
VDD
0.1uF
10uF
VSS
22.2. Reset Circuit
Normally, the power-on reset can be successfully generated during power-up. However, to further ensure the
MCU a reliable reset during power-up, the external reset is necessary. Figure 22–2 shows the external reset
circuit, which consists of a capacitor CEXT connected to VDD (power supply) and a resistor REXT connected to
VSS (ground).
In general, REXT is optional because the RST pin has an internal pull-down resistor (RRST). This internal diffused
resistor to VSS permits a power-up reset using only an external capacitor CEXT to VDD.
See Section ―23.2 DC Characteristics‖ for RRST value.
Figure 22–2. Reset Circuit
Power Supply
MCU
VDD
4.7uF
CEXT
RST
47KΩ
REXT
RRST
(Optional)
VSS
126
MPC82x52 Data Sheet
MEGAWIN
22.3. XTAL Oscillating Circuit
To achieve successful and exact oscillating (up to 25MHz), the capacitors C1 and C2 are necessary, as shown in
Figure 22–3. Normally, C1 and C2 have the same value. Table 22–1 lists the C1 & C2 value for the different
frequency crystal application.
Figure 22–3. XTAL Oscillating Circuit
MCU
XTAL2
Crystal
XTAL1
C2
C1
Table 22–1. Reference Capacitance of C1 & C2 for crystal oscillating circuit
Crystal
C1, C2 Capacitance
16MHz ~ 25MHz
10pF
6MHz ~ 16MHz
2MHz ~ 6MHz
15pF
33pF
MEGAWIN
MPC82x52 Data Sheet
127
22.4. ISP Interface Circuit
MPC82E/L52 has been inserted Megawin standard ISP code before shipping which embeds Megawin proprietary
1-Line ISP protocol. The ISP interface allows the P3.1 pin to be shared with user functions so that In-System
Flash Programming function could be performed. This is practicable because ISP communication is performed
when the device is running in the ISP memory, where the user software (AP memory) is stalled. In this state, the
Megawin ISP firmware can safely ‗borrow‘ the P3.1 pin. In most applications, external resistors are required to
isolate ISP interface traffic from the user application. A typical isolation configuration is shown in Figure 22–4.
Figure 22–4. ISP Interface Circuit
Target System
MCU
Power Supply
VDD
4.7KΩ
Input 1
P3.1
Output 1
VSS
Megawin 8051 ISP
Programmer
128
MPC82x52 Data Sheet
MEGAWIN
23. Electrical Characteristics
23.1. Absolute Maximum Rating
For MPC82E52:
Parameter
Rating
Unit
Ambient temperature under bias
-40 ~ +85
°C
Storage temperature
-65 ~ + 150
°C
Voltage on any Port I/O Pin or RST with respect to VSS
-0.5 ~ VDD + 0.5
V
Voltage on VDD with respect to VSS
-0.5 ~ +6.0
V
Maximum total current through VDD and VSS
400
mA
Maximum output current sunk by any Port pin
40
mA
*Note: stresses above those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
For MPC82L52:
Parameter
Rating
Unit
Ambient temperature under bias
-40 ~ +85
°C
Storage temperature
-65 ~ + 150
°C
Voltage on any Port I/O Pin or RESET with respect to Ground
-0.3 ~ VDD + 0.3
V
Voltage on VDD with respect to Ground
-0.3 ~ +4.2
V
Maximum total current through VDD and Ground
400
mA
Maximum output current sunk by any Port pin
40
mA
*Note: stresses above those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
MEGAWIN
MPC82x52 Data Sheet
129
23.2. DC Characteristics
For MPC82E52:
VDD = 5.0V±10%, VSS = 0V, TA = 25 ℃ and execute NOP for each machine cycle, unless otherwise specified
Limits
Unit
Symbol Parameter
Test Condition
min
typ
max
Input/Output Characteristics
VIH1
Input High voltage (All I/O Ports)
P0, P1, P2 and P3
2.0
V
VIH2
Input High voltage (RST)
3.5
VIL1
Input Low voltage (All I/O Ports)
P0, P1, P2 and P3
0.8
V
VIL2
Input Low voltage (RST)
0.8
V
Input High Leakage current (All
IIH
VPIN = VDD
0
10
uA
Input only or open-drain Ports)
IIL1
Logic 0 input current (Quasi-mode) VPIN = 0.45V
17
50
uA
Logic 0 input current (All Input only
IIL2
VPIN = 0.45V
0
10
uA
or open-drain Ports)
Logic 1 to 0 input transition current
IH2L
VPIN =1.8V
230
500
uA
(Quasi-mode)
IOH1
Output High current (Quasi-Mode) VPIN =2.4V
220
uA
Output High current (All push-pull
IOH2
VPIN =2.4V
12
20
mA
output ports)
IOL1
Output Low current (All I/O Ports) VPIN =0.45V
12
20
mA
RRST Internal reset pull-down resistance
100
Kohm
Power Consumption
SYSCLK = 12MHz @
IOP1
Normal mode operating current
12
30
mA
XTAL
SYSCLK = 12MHz @
IIDLE1 Idle mode operating current
6
15
mA
XTAL
IPD1
Power down mode current
0.1
50
uA
LVD Characteristics
SYSCLK = 12MHz @
(1)
VLVD LVD detection level
3.7
V
XTAL
Operating Condition
TA = -40℃ to +85℃
VPSR Power-on Slop Rate
0.05
V/ms
TA = -40℃ to +85℃
VOP1 Operating Speed 0–25MHz
4.5
5.5
V
TA = -40℃ to +85℃
VOP2 Operating Speed 0-12MHz
4.2
5.5
V
(1)
Data based on characterization results, not tested in production.
130
MPC82x52 Data Sheet
MEGAWIN
For MPC82L52:
VDD = 3.3V±10%, VSS = 0V, TA = 25 ℃ and execute NOP for each machine cycle, unless otherwise specified
Limits
Unit
Symbol Parameter
Test Condition
min
typ
max
Input/Output Characteristics
VIH1
Input High voltage (All I/O Ports)
P0, P1, P2 and P3
2.0
V
VIH3
Input High voltage (RST)
2.8
V
VIL1
Input Low voltage (All I/O Ports)
P0, P1, P2 and P3
0.8
V
VIL3
Input Low voltage (RST)
0.8
V
Input High Leakage current (All
IIH
VPIN = VDD
0
10
uA
Input only or open-drain Ports)
IIL1
Logic 0 input current (Quasi-mode) VPIN = 0.45V
7
50
uA
Logic 0 input current (All Input only
IIL2
VPIN = 0.45V
0
10
uA
or open-drain Ports)
Logic 1 to 0 input transition current
IH2L
VPIN =1.4V
100
600
uA
(Quasi-mode)
IOH1
Output High current (Quasi-Mode) VPIN =2.4V
64
uA
Output High current (All push-pull
IOH2
VPIN =2.4V
4
8
mA
output ports)
IOL1
Output Low current (All I/O Ports) VPIN =0.45V
8
14
mA
RRST Internal reset pull-down resistance
100
Kohm
Power Consumption
SYSCLK = 12MHz @
IOP1
Normal mode operating current
9
15
mA
XTAL
SYSCLK = 12MHz @
IIDLE1 Idle mode operating current
3.5
6
mA
XTAL
IPD1
Power down mode current
0.1
50
uA
LVD Characteristics
SYSCLK = 12MHz @
(1)
VLVD LVD detection level
2.3
V
XTAL
Operating Condition
TA = -40℃ to +85℃
VPSR Power-on Slop Rate
0.05
V/ms
TA = -40℃ to +85℃
VOP1 Operating Speed 0–25MHz
2.7
3.6
V
TA = -40℃ to +85℃
VOP2 Operating Speed 0-12MHz
2.4
3.6
V
(1)
Data based on characterization results, not tested in production.
MEGAWIN
MPC82x52 Data Sheet
131
23.3. External Clock Characteristics
For MPC82E52:
VDD = 4.5V ~ 5.5V, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
Oscillator
Symbol
Parameter
Crystal Mode
Min.
Max
1/tCLCL
Oscillator Frequency
2
25
Oscillator Frequency
1/tCLCL
2
12
(VDD = 4.2V ~ 5.5V)
tCLCL
Clock Period
40
tCHCX
High Time
0.4T
0.6T
tCLCX
Low Time
0.4T
0.6T
tCLCH
Rise Time
5
Fall Time
tCHCL
5
For MPC82L52:
VDD = 2.7V ~ 3.6V, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
Oscillator
Symbol
Parameter
Crystal Mode
Min.
Max
1/tCLCL
Oscillator Frequency
2
25
Oscillator Frequency
1/tCLCL
2
12
(VDD = 2.4V ~ 3.6V)
tCLCL
Clock Period
40
tCHCX
High Time
0.4T
0.6T
tCLCX
Low Time
0.4T
0.6T
tCLCH
Rise Time
5
Fall Time
tCHCL
5
Unit
MHz
MHz
ns
tCLCL
tCLCL
ns
ns
Unit
MHz
MHz
ns
tCLCL
tCLCL
ns
ns
Figure 23–1. External Clock Drive Waveform
TCHCX
TCLCH
TCHCL
VDD - 0.5V
0.7VDD
0.45V
0.2VDD - 0.1
TCLCX
TCLCL
132
MPC82x52 Data Sheet
MEGAWIN
23.4. IRCO Characteristics
For MPC82E52:
Parameter
Test Condition
Supply Voltage
IRCO Frequency
(1)
TA = +25℃
Limits
min
typ
4.5
(1)
4.2
(1)
6
Unit
max
5.5
(1)
7.8
V
MHz
Data based on characterization results, not tested in production.
For MPC82L52:
Limits
min
Typ
Supply Voltage
2.7
(1)
(1)
TA = +25℃
IRCO Frequency
4.2
6
(1)
Data based on characterization results, not tested in production.
Parameter
Test Condition
Unit
max
3.6
(1)
7.8
V
MHz
23.5. Flash Characteristics
For MPC82E52:
Parameter
Test Condition
Supply Voltage
Flash Write (Erase/Program) Voltage
Flash Erase/Program Cycle
Flash Data Retention
TA = -40℃ to +85℃
TA = -40℃ to +85℃
TA = -40℃ to +85℃
TA = +25℃
Limits
min
typ
4.2
4.5
20,000
100
Unit
max
5.5
5.5
V
V
times
year
For MPC82L52:
Parameter
Test Condition
Supply Voltage
Flash Write (Erase/Program) Voltage
Flash Erase/Program Cycle
Flash Data Retention
TA = -40℃ to +85℃
TA = -40℃ to +85℃
TA = -40℃ to +85℃
TA = +25℃
MEGAWIN
Limits
min
typ
2.4
2.7
20,000
100
MPC82x52 Data Sheet
Unit
max
3.6
3.6
V
V
times
year
133
23.6. Serial Port Timing Characteristics
For MPC82E52: VDD = 5.0V±10%, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
For MPC82L52: VDD = 3.3V±10%, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
URM0X3 = 0
URM0X3 = 1
Symbol
Parameter
Unit
Min.
Max
Min.
Max
Serial Port Clock Cycle Time
tXLXL
12T
4T
TSYSCLK
tQVXH
Output Data Setup to Clock Rising Edge
tXHQX
10T-20
T-20
ns
Output Data Hold after Clock Rising Edge T-10
T-10
ns
tXHDX
Input Data Hold after Clock Rising Edge
0
ns
tXHDV
Clock Rising Edge to Input Data Valid
0
10T-20
4T-20
ns
Figure 23–2. Shift Register Mode Timing Waveform
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
tXHDX
OUTPUT DATA
CLEAR RI
SET TI
tXHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
134
VALID
MPC82x52 Data Sheet
MEGAWIN
23.7. SPI Timing Characteristics
For MPC82E52: VDD = 5.0V±10%, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
For MPC82L52: VDD = 3.3V±10%, VSS = 0V, TA = -40℃ to +85℃, unless otherwise specified
Symbol
Parameter
Min
Max
Units
10
TSYSCLK
TSYSCLK
ns
ns
ns
TSYSCLK
TSYSCLK
TSYSCLK
Master Mode Timing
tMCKH
tMCKL
tMIS
tMIH
tMOH
2T
2T
2T+20
0
SPICLK High Time
SPICLK Low Time
MISO Valid to SPICLK Shift Edge
SPICLK Shift Edge to MISO Change
SPICLK Shift Edge to MOSI Change
Slave Mode Timing
tSE
tSD
tSEZ
nSS Falling to First SPICLK Edge
Last SPICLK Edge to nSS Rising
2T
2T
nSS Falling to MISO Valid
4T
tSDZ
tCKH
tCKL
tSIS
tSIH
tSOH
nSS Rising to MISO High-Z
4T
2T
TSYSCLK
4T
4T
2T
2T
SPICLK High Time
SPICLK Low Time
MOSI Valid to SPICLK Sample Edge
SPICLK Sample Edge to MOSI Change
SPICLK Shift Edge to MISO Change
Last SPICLK Edge to MISO Change
(CPHA = 1 ONLY)
tSLH
4T
TSYSCLK
TSYSCLK
TSYSCLK
TSYSCLK
TSYSCLK
TSYSCLK
1T
Figure 23–3. SPI Master Transfer Waveform with CPHA=0
1
Clock Cycle
2
3
4
5
6
7
8
SPICLK(CPOL=0)
tCKH
tCKL
SPICLK(CPOL=1)
tMIS
tMIH
MISO
tMOH
MOSI
Figure 23–4. SPI Master Transfer Waveform with CPHA=1
1
Clock Cycle
2
3
4
5
6
7
8
SPICLK(CPOL=0)
tCKH
tCKL
SPICLK(CPOL=1)
tMIS
tMIH
MISO
tMOH
MOSI
MEGAWIN
MPC82x52 Data Sheet
135
Figure 23–5. SPI Slave Transfer Waveform with CPHA=0
1
Clock Cycle
2
3
4
5
6
7
8
tSE
SPICLK(CPOL=0)
tCKH
tCKL
tSD
SPICLK(CPOL=1)
tSIS
tSIH
MOSI
MISO
tSEZ
tSOH
tSDZ
nSS
Figure 23–6. SPI Slave Transfer Waveform with CPHA=1
1
Clock Cycle
2
3
4
5
6
7
8
tSE
SPICLK(CPOL=0)
tCKL
tCKH
tSD
SPICLK(CPOL=1)
tSIS
tSIH
MOSI
tSOH
tSLH
MISO
tSEZ
tSDZ
nSS
136
MPC82x52 Data Sheet
MEGAWIN
24. Instruction Set
Table 24–1. Instruction Set
DESCRIPTION
BYTE
EXECUTION
Cycles
MOV A,Rn
Move register to Acc
MOV A,direct
Move direct byte o Acc
MOV A,@Ri
Move indirect RAM to Acc
MOV A,#data
Move immediate data to Acc
MOV Rn,A
Move Acc to register
MOV Rn,direct
Move direct byte to register
MOV Rn,#data
Move immediate data to register
MOV direct,A
Move Acc to direct byte
MOV direct,Rn
Move register to direct byte
MOV direct,direct
Move direct byte to direct byte
MOV direct,@Ri
Move indirect RAM to direct byte
MOV direct,#data
Move immediate data to direct byte
MOV @Ri,A
Move Acc to indirect RAM
MOV @Ri,direct
Move direct byte to indirect RAM
MOV @Ri,#data
Move immediate data to indirect RAM
MOV DPTR,#data16
Load DPTR with a 16-bit constant
MOVC A,@A+DPTR
Move code byte relative to DPTR to Acc
MOVC A,@A+PC
Move code byte relative to PC to Acc
MOVX A,@Ri
Move on-chip auxiliary RAM(8-bit address) to Acc
MOVX A,@DPTR
Move on-chip auxiliary RAM(16-bit address) to Acc
MOVX @Ri,A
Move Acc to on-chip auxiliary RAM(8-bit address)
MOVX @DPTR,A
Move Acc to on-chip auxiliary RAM(16-bit address)
MOVX A,@Ri
Move external RAM(8-bit address) to Acc
MOVX A,@DPTR
Move external RAM(16-bit address) to Acc
MOVX @Ri,A
Move Acc to external RAM(8-bit address)
MOVX @DPTR,A
Move Acc to external RAM(16-bit address)
PUSH direct
Push direct byte onto Stack
POP direct
Pop direct byte from Stack
XCH A,Rn
Exchange register with Acc
XCH A,direct
Exchange direct byte with Acc
XCH A,@Ri
Exchange indirect RAM with Acc
XCHD A,@Ri
Exchange low-order digit indirect RAM with Acc
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
2
4
2
3
3
4
4
3
3
3
3
3
4
4
3
3
4
3
Not Support
Not Support
Not Support
Not Support
4
3
3
4
4
4
1
2
1
2
1
2
1
2
1
2
1
2
3
3
2
2
3
3
2
2
3
3
MNEMONIC
DATA TRASFER
ARITHEMATIC OPERATIONS
ADD A,Rn
Add register to Acc
ADD A,direct
Add direct byte to Acc
ADD A,@Ri
Add indirect RAM to Acc
ADD A,#data
Add immediate data to Acc
ADDC A,Rn
Add register to Acc with Carry
ADDC A,direct
Add direct byte to Acc with Carry
ADDC A,@Ri
Add indirect RAM to Acc with Carry
ADDC A,#data
Add immediate data to Acc with Carry
SUBB A,Rn
Subtract register from Acc with borrow
SUBB A,direct
Subtract direct byte from Acc with borrow
SUBB A,@Ri
Subtract indirect RAM from Acc with borrow
MEGAWIN
MPC82x52 Data Sheet
137
SUBB A,#data
Subtract immediate data from Acc with borrow
INC A
Increment Acc
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment indirect RAM
DEC A
Decrement Acc
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement indirect RAM
INC DPTR
Increment DPTR
MUL AB
Multiply A and B
DIV AB
Divide A by B
DA A
Decimal Adjust Acc
2
1
1
2
1
1
1
2
1
1
1
1
1
2
2
3
4
4
2
3
4
4
1
4
5
4
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
3
3
2
4
4
2
3
3
2
4
4
2
3
3
2
4
4
1
2
1
1
1
1
1
1
2
1
2
1
2
2
2
2
2
1
4
1
4
1
4
3
3
3
3
LOGIC OPERATION
ANL A,Rn
AND register to Acc
ANL A,direct
AND direct byte to Acc
ANL A,@Ri
AND indirect RAM to Acc
ANL A,#data
AND immediate data to Acc
ANL direct,A
AND Acc to direct byte
ANL direct,#data
AND immediate data to direct byte
ORL A,Rn
OR register to Acc
ORL A,direct
OR direct byte to Acc
ORL A,@Ri
OR indirect RAM to Acc
ORL A,#data
OR immediate data to Acc
ORL direct,A
OR Acc to direct byte
ORL direct,#data
OR immediate data to direct byte
XRL A,Rn
Exclusive-OR register to Acc
XRL A,direct
Exclusive-OR direct byte to Acc
XRL A,@Ri
Exclusive-OR indirect RAM to Acc
XRL A,#data
Exclusive-OR immediate data to Acc
XRL direct,A
Exclusive-OR Acc to direct byte
XRL direct,#data
Exclusive-OR immediate data to direct byte
CLR A
Clear Acc
CPL A
Complement Acc
RL A
Rotate Acc Left
RLC A
Rotate Acc Left through the Carry
RR A
Rotate Acc Right
RRC A
Rotate Acc Right through the Carry
SWAP A
Swap nibbles within the Acc
BOOLEAN VARIABLE MANIPULATION
CLR C
Clear Carry
CLR bit
Clear direct bit
SETB C
Set Carry
SETB bit
Set direct bit
CPL C
Complement Carry
CPL bit
Complement direct bit
ANL C,bit
AND direct bit to Carry
ANL C,/bit
AND complement of direct bit to Carry
ORL C,bit
OR direct bit to Carry
ORL C,/bit
OR complement of direct bit to Carry
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2
2
3
4
2
2
3
3
3
3
3
4
4
5
2
Long subroutine call
3
Return from subroutine
1
Return from interrupt subroutine
1
Absolute jump
2
Long jump
3
Short jump
2
Jump indirect relative to DPTR
1
Jump if Acc is zero
2
Jump if Acc not zero
2
Compare direct byte to Acc and jump if not equal
3
Compare immediate data to Acc and jump if not equal
3
Compare immediate data to register and jump if not equal
3
Compare immediate data to indirect RAM and jump if not equal 3
Decrement register and jump if not equal
2
Decrement direct byte and jump if not equal
3
No Operation
1
6
6
4
4
3
4
3
3
3
3
5
4
4
5
4
5
1
MOV C,bit
Move direct bit to Carry
MOV bit,C
Move Carry to direct bit
BOOLEAN VARIABLE MANIPULATION
JC rel
Jump if Carry is set
JNC rel
Jump if Carry not set
JB bit,rel
Jump if direct bit is set
JNB bit,rel
Jump if direct bit not set
JBC bit,rel
Jump if direct bit is set and then clear bit
PROAGRAM BRACHING
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
MEGAWIN
Absolute subroutine call
MPC82x52 Data Sheet
139
25. Package Dimension
25.1. DIP-20
Figure 25–1. DIP-20
140
MPC82x52 Data Sheet
MEGAWIN
25.2. SOP-20
Figure 25–2. SOP-20
MEGAWIN
MPC82x52 Data Sheet
141
25.3. TSSOP-20
Figure 25–3. TSSOP-20
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MEGAWIN
26. Revision History
Table 26–1. Revision History
Rev
Descriptions
Date
A1
1. Initial issue.
2005/09
A2
1. Pin description for MISO/SCLK.
2. Operation Temperature.
3. Correct CCAPPn to CAPPn.
4. Correct SFR PWMMSBn to PCAPWMn.
5. Correct PWM diagram.
2006/01
2006/01
2006/01
2006/01
2006/01
A3
1. Revises possible operating temperature.
2006/08
A4
1. Add special note on low voltage detector.
2006/12
A5
1. Modify the storage temperature.
2007/03
A6
1. Operation frequency range up to 24 MHz.
2007/11
A7
1. Add 2.7V requirement in flash write operation.
2. Modify Absolute Maximum Rating.
2007/12
A8
1. Format modification.
2008/12
A9
1. Format modification.
2. Add sample code.
3. Operation frequency range up to 25 MHz.
3. Add description for SMOD0.
2012/11
2012/11
2012/11
2012/11
MEGAWIN
MPC82x52 Data Sheet
143
Disclaimers
Herein, Megawin stands for ―Megawin Technology Co., Ltd.‖
Life Support — This product is not designed for use in medical, life-saving or life-sustaining applications, or
systems where malfunction of this product can reasonably be expected to result in personal injury. Customers
using or selling this product for use in such applications do so at their own risk and agree to fully indemnify
Megawin for any damages resulting from such improper use or sale.
Right to Make Changes — Megawin reserves the right to make changes in the products - including circuits,
standard cells, and/or software - described or contained herein in order to improve design and/or performance.
When the product is in mass production, relevant changes will be communicated via an Engineering Change
Notification (ECN).
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