TI BQ4015MS-70 512kx8 nonvolatile sram Datasheet

bq4015/Y
512Kx8 Nonvolatile SRAM
Features
➤ Data retention for at least 10
years without power
-
Snap-on power-source for
lithium battery backup
is unconditionally write-protected to
prevent an inadvertent write operation.
-
Replaceable power-source
(part number: bq40MS)
At this time the integral energy
source is switched on to sustain the
memory until after V CC returns
valid.
➤ Automatic write-protection during
power-up/power-down cycles
➤ Conventional SRAM operation,
including unlimited write cycles
➤ Internal isolation of battery before power application
➤ Industry standard 32-pin DIP
pinout
➤ 34-pin LIFETIME LITHIUM™
module
-
Module completely
surface-mounted
General Description
The CMOS bq4015/Y is a nonvolatile 4,194,304-bit static RAM organized as 524,288 words by 8 bits. The
integral control circuitry and lithium energy source provide reliable
nonvolatility coupled with the unlimited write cycles of standard
SRAM.
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When
VCC falls out of tolerance, the SRAM
Pin Connections
The bq4015/Y uses extremely low
standby current CMOS SRAMs, coupled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The bq4015/Y requires no external
circuitry and is compatible with the
industry-standard 4Mb SRAM pinout.
Pin Names
A0–A18
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Address inputs
DQ0–DQ7 Data input/output
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
NC
A15
A16
NC
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin LIFETIME LITHIUM Module
PN4015Yncm.eps
CE
Chip enable input
OE
Output enable input
WE
Write enable input
NC
No connect
VCC
Supply voltage input
VSS
Ground
32-Pin DIP Module
PN401501.eps
Selection Guide
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
bq4015x -70
70
-5%
bq4015x -85
85
-5%
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
bq4015Yx -70
70
-10%
bq4015Yx -85
85
-10%
Part
Number
Note: x = MA for PDIP or MS for LIFETIME LITHIUM module.
5/99 E
1
bq4015/Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4015/Y operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4015/Y acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4015 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4015Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
The internal coin cells used by the bq4015/Y have an extremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from Unitrode, the integral lithium cells of
the MT-type module are electrically isolated from the
memory. (Self-discharge in this condition is approximately 0.5% per year.) Following the first application of
VCC, this isolation is broken, and the lithium backup
provides data retention on subsequent power-downs.
The LIFETIME LITHIUM package option is shipped as
two parts.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs become high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
Block Diagram
OE
WE
Power
CE
A0–A18
1024K x 8
SRAM
Block
DQ0–DQ7
CECON
Power-Fail
Control
VCC
Lithium
Cell
BD4015.eps
2
bq4015/Y
Truth Table
Mode
CE
WE
OE
I/O Operation
Power
Not selected
H
X
X
High Z
Standby
Output disable
L
H
H
High Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
Operating temperature
TSTG
Storage temperature
TBIAS
Temperature under bias
TSOLDER
Soldering temperature
Note:
0 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-40 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-10 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
+260
°C
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
3
bq4015/Y
Recommended DC Operating Conditions (TA = TOPR)
Symbol
VCC
Parameter
Minimum
Typical
Maximum
Unit
4.5
5.0
5.5
V
bq4015Y
4.75
5.0
5.5
V
bq4015
Supply voltage
VSS
Supply voltage
0
0
0
V
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (TA = TOPR, VCCmin
Symbol
Notes
Parameter
≤ VCC ≤ VCCmax)
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
CE = VIH or OE = VIH or
WE = VIL
VOH
Output high voltage
2.4
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
ISB1
Standby supply current
-
3
5
mA
CE = VIH
ISB2
Standby supply current
-
0.1
1
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA,
A17 < VIL or A17 > VIH,
A18 < VIL or A18 > VIH
ICC
Operating supply current
VPFD
Power-fail-detect voltage
VSO
Supply switch-over voltage
Note:
IOL = 2.1 mA
-
-
90
mA
4.55
4.62
4.75
V
bq4015
4.30
4.37
4.50
V
bq4015Y
-
3
-
V
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
CI/O
CIN
Note:
Parameter
Input/output capacitance
Input capacitance
Minimum
-
Typical
-
These parameters are sampled and not 100% tested.
4
Maximum
8
10
Unit
pF
pF
Conditions
Output voltage = 0V
Input voltage = 0V
bq4015/Y
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Read Cycle
Figure 2. Output Load B
(TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
-70
Symbol
Parameter
-85/-85N
-120/-120N
Min.
Max.
Min.
Max.
Min.
Max.
Unit
70
-
85
-
120
-
ns
Conditions
tRC
Read cycle time
tAA
Address access time
-
70
-
85
-
120
ns
Output load A
tACE
Chip enable access time
-
70
-
85
-
120
ns
Output load A
tOE
Output enable to output valid
-
35
-
45
-
60
ns
Output load A
tCLZ
Chip enable to output in low Z
5
-
5
-
5
-
ns
Output load B
tOLZ
Output enable to output in low Z
5
-
0
-
0
-
ns
Output load B
tCHZ
Chip disable to output in high Z
0
25
0
35
0
45
ns
Output load B
tOHZ
Output disable to output in high Z
0
25
0
25
0
35
ns
Output load B
tOH
Output hold from address change
10
-
10
-
10
-
ns
Output load A
5
bq4015/Y
Read Cycle No. 1 (Address Access) 1, 2
Read Cycle No. 2 (CE Access) 1, 2, 3
Read Cycle No. 3 (OE Access) 1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
6
bq4015/Y
Write Cycle
(TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
-70
Symbol
Parameter
-85/-85N
Min.
Max.
Min.
-120/-120N
Max. Min. Max. Units
Conditions/Notes
tWC
Write cycle time
70
-
85
-
120
-
ns
tCW
Chip enable to end of write
65
-
75
-
100
-
ns
(1)
tAW
Address valid to end of write
65
-
75
-
100
-
ns
(1)
tAS
Address setup time
0
-
0
-
0
-
ns
Measured from address
valid to beginning of
write. (2)
tWP
Write pulse width
55
-
65
-
85
-
ns
Measured from beginning of write to end of
write. (1)
tWR1
Write recovery time
(write cycle 1)
5
-
5
-
5
-
ns
Measured from WE going high to end of write
cycle. (3)
tWR2
Write recovery time
(write cycle 2)
15
-
15
-
15
-
ns
Measured from CE going
high to end of write cycle. (3)
tDW
Data valid to end of write
30
-
35
-
45
-
ns
Measured to first lowto-high transition of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
0
-
0
-
ns
Measured from WE going high to end of write
cycle. (4)
tDH2
Data hold time
(write cycle 2)
10
-
10
-
10
-
ns
Measured from CE going
high to end of write cycle. (4)
tWZ
Write enabled to output in
high Z
0
25
0
30
0
40
ns
I/O pins are in output
state. (5)
tOW
Output active from end of
write
5
-
0
-
0
-
ns
I/O pins are in output
state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
7
bq4015/Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
8
bq4015/Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tPF
VCC slew, 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew, 4.25 to VSO
10
-
-
µs
tPU
VCC slew, VSO to VPFD (max.)
0
-
-
µs
Conditions
t
Chip enable recovery time
40
80
120
ms
Time during which
SRAM is write-protected
after VCC passes VPFD on
power-up.
tDR
Data-retention time in
absence of VCC
10
-
-
years
TA = 25°C. (2)
150
µs
CER
tWPT
Notes:
Write-protect time
40
100
Delay after VCC slews
down past VPFD before
SRAM is writeprotected.
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9
bq4015/Y
MA: 32-Pin A-Type Module
32-Pin MA (A-Type Module)
Dimension
Minimum
A
0.365
A1
0.015
B
0.017
C
0.008
D
1.670
E
0.710
e
0.590
G
0.090
L
0.120
S
0.075
All dimensions are in inches.
Maximum
0.375
0.023
0.013
1.700
0.740
0.630
0.110
0.150
0.110
MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module
34-Pin LCR LIFETIME LITHIUM Module
Dimension
Minimum
A
0.920
B
0.980
C
D
0.052
E
0.045
F
0.015
G
0.020
H
J
0.053
All dimensions are in inches.
10
Maximum
0.930
0.995
0.080
0.060
0.055
0.025
0.030
0.090
0.073
1
Centerline of lead within ±0.005 of true position.
2
Leads coplanar within ±0.004 at seating plane.
3
Components and location may vary.
bq4015/Y
MS: LIFETIME LITHIUM Module Housing
LIFETIME LITHIUM Module Housing
Dimension
Minimum
A
0.845
B
0.955
C
0.210
D
0.065
E
0.065
All dimensions are in inches.
1
Maximum
0.855
0.965
0.220
0.075
0.075
Edges coplanar within ±0.025.
MS: LIFETIME LITHIUM Module with LCR attached
LIFETIME LITHIUM Module
Dimension
Minimum
A
0.955
B
0.980
C
0.240
D
0.052
E
0.045
F
0.015
All dimensions are in inches.
11
Maximum
0.965
0.995
0.250
0.060
0.055
0.025
1
Leads coplanar within ±0.004 at seating plane.
2
Components and location may vary.
bq4015/Y
Data Sheet Revision History
Change No.
Page No.
1
3
2
1, 2, 3, 4, 7, 8, 10
3
2, 10
4
1, 3, 10
5
1, 10
Notes:
Description
Nature of Change
ICC test conditions
Clarification
bq4015MA part
Addition
Added industrial temperature
range
Addition
Removed MB package selection
Deletion
Added MS package
Addition
Change 1 = Sept. 1992 B changes from Sept. 1990 A.
Change 2 = Nov. 1993 C changes from Sept. 1992 B.
Change 3 = June 1995 C changes from Nov. 1993 C.
Change 4 = Nov. 1997 D changes from June 1995 C.
Change 5 = May 1999 E changes from Nov. 1997 D.
Ordering Information
bq4015
xx Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)1
Speed Options:
70 = 70 ns
85 = 85 ns
120 = 120 ns
Package Option:
MA = A-type Module
MS = LIFETIME LITHIUM LCR34 (preliminary package option)2
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4013 128K x 8 NVSRAM
Notes:
1. Only 10% supply (“Y-MA”) version is available in industrial
temperature range; contact factory for speed grade availability.
2. The LIFETIME LITHIUM module is ordered seperately under
part number bq40MS.
12
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ4015MA-70
ACTIVE
DIP MOD
ULE
MA
32
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4015MA-85
ACTIVE
DIP MOD
ULE
MA
32
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4015YMA-70
ACTIVE
DIP MOD
ULE
MA
32
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4015YMA-85
ACTIVE
DIP MOD
ULE
MA
32
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI061 – MAY 2001
MA (R-PDIP-T**)
PLASTIC DUAL-IN-LINE
28 PINS SHOWN
Millimeters
Inches
D
Dimension
Min.
Max.
Min.
Max.
A
0.365
0.375
9.27
A1
0.015
–
0.38
9.53
–
B
0.017
0.023
0.43
0.58
C
0.008
0.013
0.20
0.33
D/12 PIN
0.710
0.740
18.03
18.80
D/28 PIN
1.470
1.500
37.34
38.10
D/32 PIN
1.670
1.700
42.42
43.18
D/40 PIN
2.070
2.100
52.58
53.34
E
0.710
0.740
18.03
18.80
e
G
0.590
0.630
14.99
16.00
0.090
0.110
2.29
2.79
L
0.120
0.150
3.05
3.81
S/12 PIN
0.105
0.130
2.67
3.30
S
0.075
0.110
1.91
2.79
E
A
L
A1
C
B
e
S
G
4201975/A 03/01
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
•
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•
1
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