LT3082 200mA Single Resistor Low Dropout Linear Regulator FEATURES n n n n n n n n n n n n n n DESCRIPTION Outputs May Be Paralleled for Higher Output Current or Heat Spreading Maximum Output Current: 200mA Wide Input Voltage Range: 1.2V to 40V Output Adjustable to 0V Stable with Minimum 2.2μF Ceramic Capacitors Single Resistor Sets Output Voltage Initial Set Pin Current Accuracy: 1% Low Output Noise: 33μVRMS (10Hz to 100kHz) Reverse-Battery Protection Reverse-Current Protection <1mV Load Regulation Typical <0.001%/V Line Regulation Typical Current Limit and Thermal Shutdown Protection Available in 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages APPLICATIONS n n n n n The LT®3082 is a 200mA low dropout linear regulator that can be paralleled to increase output current or spread heat in surface mounted boards. Architected as a precision current source and voltage follower, this regulator benefits many applications requiring high current, adjustability to zero and no heat sink. The LT3082 withstands reverse input voltages and reverse output-to-input voltages without reverse-current flow. A key feature of the LT3082 is the capability to supply a wide output voltage range. A precision “0” TC 10μA reference current source drives a single resistor to program the output voltage to any level between zero and 38.5V. The LT3082 is stable with only 2.2μF of capacitance on the output; the IC uses small ceramic capacitors that do not require additional ESR as is common with other regulators. Internal protection circuitry includes reverse-battery and reverse-current protection, current limiting and thermal limiting. The LT3082 is offered in the thermally enhanced 8-lead TSOT-23, 3-lead SOT-223 and 8-lead 3mm × 3mm DFN packages. All-Surface Mount Power Supply Post Regulator for Switching Supplies Low Parts Count Variable Voltage Supply Low Output Voltage Supply Battery Powered Regulator L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION SET Pin Current vs Temperature Variable Output Voltage Battery Powered Supply SET PIN CURRENT (μA) 1μF 10.075 LT3082 IN 9V 10μA + – SET OUT VOUT = 10μA • RSET CSET 0.1μF RSET 500k 10.100 COUT 2.2μF 10.050 10.025 10.000 9.975 9.950 9.925 9.900 –50 –25 3082 TA01a 0 25 50 75 100 125 150 TEMPERATURE (°C) 3082 TA01b 3082f 1 LT3082 ABSOLUTE MAXIMUM RATINGS (Note 1) All Voltages Relative to VOUT IN Pin Voltage Relative to SET, OUT ........................±40V SET Pin Current (Note 6) .....................................±15mA SET Pin Voltage (Relative to OUT, Note 6) ...............±10V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature Range (Notes 2, 8) E, I Grades ......................................... –40°C to 125°C MP Grade........................................... –55°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (ST, TS8 Packages Only) Soldering, 10 sec .............................................. 300°C PIN CONFIGURATION TOP VIEW OUT 1 OUT 2 NC 3 SET 4 TOP VIEW 3 8 IN 9 7 IN TAB IS OUT IN 2 OUT 1 SET TOP VIEW NC 1 OUT 2 OUT 3 OUT 4 6 NC 5 NC ST PACKAGE 3-LEAD PLASTIC SOT-223 DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 24°C/W, θJC = 15°C/W TAB IS OUT, MUST BE SOLDERED TO OUT ON THE PCB; SEE THE APPLICATIONS INFORMATION SECTION TJMAX = 125°C, θJA = 28°C/W, θJC = 3°C/W EXPOSED PAD (PIN 9) IS OUT, MUST BE SOLDERED TO OUT ON THE PCB; SEE THE APPLICATIONS INFORMATION SECTION 8 IN 7 IN 6 NC 5 SET TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 125°C, θJA = 57°C/W, θJC = 15°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3082EDD#PBF LT3082EDD#TRPBF LDYT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3082IDD#PBF LT3082IDD#TRPBF LDYT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3082EST#PBF LT3082EST#TRPBF 3082 3-Lead Plastic SOT-223 –40°C to 125°C LT3082IST#PBF LT3082IST#TRPBF 3082 3-Lead Plastic SOT-223 –40°C to 125°C LT3082MPST#PBF LT3082MPST#TRPBF 3082MP 3-Lead Plastic SOT-223 –55°C to 125°C LT3082ETS8#PBF LT3082ETS8#TRPBF LTDYV 8-Lead Plastic SOT-23 –40°C to 125°C LT3082ITS8#PBF LT3082ITS8#TRPBF LTDYV 8-Lead Plastic SOT-23 –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3082EDD LT3082EDD#TR LDYT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3082IDD LT3082IDD#TR LDYT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3082EST LT3082EST#TR 3082 3-Lead Plastic SOT-223 –40°C to 125°C LT3082IST LT3082IST#TR 3082 3-Lead Plastic SOT-223 –40°C to 125°C LT3082MPST LT3082MPST#TR 3082MP 3-Lead Plastic SOT-223 –55°C to 125°C LT3082ETS8 LT3082ETS8#TR LTDYV 8-Lead Plastic SOT-23 –40°C to 125°C LT3082ITS8 LT3082ITS8#TR LTDYV 8-Lead Plastic SOT-23 –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3082f 2 LT3082 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. (Note 2) PARAMETER SET Pin Current CONDITIONS MIN TYP MAX UNITS 10 10 10.10 10.20 μA μA 2 4 mV mV –0.1 –0.5 –2 nA mV 0.03 0.003 0.2 0.010 ISET VIN = 2V, ILOAD = 1mA 2V ≤ VIN ≤ 40V, 1mA ≤ ILOAD ≤ 200mA l 9.90 9.80 Offset Voltage (VOUT – VSET) VOS VIN = 2V, ILOAD = 1mA VIN = 2V, ILOAD = 1mA l –2 –4 Load Regulation (Note 7) ΔISET ΔVOS ΔILOAD = 1mA to 200mA ΔILOAD = 1mA to 200mA l ΔISET ΔVOS ΔVIN = 2V to 40V, ILOAD = 1mA ΔVIN = 2V to 40V, ILOAD = 1mA Line Regulation nA/V mV/V Minimum Load Current (Note 3) 2V ≤ VIN ≤ 40V l 300 500 μA Dropout Voltage (Note 4) ILOAD = 10mA ILOAD = 200mA l l 1.22 1.3 1.45 1.65 V V Current Limit VIN = 5V, VSET = 0V, VOUT = –0.1V l Error Amplifier RMS Output Noise (Note 5) 300 mA ILOAD = 200mA, 10Hz ≤ f ≤ 100kHz, COUT = 10μF, CSET = 0.1μF 33 μVRMS Reference Current RMS Output Noise (Note 5) 10Hz ≤ f ≤ 100kHz 0.7 nARMS Ripple Rejection f = 120Hz, VRIPPLE = 0.5VP-P, ILOAD = 0.1A, COUT = 2.2μF, CSET = 0.1μF f = 10kHz f = 1MHz 90 dB 75 20 dB dB Thermal Regulation ISET 10ms Pulse Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Unless otherwise specified, all voltages are with respect to VOUT. The LT3082E is tested and specified under pulse load conditions such that TJ ≅ TA. The LT3082E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization, and correlation with statistical process controls. The LT3082I is guaranteed to meet all data sheet specifications over the full –40°C to 125°C operating junction temperature range. The LT3082MP is 100% tested and guaranteed over the –55°C to 125°C operating junction temperature range. Note 3: Minimum load current is equivalent to the quiescent current of the part. Since all quiescent and drive current is delivered to the output of the part, the minimum load current is the minimum current required to maintain regulation. 200 0.003 %/W Note 4: For the LT3082, dropout is specified as the minimum input-tooutput voltage differential required supplying a given output current. Note 5: Adding a small capacitor across the reference current resistor lowers output noise. Adding this capacitor bypasses the resistor shot noise and reference current noise; output noise is then equal to error amplifier noise (see the Applications Information section). Note 6: Diodes with series 1k resistors clamp the SET pin to the OUT pin. These diodes and resistors only carry current under transient overloads. Note 7: Load regulation is Kelvin-sensed at the package. Note 8: This IC includes overtemperature protection that protects the device during momentary overload conditions. Junction temperature exceeds the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3082f 3 LT3082 TYPICAL PERFORMANCE CHARACTERISTICS SET Pin Current 2.0 N = 1326 10.075 1.5 10.050 1.0 OFFSET VOLTAGE (mV) SET PIN CURRENT (μA) Offset Voltage (VOUT – VSET) SET Pin Current Distribution 10.100 10.025 10.000 9.975 9.950 9.925 0.5 0 –0.5 –1.0 –1.5 9.900 –50 –25 0 9.80 25 50 75 100 125 150 TEMPERATURE (°C) 3082 G01 –2.0 –50 –25 10 10.20 9.90 10.10 SET PIN CURRENT DISTRIBUTION (μA) 0 25 50 75 100 125 150 TEMPERATURE (°C) 3082 G03 3082 G02 Offset Voltage Offset Voltage Distribution 1.00 N = 1326 Offset Voltage 100 ILOAD = 1mA 50 –2 0 –1 1 VOS DISTRIBUTION (mV) 2 0 0.50 OFFSET VOLTAGE (μV) OFFSET VOLTAGE (mV) 0.75 0.25 0 –0.25 –0.50 –50 –100 –150 –200 –250 –300 –0.75 –350 –1.00 –400 0 5 10 15 20 25 30 35 INPUT-TO-OUTPUT VOLTAGE (V) 0 40 3082 G05 50 150 100 LOAD CURRENT (mA) 200 3082 G06 3082 G04 ΔILOAD = 1mA TO 200mA VIN – VOUT = 3V 10 0 –50 0 CHANGE IN REFERENCE CURRENT –10 –100 –20 –150 –30 –200 –40 –250 (VOUT – VSET) –50 CHANGE IN OFFSET VOLTAGE –300 –60 –350 –70 –400 –50 –25 0 –80 25 50 75 100 125 150 TEMPERATURE (°C) Minimum Load Current 600 MINIMUM LOAD CURRENT (μA) CHANGE IN OFFSET VOLTAGE WITH LOAD (μV) 50 20 CHANGE IN REFERENCE CURRENT WITH LOAD (nA) Load Regulation 100 500 400 300 200 100 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3082 G08 3082 G07 3082f 4 LT3082 TYPICAL PERFORMANCE CHARACTERISTICS Dropout Voltage Dropout Voltage TJ = –55°C 1.2 TJ = 25°C 1.0 TJ = 125°C 0.8 0.6 0.4 0.2 0 50 75 100 125 150 175 200 LOAD CURRENT (mA) 1.2 ILOAD = 200mA 1.0 ILOAD = 100mA 0.8 0.6 0.4 0.2 350 300 250 200 150 100 50 0 –50 –25 TJ = 25°C 0 25 50 75 100 125 150 0 TEMPERATURE (°C) 3082 G10 0 2 6 8 10 4 INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V) 3082 G11 3082 G09 Current Limit Load Transient Response 450 400 350 300 250 200 150 100 200 150 100 50 0 –50 –100 50 0 –50 –25 0 250 –150 VIN = 7V VOUT = 0V 0 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA) OUTPUT VOLTAGE DEVIATION (mV) 500 TIME (μs) VOUT = 1V CSET = 0.1μF CIN = 1μF CERAMIC ΔILOAD = 10mA to 200mA COUT = 2.2μF CERAMIC 25 50 75 100 125 150 TEMPERATURE (°C) 3082 G12 3082 G13 Line Transient Response Turn-On Response OUTPUT VOLTAGE (V) 25 CURRENT LIMIT (mA) 0 400 CURRENT LIMIT (mA) DROPOUT VOLTAGE (VIN – VOUT) (V) 1.4 OUTPUT VOLTAGE DEVIATION (mV) DROPOUT VOLTAGE (VIN – VOUT) (V) Current Limit 1.4 1.6 60 40 20 0 –20 4 2 0 0 50 100 150 200 250 300 350 400 450 500 TIME (μs) VOUT = 1V CSET = 0.1μF CIN = 1μF CERAMIC ILOAD = 10mA COUT = 2.2μF CERAMIC 1.0 0.5 0 4 2 0 0 INPUT VOLTAGE (V) 6 1.5 INPUT VOLTAGE (V) –40 2.0 10 20 30 40 50 60 70 80 90 100 TIME (μs) COUT = 2.2μF CERAMIC CSET = 0 RSET = 100k RLOAD = 5Ω 3082 G14 3082f 5 LT3082 TYPICAL PERFORMANCE CHARACTERISTICS Residual Output for Less Than Minimum Load Current Ripple Rejection 800 SET PIN = 0V 89 VOUT 600 100 VIN = 36V RTEST 500 VIN = 5V 400 300 200 80 60 CSET = 0.1μF 40 20 100 0 0 0 1000 RTEST (Ω) 2000 88 RIPPLE REJECTION (dB) VIN RIPPLE REJECTION (dB) 700 OUTPUT VOLTAGE (mV) Ripple Rejection (120Hz) 90 120 VIN = VOUT(NOMINAL) + 3V RIPPLE = 500mVP-P ILOAD = 200mA COUT = 2.2μF 10 100 3082 G16 CSET = 0 1k 10k 100k FREQUENCY (Hz) 87 86 85 84 83 82 81 1M 10M VIN = VOUT(NOMINAL) + 2V RIPPLE = 500mVP-P, f = 120Hz ILOAD = 0.2A CSET = 0, COUT = 2.2μF 80 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3082 G18 3082 G17 NOISE SPECTRAL DENSITY (nV/√Hz) 1k 1k 100 100 10 10 1.0 1 10 100 1k 10k FREQUENCY (Hz) 0.1 100k REFERENCE CURRENT NOISE SPECTRAL DENSITY (pA /√Hz) Noise Spectral Density 10k Output Voltage Noise VBAT = 3.6V ICPO = 200μA CCPO = 2.2ΩF VOUT 100μV/DIV TIME 1ms/DIV 3082 G20 VOUT = 1V COUT = 2.2μF RSET = 100k ILOAD = 200mA CSET = 0.1μF 3082 G19 3082f 6 LT3082 PIN FUNCTIONS (DD/ST/TS8) IN (Pins 7, 8/Pin 3/Pins 7, 8): Input. This pin supplies power to regulate internal circuitry and supply output load current. For the device to operate properly and regulate, the voltage on this pin must be 1.2V to 1.4V above the OUT pin (depending on output load current—see the dropout voltage specifications in the Electrical Characteristics table). NC (Pins 3, 5, 6/NA/Pins 1, 6): No Connection. These pins have no connection to internal circuitry and may be tied to IN, OUT, GND or floated. OUT (Pins 1, 2/Pin 2/Pins 2, 3, 4): Output. This is the power output of the device. The LT3082 requires a 0.5mA minimum load current or the output will not regulate. SET (Pin 4/Pin 1/Pin 5): Set. This pin is the error amplifier’s noninverting input and also sets the operating bias point of the circuit. A fixed 10μA current source flows out of this pin. A single external resistor programs VOUT. Output voltage range is 0V to 38.5V. Exposed Pad/Tab (Pin 9/Tab/NA): Output. The Exposed Pad of the DFN package and the Tab of the SOT-223 package are tied internally to OUT. Tie them directly to OUT pins (Pins 1, 2/Pin 2) at the PCB. The amount of copper area and planes connected to the Exposed Pad/Tab determine the effective thermal resistance of the packages (see the Applications Information section). BLOCK DIAGRAM IN 10μA + – SET OUT 3082 BD 3082f 7 LT3082 APPLICATIONS INFORMATION Introduction The LT3082 regulator is easy to use and has all the protection features expected in high performance regulators. Included are reverse-input, reverse-output and reverse input-to-output protection for sensitive circuitry and loads. Additional protection includes short-circuit protection and thermal shutdown with hysteresis. The LT3082 fits well in applications needing multiple rails. This new architecture adjusts down to zero with a single resistor, handling modern low voltage digital IC’s as well as allowing easy parallel operation and thermal management without heat sinks. Adjusting to zero output allows shutting off the powered circuitry. When the input is preregulated—such as a 5V or 3.3V input supply—external resistors can help spread the heat. A precision “0” TC 10μA reference current source connects to the noninverting input of a power operational amplifier. The power operational amplifier provides a low impedance buffered output to the voltage on the noninverting input. A single resistor from the noninverting input to ground sets the output voltage. If this resistor is set to 0Ω, zero output voltage results. Therefore, any output voltage between zero and the maximum defined by the input power supply voltage is obtainable. The benefit of using a true internal current source as the reference, as opposed to a bootstrapped reference in older regulators, is not so obvious in this architecture. A true Programming Output Voltage The LT3082 generates a 10μA reference current that flows out of the SET pin. Connecting a resistor from SET to GND generates a voltage that becomes the reference point for the error amplifier (see Figure 1). The reference voltage equals 10μA multiplied by the value of the SET pin resistor. Any voltage may be generated and there is no minimum output voltage for the regulator. Table 1 lists many common output voltages and the closest standard 1% resistor values used to generate that output voltage. Regulation of the output voltage requires a minimum load current of 0.5mA. For a true 0V output operation, return this minimum 0.5mA load current to a negative supply voltage. LT3082 IN CIN reference current source allows the regulator to have gain and frequency response independent of the impedance on the positive input. On older adjustable regulators, such as the LT1086, loop gain changes with output voltage and bandwidth changes if the adjustment pin is bypassed to ground. For the LT3082, loop gain is unchanged with output voltage changes or bypassing. Output regulation is not a fixed percentage of output voltage, but is a fixed fraction of millivolts. Use of a true current source allows all of the gain in the buffer amplifier to provide regulation, and none of that gain is needed to amplify up the reference to a higher output voltage. 10μA + – SET OUT VOUT = 10μA • RSET CSET RSET COUT RLOAD 3082 F01 Figure 1. Basic Adjustable Regulator 3082f 8 LT3082 APPLICATIONS INFORMATION Table 1. 1% Resistors for Common Output Voltages VOUT (V) RSET (k) 1 100 1.2 121 1.5 150 1.8 182 2.5 249 3.3 332 5 499 With a 10μA current source generating the reference voltage, leakage paths to or from the SET pin can create errors in the reference and output voltages. High quality insulation should be used (e.g., Teflon, Kel-F). The cleaning of all insulating surfaces to remove fluxes and other residues may be required. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Minimize board leakage by encircling the SET pin and circuitry with a guard ring that is operated at a potential close to itself. Tie the guard ring to the OUT pin. Guarding both sides of the circuit board is required. Bulk leakage reduction depends on the guard ring width. 10nA of leakage into or out of the SET pin and its associated circuitry creates a 0.1% reference voltage error. Leakages of this magnitude, coupled with other sources of leakage, can cause significant offset voltage and reference drift, especially over the possible operating temperature range. Figure 2 depicts an example guard ring layout. If guard ring techniques are used, this bootstraps any stray capacitance at the SET pin. Since the SET pin is a high impedance node, unwanted signals may couple into the SET pin and cause erratic behavior. This will be most noticeable when operating with minimum output capacitors at full load current. The easiest way to remedy this is to bypass the SET pin with a small amount of capacitance from SET to ground; 10pF to 20pF is sufficient. Stability and Output Capacitance The LT3082 requires an output capacitor for stability. It is designed to be stable with most low ESR capacitors (typically ceramic, tantalum or low ESR electrolytic). A minimum output capacitor of 2.2μF with an ESR of 0.5Ω or less is recommended to prevent oscillations. Larger values of output capacitance decrease peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3082, increase the effective output capacitor value. For improvement in transient response performance, place a capacitor across the voltage setting resistor. Capacitors up to 1μF can be used. This bypass capacitor reduces system noise as well, but start-up time is proportional to the time constant of the voltage setting resistor (RSET in Figure 1) and SET pin bypass capacitor. Give extra consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of di- OUT SET GND 3082 F02 Figure 2. Example Guard Ring Layout for DFN Package 3082f 9 LT3082 APPLICATIONS INFORMATION electrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients, as shown in Figures 3 and 4. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors. The X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than with Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Stability and Input Capacitance Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress. In a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. One of two ways reduces a wire’s self-inductance. One method divides the current flowing towards the LT3082 between two parallel conductors. In this case, the farther apart the wires are from each other, the more the self-inductance is reduced; up to a 50% reduction when placed a few inches apart. Splitting the wires basically connects Low ESR, ceramic input bypass capacitors are acceptable for applications without long input leads. However, applications connecting a power supply to an LT3082 circuit’s IN and GND pins with long input wires combined with a low ESR, ceramic input capacitors are prone to voltage spikes, reliability concerns and application-specific board oscillations. The input wire inductance found in many battery powered applications, combined with the low ESR ceramic input capacitor, forms a high-Q LC resonant tank circuit. In some instances this resonant frequency beats against the output current dependent LDO bandwidth and interferes with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of LT3082 instability, but is a common ceramic input bypass capacitor application issue. The self-inductance, or isolated inductance, of a wire is directly proportional to its length. Wire diameter is not a major factor on its self-inductance. For example, the selfinductance of a 2-AWG isolated wire (diameter = 0.26") is about half the self-inductance of a 30-AWG wire (diameter = 0.01"). One foot of 30-AWG wire has about 465nH of self-inductance. 40 20 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 20 X5R CHANGE IN VALUE (%) CHANGE IN VALUE (%) 0 –20 –40 –60 Y5V –80 –100 –20 –40 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16 3082 F03 Figure 3. Ceramic Capacitor DC Bias Characteristics Y5V –60 –80 0 X5R 0 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF –100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3082 F04 Figure 4. Ceramic Capacitor Temperature Characteristics 3082f 10 LT3082 APPLICATIONS INFORMATION two equal inductors in parallel, but placing them in close proximity gives the wires mutual inductance adding to the self-inductance. The second and most effective way to reduce overall inductance is to place both forward and return current conductors (the input and GND wires) in very close proximity. Two 30-AWG wires separated by only 0.02", used as forward- and return-current conductors, reduce the overall self-inductance to approximately one-fifth that of a single isolated wire. Spreading the devices on the PC board also spreads the heat. Series input resistors can further spread the heat if the input-to-output difference is high. LT3082 IN 10μA + – SET If wiring modifications are not permissible for the applications, including series resistance between the power supply and the input of the LT3082 also stabilizes the application. As little as 0.1Ω to 0.5Ω, often less, is effective in damping the LC resonance. If the added impedance between the power supply and the input is unacceptable, adding ESR to the input capacitor also provides the necessary damping of the LC resonance. However, the required ESR is generally higher than the series impedance required. VIN 4.8V TO 40V OUT 50mΩ LT3082 IN 10μA + – 1μF SET OUT 50mΩ 165k VOUT, 3.3V 0.4A 10μF 3082 F05 Paralleling Devices Figure 5. Parallel Devices Higher output current is obtained by paralleling multiple LT3082s together. Tie the individual SET pins together and tie the individual IN pins together. Connect the outputs in common using small pieces of PC trace as ballast resistors to promote equal current sharing. PC trace resistance in mΩ/inch is shown in Table 2. Ballasting requires only a tiny area on the PCB. Table 2. PC Board Trace Resistance WEIGHT (oz) 10mil WIDTH 1 54.3 2 27.1 Trace resistance is measured in mΩ/in 20mil WIDTH 27.1 13.6 The worst-case room temperature offset, only ±2mV between the SET pin and the OUT pin, allows the use of very small ballast resistors. As shown in Figure 5, each LT3082 has a small 50mΩ ballast resistor, which at full output current gives better than 80% equalized sharing of the current. The external resistance of 50mΩ (25mΩ for the two devices in parallel) adds only about 10mV of output regulation drop at an output of 0.4A. Even with an output voltage as low as 1V, this adds only 1% to the regulation. Of course, paralleling more than two LT3082s yields even higher output current. Quieting the Noise The LT3082 offers numerous noise performance advantages. Every linear regulator has its sources of noise. In general, a linear regulator’s critical noise source is the reference. In addition, consider the error amplifier’s noise contribution along with the resistor divider’s noise gain. Many traditional low noise regulators bond out the voltage reference to an external pin (usually through a large value resistor) to allow for bypassing and noise reduction. The LT3082 does not use a traditional voltage reference like other linear regulators. Instead, it uses a 10μA reference current. The 10μA current source generates noise current levels of 2.7pA/√Hz (0.7nARMS over the 10Hz to 100kHz bandwidth). The equivalent voltage noise equals the RMS noise current multiplied by the resistor value. The SET pin resistor generates spot noise equal to √4kTR (k = Boltzmann’s constant, 1.38 • 10–23J/°K, and T is absolute temperature) which is RMS summed with the voltage noise If the application requires lower noise performance, bypass the voltage/current setting resistor with a capacitor to GND. Note that this noise-reduction capacitor increases start-up time as a factor of the RC time constant. 3082f 11 LT3082 APPLICATIONS INFORMATION The LT3082 uses a unity-gain follower from the SET pin to the OUT pin. Therefore, multiple possibilities exist (besides a SET pin resistor) to set output voltage. For example, using a high accuracy voltage reference from SET to GND removes the errors in output voltage due to reference current tolerance and resistor tolerance. Active driving of the SET pin is acceptable. The typical noise scenario for a linear regulator is that the output voltage setting resistor divider gains up the noise reference, especially if VOUT is much greater than VREF. The LT3082’s noise advantage is that the unity-gain follower presents no noise gain whatsoever from the SET pin to the output. Thus, noise figures do not increase accordingly. Error amplifier noise is typical 100nV/√Hz (33μVRMS over the 10Hz to 100kHz bandwidth). The error amplifier’s noise is RMS summed with the other noise terms to give a final noise figure for the regulator. Curves in the Typical Performance Characteristics section show noise spectral density and peak-to-peak noise characteristics for both the reference current and error amplifier over the 10Hz to 100kHz bandwidth. Load Regulation The LT3082 is a floating device. No ground pin exists on the packages. Thus, the IC delivers all quiescent current and drive current to the load. Therefore, it is not possible to provide true remote load sensing. The connection resistance between the regulator and the load determines load regulation performance. The data sheet’s load regulation specification is Kelvin sensed at the package’s pins. Negative-side sensing is a true Kelvin connection by returning the bottom of the voltage setting resistor to the negative side of the load (see Figure 6). Connected as shown, system load regulation is the sum of the LT3082’s load regulation and the parasitic line resistance multiplied by the output current. To minimize load regulation, keep the positive connection between the regulator and load as short as possible. If possible, use large diameter wire or wide PC board traces. LT3082 IN 10μA + – PARASITIC RESISTANCE SET OUT RSET RP RP LOAD 3082 F06 RP Figure 6. Connections for Best Load Regulation Thermal Considerations The LT3082’s internal power and thermal limiting circuitry protects itself under overload conditions. For continuous normal load conditions, do not exceed the 125°C maximum junction temperature. Carefully consider all sources of thermal resistance from junction-to-ambient. This includes (but is not limited to) junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. Consider all additional, adjacent heat generating sources in proximity on the PCB. Surface mount packages provide the necessary heatsinking by using the heat spreading capabilities of the PC board, copper traces and planes. Surface mount heat sinks, plated through-holes and solder-filled vias can also spread the heat generated by power devices. Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly, or the bottom of the pin most directly, in the heat path. This is the lowest thermal resistance path for heat flow. Only proper device mounting ensures the best possible thermal flow from this area of the package to the heat sinking material. Note that the Exposed Pad of the DFN package and the tab of the SOT-223 package is electrically connected to the output (VOUT). 3082f 12 LT3082 APPLICATIONS INFORMATION Tables 3 through 5 list thermal resistance as a function of copper areas in a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1oz solid internal planes and 2oz external trace planes with a total finished board thickness of 1.6mm. Table 3. DD Package, 8-Lead DFN COPPER AREA TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 25°C/W 1000mm2 2500mm2 2500mm2 25°C/W 225mm2 2500mm2 2500mm2 28°C/W 100mm2 2500mm2 2500mm2 32°C/W *Device is mounted on topside Table 4. TS8 Package, 8-Lead SOT-23 COPPER AREA PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. Please reference JEDEC standard JESD51-7 for further information on high thermal conductivity test boards. Achieving low thermal resistance necessitates attention to detail and careful layout. Demo circuit 1447A’s board layout using multiple inner VOUT planes and multiple thermal vias achieves 28°C/W performance for the DFN package. Calculating Junction Temperature Example: Given an industrial factory application with an input voltage of 15V ±10%, an output voltage of 12V ±5%, an output current of 200mA and a maximum ambient temperature of 50°C, what would be the maximum junction temperature for a DFN package? The total circuit power equals: TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 54°C/W 1000mm2 2500mm2 2500mm2 54°C/W 225mm2 2500mm2 2500mm2 57°C/W VIN(MAX CONTINUOUS) = 16.5 (15V + 10%) 100mm2 2500mm2 2500mm2 63°C/W VOUT(MIN CONTINUOUS) = 11.4V (12V – 5%) *Device is mounted on topside PTOTAL = (VIN – VOUT)(IOUT) The SET pin current is negligible and can be ignored. IOUT = 200mA Table 5. ST Package, 3-Lead SOT-223 COPPER AREA Power dissipation under these conditions equals: TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 20°C/W 1000mm2 2500mm2 2500mm2 20°C/W 225mm2 2500mm2 2500mm2 24°C/W 100mm2 2500mm2 2500mm2 29°C/W *Device is mounted on topside For further information on thermal resistance and using thermal information, refer to JEDEC standard JESD51, notably JESD51-12. PTOTAL = (16.5 – 11.4V)(200mA) = 1.02W Junction temperature equals: TJ = TA + PTOTAL • θJA TJ = 50°C + (1.02W • 30°C/W) = 80.6°C In this example, junction temperature is below the maximum rating, ensuring reliable operation. 3082f 13 LT3082 APPLICATIONS INFORMATION Protection Features greater than IN, is less than 1mA (typically under 100μA), protecting the LT3082 and sensitive loads. The LT3082 incorporates several protection features ideal for battery-powered circuits, among other applications. In addition to normal monolithic regulator protection features such as current limiting and thermal limiting, the LT3082 protects itself against reverse-input voltages, reverseoutput voltages, and reverse OUT-to-SET pin voltages. Clamping diodes and 1k limiting resistors protect the LT3082’s SET pin relative to the OUT pin voltage. These protection components typically only carry current under transient overload conditions. These devices are sized to handle ±10V differential voltages and ±15mA crosspin current flow without concern. Relative to these application concerns, note the following two scenarios. The first scenario employs a noise-reducing SET pin bypass capacitor while OUT is instantaneously shorted to GND. The second scenario follows improper shutdown techniques in which the SET pin is reset to GND quickly while OUT is held up by a large output capacitance with light load. The Typical Applications section shows simple, robust techniques for shutting down SET and OUT together. Current limit protection and thermal overload protection protect the IC against output current overload conditions. For normal operation, do not exceed a junction temperature of 125°C. The thermal shutdown circuit’s temperature threshold is typically 165°C and incorporates about 5°C of hysteresis. The LT3082’s IN pin withstands ±40V voltages with respect to the OUT and SET pins. Reverse current flow, if OUT is TYPICAL APPLICATIONS DAC-Controlled Regulator VIN Two-Level Regulator LT3082 IN VIN 10μA SPI LTC2641 150k 450k 150k – + LT3082 IN 10μA + – LT1991 SET + – OUT VOUT SET 4.7μF R2 3082 TA02 GAIN = 4 OUT VOUT 2.2μF 3082 TA03 VN2222LL R1 3082f 14 LT3082 TYPICAL APPLICATIONS Using a Lower Value SET Resistor VIN 12V LT3082 IN 10μA + – C1 1μF VOUT 0.5V TO 10V VOUT = 0.5V + 1mA • RSET OUT SET R1 49.9k 1% 1mA R2 499Ω 1% COUT 4.7μF RSET 10k 3082 TA04 Adding Soft-Start LT3082 IN VIN 4.8V to 40V 10μA + – D1 1N4148 C1 1μF C2 0.01μF VOUT 3.3V 0.2A OUT SET COUT 4.7μF R1 332k 3082 TA05 Coincident Tracking LT3082 IN 10μA IN LT3082 + – 10μA VIN 7V TO 40V LT3082 IN + – 10μA C1 1.5μF + – SET R1 249k R2 80.6k OUT C2 4.7μF R3 169k OUT SET OUT SET C3 4.7μF VOUT3 5V 0.2A C4 4.7μF VOUT2 3.3V 0.2A 3082 TA06 VOUT1 2.5V 0.2A 3082f 15 LT3082 TYPICAL APPLICATIONS Adding Shutdown VIN Reference Buffer LT3082 IN LT3082 IN VIN 10μA 10μA + – + – OUT SET ON OFF Q1 VN2222LL INPUT OUTPUT LT1019 Q2* VN2222LL R1 GND SHUTDOWN OUT SET VOUT C1 1μF 3082 TA07 VOUT* C2 4.7μF * MINIMUM LOAD 0.5mA 3082 TA08 *Q2 INSURES ZERO OUTPUT IN THE ABSENCE OF ANY OUTPUT LOAD. High Voltage Regulator 6.1V 10k VIN 50V 1N4148 LT3082 IN BUZ11 10μA + + – 10μF + RSET 2MEG 15μF VOUT 0.2A OUT SET VOUT = 20V VOUT = 10μA • RSET 4.7μF 3082 TA09 Ramp Generator LT3082 IN VIN 5V 10μA + – 1μF SET VN2222LL 1nF OUT VN2222LL VOUT 4.7μF 3082 TA10 3082f 16 LT3082 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 3.00 ±0.10 (4 SIDES) 0.38 ± 0.10 8 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD) DFN 1203 0.200 REF 0.75 ±0.05 0.00 – 0.05 4 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 3082f 17 LT3082 PACKAGE DESCRIPTION ST Package 3-Lead Plastic SOT-223 (Reference LTC DWG # 05-08-1630) .248 – .264 (6.30 – 6.71) .129 MAX .114 – .124 (2.90 – 3.15) .059 MAX .264 – .287 (6.70 – 7.30) .248 BSC .130 – .146 (3.30 – 3.71) .039 MAX .059 MAX .181 MAX .033 – .041 (0.84 – 1.04) .0905 (2.30) BSC .090 BSC RECOMMENDED SOLDER PAD LAYOUT 10° – 16° .010 – .014 (0.25 – 0.36) 10° MAX .071 (1.80) MAX 10° – 16° .024 – .033 (0.60 – 0.84) .181 (4.60) BSC .012 (0.31) MIN .0008 – .0040 (0.0203 – 0.1016) ST3 (SOT-233) 0502 3082f 18 LT3082 PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0802 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 3082f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT3082 TYPICAL APPLICATIONS Active-Driven Regulator VIN LT3082 IN 10μA + – OUT V1 0V TO 5V SET R1, 100k R2 100k 2.2μF ⎛ R2 ⎞ VOUT = ⎜ • V1 + 10µA • (R1 || R2) ⎝ R1 + R2 ⎟⎠ VOUT 0.5V TO 3V 3082 TA11 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise = 20μVRMS, VIN: 1.8V to 20V, ThinSOT™ Package LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise = 20μVRMS, VIN: 1.8V to 20V, MS-8 Package LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise = 20μVRMS, VIN: 1.8V to 20V, SO-8 Package LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise = 20μVRMS, VIN: 1.8V to 20V, MS-8 Package LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise = 30μVRMS, VIN: –1.8V to –20V, ThinSOT Package LT3008 20mA, 45V, 3μA IQ Micropower LDO 280mV Dropout Voltage, Low IQ = 3μA, VIN: 2V to 45V, VOUT : 0.6V to 39.5V; ThinSOT and 2mm × 2mm DFN-6 Packages LT3009 20mA, 3μA IQ Micropower LDO 280mV Dropout Voltage, Low IQ = 3μA, VIN: 1.6V to 20V, VOUT : 0.6V to 19.5V; ThinSOT and SC-70 Packages LT3010 50mA, High Voltage, Micropower LDO VIN: 3V to 80V, VOUT : 1.275V to 60V, VDO = 0.3V, IQ = 30μA, ISD <1μA, Low Noise <100μVRMS, Stable with 1μF Output Capacitor, Exposed MS8 Package LT3011 50mA, High Voltage, Micropower LDO with Power Good VIN: 3V to 80V, VOUT : 1.275V to 60V, VDO = 0.3V, IQ = 46μA, ISD <1μA, Low Noise <100μVRMS, Power Good, Stable with 1μF Output Capacitor, 3mm × 3mm DFN-10 and Exposed MS-12E Packages LT3012 250mA, 4V to 80V, Low Dropout Micropower Linear Regulator VIN: 4V to 80V, VOUT : 1.24V to 60V, VDO = 0.4V, IQ = 40μA, ISD <1μA, TSSOP-16E and 4mm × 3mm DFN-12 Packages LT3013 250mA, 4V to 80V, Low Dropout Micro-power Linear Regulator with PWRGD VIN: 4V to 80V, VOUT : 1.24V to 60V, VDO = 0.4V, IQ = 65μA, ISD <1μA, Power Good; TSSOP-16E and 4mm × 3mm DFN-12 Packages LT3014/LT3014HV 20mA, 3V to 80V, Low Dropout Micropower Linear Regulator VIN: 3V to 80V (100V for 2ms, HV Version), VOUT : 1.22V to 60V, VDO = 0.35V, IQ = 7μA, ISD <1μA, ThinSOT and 3mm × 3mm DFN-8 Packages LT3020 100mA, Low Voltage VLDO Linear Regulator VIN: 0.9V to 10V, VOUT : 0.2V to 5V (Min), VDO = 0.15V, IQ = 120μA, Noise <250μVRMS, Stable with 2.2μF Ceramic Capacitors, DFN-8 and MS-8 Packages LT3021 500mA, Low Voltage, Very Low Dropout VLDO Linear Regulator VIN: 0.9V to 10V, Dropout Voltage = 160mV (Typical), Adjustable Output (VREF = VOUT(MIN) = 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V, Stable with Low ESR, Ceramic Output Capacitors 16-Pin 5mm × 5mm DFN and 8-Lead SO Packages LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise = 40μVRMS, VIN: 1.2V to 36V, VOUT : 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors; TO-220, SOT-223, MSOP-8 and 3mm × 3mm DFN-8 Packages; LT3080-1 Version Has Integrated Internal Ballast Resistor LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors; MSOP-8 and 2mm × 3mm DFN-6 Packages ThinSOT is a trademark of Linear Technology Corporation. 3082f 20 Linear Technology Corporation LT 0709 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009