AD AD8631 1.8 v, 5 mhz rail-to-rail low power operational amplifier Datasheet

a
FEATURES
Single Supply Operation: 1.8 V to 6 V
Space-Saving SOT-23, ␮SOIC Packaging
Wide Bandwidth: 5 MHz @ 5 V, 4 MHz @ 1.8 V
Low Offset Voltage: 4 mV Max, 0.8 mV typ
Rail-to-Rail Input and Output Swing
2 V/␮s Slew Rate @ 1.8 V
Only 225 ␮A Supply Current @ 1.8 V
APPLICATIONS
Portable Communications
Portable Phones
Sensor Interface
Active Filters
PCMCIA Cards
ASIC Input Drivers
Wearable Computers
Battery-Powered Devices
New Generation Phones
Personal Digital Assistants
1.8 V, 5 MHz Rail-to-Rail
Low Power Operational Amplifiers
AD8631/AD8632
PIN CONFIGURATIONS
5-Lead SOT-23
(RT Suffix)
OUT A 1
5 V+
V– 2
+IN A 3
4 –IN A
8-Lead SOIC
(R Suffix)
OUT A 1
8
V+
–IN A 2
7
OUT B
+IN A 3
AD8632
V– 4
6
–IN B
5
+IN B
8-Lead ␮SOIC
(RM Suffix)
GENERAL DESCRIPTION
The AD8631 brings precision and bandwidth to the SOT-23-5
package at single supply voltages as low as 1.8 V and low supply
current. The small package makes it possible to place the AD8631
next to sensors, reducing external noise pickup.
AD8631
OUT A
–IN A
+IN A
V–
1
8
AD8632
4
5
V+
OUT B
–IN B
+IN B
The AD8631 and AD8632 are rail-to-rail input and output bipolar
amplifiers with a gain bandwidth of 4 MHz and typical voltage
offset of 0.8 mV from a 1.8 V supply. The low supply current and
the low supply voltage makes these parts ideal for battery-powered
applications. The 3 V/µs slew rate makes the AD8631/AD8632 a
good match for driving ASIC inputs, such as voice codecs.
The AD8631/AD8632 is specified over the extended industrial
(–40ⴗC to +125ⴗC) temperature range. The AD8631 single is
available in 5-lead SOT-23 surface-mount packages. The dual
AD8632 is available in 8-lead SOIC and µSOIC packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD8631/AD8632–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 5 V, V– = 0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
VCM
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Output Voltage Swing Low
Short Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
∆VOS/∆T
∆IB/∆T
VOH
VOL
ISC
PSRR
ISY
CM
= 2.5 V, TA = 25ⴗC unless otherwise noted)
Conditions
Min
Typ
Max
Unit
0.8
4.0
6
250
500
± 150
550
5
mV
mV
nA
nA
nA
nA
V
dB
dB
V/mV
V/mV
V/mV
µV/ⴗC
pA/ⴗC
–40ⴗC ≤ TA ≤ +125ⴗC
–40ⴗC ≤ TA ≤ +125ⴗC
–40ⴗC ≤ TA ≤ +125ⴗC
0 V ≤ VCM ≤ 5 V,
–40ⴗC ≤ TA ≤ +125ⴗC
RL = 10 kΩ, 0.5 V < VOUT < 4.5 V
RL = 100 kΩ, 0.5 V < VOUT < 4.5 V
RL = 100 kΩ, –40ⴗC ≤ TA ≤ +125ⴗC
0
63
56
100
100
70
25
400
3.5
400
IL = 100 µA
–40ⴗC ≤ TA ≤ +125ⴗC
IL = 1 mA
IL = 100 µA
–40ⴗC ≤ TA ≤ +125ⴗC
IL = 1 mA
Short to Ground, Instantaneous
VS = 2.2 V to 6 V,
–40ⴗC ≤ TA ≤ +125ⴗC
VOUT = 2.5 V
–40ⴗC ≤ TA ≤ +125ⴗC
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling Time
Phase Margin
SR
GBP
TS
φm
1 V < VOUT < 4 V, RL = 10 kΩ
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.1%
4.965
4.7
V
V
35
200
± 10
75
72
90
300
450
650
mV
mV
mA
dB
dB
µA
µA
3
5
860
53
V/µs
MHz
ns
Degrees
0.8
23
1.7
µV p-p
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
–2–
REV. 0
AD8631/AD8632
ELECTRICAL CHARACTERISTICS (V = 2.2 V, V– = 0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IB
IOS
VCM
CMRR
Large Signal Voltage Gain
AVO
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Output Voltage Swing Low
VOH
VOL
CM
= 1.1 V, TA = 25ⴗC unless otherwise noted)
Conditions
Min
Typ
Max
Unit
0.8
4.0
6
250
± 150
2.2
mV
mV
nA
nA
V
dB
dB
V/mV
V/mV
–40ⴗC ≤ TA ≤ +125ⴗC
0 V ≤ VCM ≤ 2.2 V,
–40ⴗC ≤ TA ≤ +125ⴗC
RL = 10 kΩ, 0.5 V < VOUT < 1.7 V
RL = 100 kΩ
IL = 100 µA
IL = 750 µA
IL = 100 µA
IL = 750 µA
0
54
47
50
70
25
200
2.165
1.9
35
200
V
V
mV
mV
350
500
µA
µA
POWER SUPPLY
Supply Current/Amplifier
ISY
VOUT = 1.1 V
–40ⴗC ≤ TA ≤ +125ⴗC
250
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
φm
RL = 10 kΩ
2.5
4.3
50
V/µs
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
en
in
f = 1 kHz
f = 1 kHz
23
1.7
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
REV. 0
–3–
AD8631/AD8632–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 1.8 V, V– = 0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
VOS
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IB
IOS
VCM
CMRR
Large Signal Voltage Gain
AVO
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Output Voltage Swing Low
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
VOH
VOL
PSRR
ISY
CM
= 0.9 V, TA = 25ⴗC unless otherwise noted)
Conditions
Min
Typ
Max
Unit
0.8
4.0
6
250
± 150
1.8
mV
mV
nA
nA
V
0ⴗC ≤ TA ≤ 125ⴗC
0
0 V ≤ VCM ≤ 1.8 V,
0ⴗC ≤ TA ≤ 125ⴗC
RL = 10 kΩ, 0.5 V < VOUT < 1.3 V
RL = 100 kΩ, 0.5 V < VOUT < 1.3 V
49
40
IL = 100 µA
IL = 750 µA
IL = 100 µA
IL = 750 µA
1.765
1.5
VS = 1.7 V to 2.2 V,
0ⴗC ≤ TA ≤ 125ⴗC
VOUT = 0.9 V
0ⴗC ≤ TA ≤ 125ⴗC
68
65
65
20
200
dB
V/mV
V/mV
35
200
V
V
mV
mV
325
450
dB
dB
µA
µA
86
225
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
φm
RL = 10 kΩ
2
4
49
V/µs
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
en
in
f = 1 kHz
f = 1 kHz
23
1.7
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
–4–
REV. 0
AD8631/AD8632
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 0.6 V
Internal Power Dissipation
SOT-23 (RT) . . . . . . . . . . . . See Thermal Resistance Chart
SOIC (R) . . . . . . . . . . . . . . . See Thermal Resistance Chart
µSOIC (RM) . . . . . . . . . . . . See Thermal Resistance Chart
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
R, RM, and RT Packages . . . . . . . . . . . . . –65ⴗC to +150ⴗC
Operating Temperature Range
AD8631, AD8632 . . . . . . . . . . . . . . . . . . –40ⴗC to +125ⴗC
Junction Temperature Range
R, RM, and RT Packages . . . . . . . . . . . . . –65ⴗC to +150ⴗC
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300ⴗC
Package Type
␪JA1
␪JC
Unit
5-Lead SOT-23 (RT)
8-Lead SOIC (R)
8-Lead µSOIC (RM)
230
158
210
146
43
45
ⴗC/W
ⴗC/W
ⴗC/W
NOTE
1
θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered
in circuit board for SOT-23 and SOIC packages.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
For supply voltages less than 6 V the input voltage is limited to the supply voltage.
ORDERING GUIDE
Temperature
Range
Model
1
AD8631ART –40ⴗC to +125ⴗC
AD8632AR
–40ⴗC to +125ⴗC
AD8632ARM2 –40ⴗC to +125ⴗC
Package
Description
Package
Option
5-Lead SOT-23
8-Lead SOIC
8-Lead µSOIC
RT-5
SO-8
RM-8
Brand
AEA
AGA
NOTES
1
Available in 3,000-piece reels only.
2
Available in 2,500-piece reels only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8631/AD8632 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
120
ESD SENSITIVE DEVICE
350
VS = 5V
VCM = 2.5V
TA = 25ⴗC
COUNT = 1,133 OP AMPS
TA = 25ⴗC
325
90
SUPPLY CURRENT – ␮A
QUANTITY OF AMPLIFIERS
WARNING!
60
30
300
275
250
225
0
–4
–3
–2
–1
0
1
2
INPUT OFFSET VOLTAGE – mV
3
200
4
Figure 1. Input Offset Voltage Distribution
REV. 0
1
2
3
4
SUPPLY VOLTAGE – V
5
6
Figure 2. Supply Current per Amplifier vs. Supply Voltage
–5–
AD8631/AD8632 – Typical Characteristics
40
VS = 5V
TA = 25ⴗC
VS = 5V
30
GAIN
OPEN-LOOP GAIN – dB
SUPPLY CURRENT – ␮A
450
400
350
300
250
200
ⴚ50
20
90
10
PHASE
0
ⴚ45
ⴚ10
ⴚ90
ⴚ20
ⴚ30
ⴚ25
0
25
50
TEMPERATURE – ⴗC
75
100
ⴚ40
100k
125
Figure 3. Supply Current per Amplifier vs. Temperature
10M
1M
FREQUENCY – Hz
100M
Figure 6. Open-Loop Gain vs. Frequency
150
50
VS = ⴞ2.5V
TA = 25ⴗC
VS = ±2.5V
TA = 25ⴗC
40
CLOSED-LOOP GAIN – dB
100
INPUT BIAS CURRENT – nA
45
0
PHASE SHIFT – Degrees
500
50
0
ⴚ50
ⴚ100
30
20
10
0
ⴚ10
ⴚ20
ⴚ30
ⴚ150
ⴚ3
ⴚ2
0
ⴚ1
1
COMMON-MODE VOLTAGE – V
2
ⴚ40
3
Figure 4. Input Bias Current vs. Common-Mode Voltage
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
Figure 7. Closed-Loop Gain vs. Frequency
140
0
VS = ⴞ2.5V
TA = 25ⴗC
TA = 25ⴗC
120
CMRR – dB
OUTPUT VOLTAGE – mV
20
100
80
60
40
60
40
SOURCE
80
20
0
10
1k
100
LOAD CURRENT – ␮A
100
10k
Figure 5. Output Voltage to Supply Rail vs. Load Current
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 8. CMRR vs. Frequency
–6–
REV. 0
AD8631/AD8632
60
0
VS = ⴞ2.5V
TA = 25ⴗC
20
OUTPUT IMPEDANCE – ⍀
ⴚPSRR
PSRR – dB
40
ⴙPSRR
60
80
40
20
AV = +1
10
10
1k
10k
100k
FREQUENCY – Hz
100
1M
0
10M
Figure 9. PSRR vs. Frequency
VOLTAGE NOISE DENSITY – pA/ Hz
40
ⴚOS
30
20
+OS
10
10k
100k
FREQUENCY – Hz
1M
10M
100M
40
30
20
10
0
10
100
10
Figure 10. Overshoot vs. Capacitance Load
5
4
3
2
1
0
10k
100k
FREQUENCY – Hz
10k
5
VS = 5V
AV = +1
RL = 10k⍀
TA = 25ⴗC
CL = 15pF
3%
CURRENT NOISE DENSITY – pA/ Hz
DISTORTION
100
1k
FREQUENCY – Hz
Figure 13. Voltage Noise Density vs. Frequency
6
MAXIMUM OUTPUT SWING – V p-p
1k
VS =5V
TA = 25ⴗC
CAPACITANCE – pF
VS = 5V
TA = 25ⴗC
4
3
2
1
0
10
1M
Figure 11. Output Swing vs. Frequency
REV. 0
100
50
VS = 5V
VCM = 2.5V
RL = 10k⍀
TA = 25ⴗC
VIN = ⴞ50mV
AV = +1
50
0
10
Figure 12. Output Impedance vs. Frequency
60
OVERSHOOT – %
AV = +10
30
100
120
VS = 5V
TA = 25ⴗC
50
100
1k
FREQUENCY – Hz
10k
Figure 14. Current Noise Density vs. Frequency
–7–
AD8631/AD8632
0
0
VS = ⴞ2.5V
TA = 25ⴗC
0
0
VOLTAGE – 20mV/DIV
VOLTAGE – 200nV/DIV
0
0
0
0
0
0
0
0
0
0
0
0
VS = ⴞ2.5V
AV = +1
TA = 25ⴗC
CL = 33pF
RL = 10k⍀
0
TIME – 1s/DIV
TIME – 250ns/DIV
Figure 15. 0.1 Hz to 10 Hz Noise
Figure 17. Small Signal Transient Response
0
0
VS = ⴞ2.5V
AV = 1
VIN = SINE WAVE
TA = 25ⴗC
VOLTAGE – 500mV/DIV
VOLTAGE – 1V/DIV
0
0
0
0
0
0
0
0
0
0
0
0
0
VS = ⴞ2.5V
AV = +1
TA = 25ⴗC
CL = 100pF
RL = 10k⍀
0
TIME – 200␮s/DIV
TIME – 500ns/DIV
Figure 16. No Phase Reversal
Figure 18. Large Signal Transient Response
configuration. The output swing when sinking or sourcing 100 µA
is 35 mV maximum from each rail.
THEORY OF OPERATION
The AD863x is a rail-to-rail operational amplifier that can operate
at supply voltages as low as 1.8 V. This family is fabricated using
Analog Devices’ high-speed complementary bipolar process, also
called XFCB. The process trench isolates each transistor to minimize parasitic capacitance, thereby allowing high-speed performance. Figure 19 shows a simplified schematic of the AD863x
family.
The input bias current characteristics depend on the commonmode voltage (see Figure 4). As the input voltage reaches about
1 V below VCC, the PNP pair (Q3 and Q4) turns off.
The 1 kΩ input resistor R1 and R2, together with the diodes D7
and D8, protect the input pairs against avalanche damage.
The AD863x family exhibits no phase reversal as the input signal
exceeds the supply by more than 0.6 V. Excessive current can flow
through the input pins via the ESD diodes D1-D2 or D3-D4, in the
event their ~0.6 V thresholds are exceeded. Such fault currents must
be limited to 5 mA or less by the use of external series resistance(s).
The input stage consists of two parallel complementary differential pair: one NPN pair (Q1 and Q2) and one PNP pair (Q3 and
Q4). The voltage drops across R7, R8, R9, and R10 are kept low
for rail-to-rail operation. The major gain stage of the op amp is a
double-folded cascode consisting of transistors Q5, Q6, Q8, and
Q9. The output stage, which also operates rail-to-rail, is driven by
Q14. The transistors Q13 and Q10 act as level-shifters to give
more headroom during 1.8 V operation.
LOW VOLTAGE OPERATION
Battery Voltage Discharge
The AD8631 operates at supply voltages as low as 1.8 V. This
amplifier is ideal for battery-powered applications since it can
operate at the end of discharge voltage of most popular batteries.
Table I lists the Nominal and End-of-Discharge Voltages of
several typical batteries.
As the voltage at the base of Q13 increases, Q18 starts to sink
current. When the voltage at the base of Q13 decreases I8 flows
through D16 and Q15 increasing the VBE of Q17, then Q20
sources current.
The output stage also furnishes gain, which depends on the load
resistance, since the output transistors are in common emitter
–8–
REV. 0
AD8631/AD8632
VCC
R7
D1
VCC
R8
R14
Q19
Q6
I1
ESD
Q7
Q5
I7
D3
ESD
R3
ⴚIN
Q3
R1
C4
R4
Q2
Q1
ⴙIN
Q14
R2
R5
D9
I3
Q4
D7
Q20
I8
Q11
VOUT
R6
D8
Q10
C3
Q13
C1
D4
ESD
D2
Q8
Q9
C2
Q18
ESD
I2
R11
I4
R9
Q17
I5
D16
D6
R13
VEE
Q15
I6
R10
R12
VEE
Figure 19. Simplified Schematic
The rail-to-rail feature of the AD8631 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.
Table I. Typical Battery Life Voltage Range
Battery
Nominal
Voltage (V)
End-of-Voltage
Discharge (V)
Lead-Acid
Lithium
NiMH
NiCd
Carbon-Zinc
2
2.6–3.6
1.2
1.2
1.5
1.8
1.7–2.4
1
1
1.1
INPUT BIAS CONSIDERATION
The input bias current (IB) is a non-ideal, real-life parameter that
affects all op amps. IB can generate a somewhat significant offset
voltage. This offset voltage is created by IB when flowing through
the negative feedback resistor RF. If IB is 250 nA (worst case), and
RF is 100 kΩ, the corresponding generated offset voltage is 25 mV
(VOS = IB RF).
RAIL-TO-RAIL INPUT AND OUTPUT
Obviously the lower the RF the lower the generated voltage offset.
Using a compensation resistor, RB, as shown in Figure 21, can
minimize this effect. With the input bias current minimized we
still need to be aware of the input offset current (IOS) which will
generate a slight offset error. Figure 21 shows three different
configurations to minimize IB-induced offset errors.
The AD8631 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier’s
supply set to 1.8 V, the input can be set to 1.8 V p-p, allowing the
output to swing to both rails without clipping. Figure 20 shows a
scope picture of both input and output taken at unity gain, with a
frequency of 1 kHz, at VS = 1.8 V and VIN = 1.8 V p-p.
RF
VS = 1.8V
VIN = 1.8V p-p
RI
VI
AD8631
VIN
VOUT
INVERTING CONFIGURATION
RB = RIⱍⱍRF
RF
RI
VOUT
AD8631
VI
VOUT
NONINVERTING CONFIGURATION
RB = RIⱍⱍRF
RF = RS
TIME – 200␮s/Div
AD8631
Figure 20. Rail-to-Rail Input Output
VI
VOUT
UNITY GAIN BUFFER
RS
Figure 21. Input Bias Cancellation Circuits
REV. 0
–9–
AD8631/AD8632
DRIVING CAPACITIVE LOADS
Capacitive Load vs. Gain
90kHz INPUT SIGNAL
AV = 1
C = 600pF
VOLTAGE – 200mV/DIV
Most amplifiers have difficulty driving capacitance due to degradation of phase margin caused by additional phase lag from the
capacitive load. Higher capacitance at the output can increase the
amount of overshoot and ringing in the amplifier’s step response
and could even affect the stability of the device. The value of
capacitive load that an amplifier can drive before oscillation varies
with gain, supply voltage, input signal, temperature, among others. Unity gain is the most challenging configuration for driving
capacitive load. However, the AD8631 offers reasonably good
capacitive driving ability. Figure 22 shows the AD8631’s ability to
drive capacitive loads at different gains before instability occurs.
This graph is good for all VSY.
TIME – 2␮s/DIV
1M
Figure 24. Driving Capacitive Loads without Compensation
UNSTABLE
By connecting a series R–C from the output of the device to
ground, known as the “snubber” network, this ringing and overshoot can be significantly reduced. Figure 25 shows the network
setup, and Figure 26 shows the improvement of the output
response with the “snubber” network added.
CAPACITIVE LOAD – pF
100k
10k
1k
5V
STABLE
100
AD8631
10
2
1
3
4
5
6
GAIN – V/V
7
8
9
VIN
10
VOUT
RX
CL
CX
Figure 22. Capacitive Load vs. Gain
In-the-Loop Compensation Technique for Driving
Capacitive Loads
Figure 25. Snubber Network Compensation for Capacitive
Loads
When driving capacitance in low gain configuration, the in-the-loop
compensation technique is recommended to avoid oscillation as is
illustrated in Figure 23.
RG
VOLTAGE – 200mV/DIV
RF
90kHz INPUT SIGNAL
AV = 1
C = 600pF
VIN
CF
RX
VOUT
AD8631
CL
RX =
RO RG
RF
WHERE RO = OPEN-LOOP OUTPUT RESISTANCE
CF =
[
1+
1
ACL
[
RF + RG
RF
CLRO
Figure 23. In-the-Loop Compensation Technique for
Driving Capacitive Loads
Snubber Network Compensation for Driving Capacitive Loads
As load capacitance increases, the overshoot and settling time
will increase and the unity gain bandwidth of the device will
decrease. Figure 24 shows an example of the AD8631 in a noninverting configuration driving a 10 kΩ resistor and a 600 pF
capacitor placed in parallel, with a square wave input set to a
frequency of 90 kHz and unity gain.
TIME – 2␮s/DIV
Figure 26. Photo of a Square Wave with the Snubber
Network Compensation
The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor have to be empirically
determined. Table II shows some values of snubber network for
large capacitance load.
–10–
REV. 0
AD8631/AD8632
Table II. Snubber Network Values for Large Capacitive Loads
CLOAD
Rx
Cx
600 pF
1 nF
10 nF
300 Ω
300 Ω
90 Ω
1 nF
1 nF
8 nF
A MICROPOWER REFERENCE VOLTAGE GENERATOR
Many single-supply circuits are configured with the circuit biased
to one-half of the supply voltage. In these cases, a false-ground
reference can be created by using a voltage divider buffered by an
amplifier. Figure 28 shows the schematic for such a circuit.
TOTAL HARMONIC DISTORTION + NOISE
The AD863x family offers a low total harmonic distortion, which
makes this amplifier ideal for audio applications. Figure 27 shows
a graph of THD + N, which is ~0.02% @ 1 kHz, for a 1.8 V supply.
At unity gain in an inverting configuration the value of the Total
Harmonic Distortion + Noise stays consistently low over all voltages supply ranges.
The two 1 MΩ resistors generate the reference voltages while
drawing only 0.9 µA of current from a 1.8 V supply. A capacitor
connected from the inverting terminal to the output of the op
amp provides compensation to allow a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
establish an ac ground for the reference output.
1.8V TO 5V
10k⍀
0.022␮F
10
INVERTING
AV = 1
1
100⍀
AD8631
1M⍀
VREF
0.9V TO 2.5V
THD + N – %
1␮F
1M⍀
0.1
VS = 1.8V
0.01
0.001
10
1␮F
Figure 29. A Micropower Reference Voltage Generator
VS = 5V
MICROPHONE PREAMPLIFIER
The AD8631 is ideal to use as a microphone preamplifier.
Figure 30 shows this implementation.
100
1k
FREQUENCY – Hz
10k 20k
R3
220k⍀
Figure 27. THD + N vs. Frequency Graph
1.8V
AD8632 Turn-On Time
1.8V
The low voltage, low power AD8632 features an extraordinary turn
on time. This is about 500 ns for VSY = 5 V, which is impressive
considering the low supply current (300 µA typical per amplifier).
Figure 28 shows a scope picture of the AD8632 with both channels
configured as followers. Channel A has an input signal of 2.5 V and
channel B has the input signal at ground. The top waveform shows
the supply voltage and the bottom waveform reflects the response
of the amplifier at the output of Channel A.
0
VOLTAGE – 1V/DIV
0
VS = 5V
AV = 1
VIN = 2.5V STEP
0
0V
0
0
0V
0
0
TIME – 200ns/DIV
Figure 28. AD8632 Turn-On Time
REV. 0
R1
2.2k⍀
C1
0.1␮F
R2
22k⍀
VIN
VOUT
AD8631
ELECTRET
MIC
AV = R3
R2
VREF = 0.9V
Figure 30. A Microphone Preamplifier
R1 is used to bias an electret microphone and C1 blocks dc voltage
from the amplifier. The magnitude of the gain of the amplifier is
approximately R3/R2 when R2 ≥ 10 R1. VREF should be equal to
1/2 1.8 V for maximum voltage swing.
Direct Access Arrangement for Telephone Line Interface
Figure 31 illustrates a 1.8 V transmit/receive telephone line interface
for 600 Ω transmission systems. It allows full duplex transmission of
signals on a transformer-coupled 600 Ω line in a differential manner.
Amplifier A1 provides gain that can be adjusted to meet the modem
output drive requirements. Both A1 and A2 are configured to apply
the largest possible signal on a single supply to the transformer.
Amplifier A3 is configured as a difference amplifier for two reasons:
(1) It prevents the transmit signal from interfering with the receive
signal and (2) it extracts the receive signal from the transmission line
for amplification by A4. A4’s gain can be adjusted in the same
manner as A1’s to meet the modem’s input signal requirements.
Standard resistor values permit the use of SIP (Single In-line
Package) format resistor arrays. Couple this with the AD8631/
–11–
AD8631/AD8632
AD8632’s 5-lead SOT-23, 8-lead µSOIC, and 8-lead SOIC
footprint and this circuit offers a compact solution.
TO TELEPHONE
LINE
1:1
2k⍀
R3
360⍀
1
C1
R1
10k⍀ 0.1␮F
2
A1
R5
10k⍀
6.2V
ZO
600⍀
R2
9.09k⍀
TRANSMIT
TxA
3
6.2V
+1.8V DC
T1
MIDCOM
671-8005
R6
10k⍀
6
7
A2
R7
10k⍀
5
R8
10k⍀
10␮F
R10
10k⍀
R9
10k⍀
2
R11
10k⍀
3
A3
1
R13
R14
10k⍀ 14.3k⍀
A1, A2 = 1/2 AD8632
A3, A4 = 1/2 AD8632
P2
Rx GAIN
ADJUST
2k⍀
6
R12
10k⍀
A4
5
7
The SPICE model for the AD8631 amplifier is available and
can be downloaded from the Analog Devices’ web site at
http://www.analog.com. The macro-model accurately simulates
a number of AD8631 parameters, including offset voltage, input
common-mode range, and rail-to-rail output swing. The output
voltage versus output current characteristics of the macro-model
is identical to the actual AD8631 performance, which is a critical
feature with a rail-to-rail amplifier model. The model also accurately
simulates many ac effects, such as gain-bandwidth product, phase
margin, input voltage noise, CMRR and PSRR versus frequency,
and transient response. Its high degree of model accuracy makes the
AD8631 macro-model one of the most reliable and true-to-life
models available for any amplifier.
C3810–2.5–4/00 (rev. 0)
P1
Tx GAIN
ADJUST
SPICE Model
RECEIVE
RxA
C2
0.1␮F
Figure 31. A Single-Supply Direct Access Arrangement
for Modems
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead ␮SOIC
(RM-8)
8-Lead Narrow Body SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.122 (3.10)
0.114 (2.90)
0.2440 (6.20)
0.2284 (5.80)
8
5
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8ⴗ
0ⴗ
4
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.0500 (1.27)
0.0160 (0.41)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.011 (0.28)
0.003 (0.08)
33ⴗ
27ⴗ
0.028 (0.71)
0.016 (0.41)
5-Lead SOT-23
(RT-5)
PRINTED IN U.S.A.
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.1181 (3.00)
0.1102 (2.80)
0.0669 (1.70)
0.0590 (1.50)
5
1
4
2
0.1181 (3.00)
0.1024 (2.60)
3
PIN 1
0.0374 (0.95) BSC
0.0748 (1.90)
BSC
0.0512 (1.30)
0.0354 (0.90)
0.0059 (0.15)
0.0019 (0.05)
0.0079 (0.20)
0.0031 (0.08)
0.0571 (1.45)
0.0374 (0.95)
0.0197 (0.50)
0.0138 (0.35)
SEATING
PLANE
–12–
10ⴗ
0ⴗ
0.0217 (0.55)
0.0138 (0.35)
REV. 0