MC74HC273A Octal D Flip-Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip−flops with common Clock and Reset inputs. Each flip−flop is loaded with a low−to−high transition of the Clock input. Reset is asynchronous and active low. www.onsemi.com SOIC−20 DW SUFFIX CASE 751D Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 264 FETs or 66 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant PIN ASSIGNMENT RESET 1 20 VCC Q0 D0 2 3 19 18 Q7 D7 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK RESET 2 4 5 7 6 8 9 13 12 17 15 16 18 19 11 1 Q0 Q3 Q4 NONINVERTING OUTPUTS D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 CLOCK 20 HC 273A ALYWG G 1 1 SOIC−20 TSSOP−20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) Q5 Q6 Q7 PIN 20 = VCC PIN 10 = GND FUNCTION TABLE Internal Gate Count* 66 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW .0075 pJ *Equivalent to a two−input NAND gate. October, 2015 − Rev. 17 Q6 Q5 Q2 Units © Semiconductor Components Industries, LLC, 2015 D6 16 15 HC273A AWLYYWWG Q1 Value Speed Power Product 17 5 6 20 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria 4 MARKING DIAGRAMS 3 14 D1 Q1 Q2 GND LOGIC DIAGRAM D0 TSSOP−20 DT SUFFIX CASE 948E 1 Inputs Output Reset Clock D Q L H H H H X X H L X X L H L No Change No Change L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: MC74HC273A/D MC74HC273A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. °C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/°C from 65° to 125°C TSSOP Package: −6.1 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 °C 0 0 0 1000 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Test Conditions VCC V –55 to 25°C v 85°C v 125°C Unit Symbol Parameter VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VIH VOL Maximum Low−Level Output Voltage Vin = VIL |Iout| v 20 mA Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA www.onsemi.com 2 V MC74HC273A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V –55 to 25°C v 85°C v 125°C Unit Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC V –55 to 25°C v 85°C v 125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 15 30 35 5.0 10 24 28 4.0 8.0 20 24 MHz tPLH tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 3.0 4.5 6.0 145 90 29 25 180 120 36 31 220 140 44 38 ns tPHL Maximum Propagation Delay, Reset to Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 145 90 29 25 180 120 36 31 220 140 44 38 ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Cin Maximum Input Capacitance 10 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 48 Power Dissipation Capacitance (Per Enabled Output)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC 2f pF + ICC VCC . ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter Figure –55 to 25°C VCC Volts Min Max v 85°C Min Max v 125°C Min Max Unit tsu Minimum Setup Time, Data to Clock 3 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns th Minimum Hold Time, Clock to Data 3 2.0 3.0 4.5 6.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ns trec Minimum Recovery Time, Reset Inactive to Clock 2 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock 1 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns www.onsemi.com 3 MC74HC273A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Symbol tw tr, tf Parameter Figure VCC Volts Min 60 23 12 10 Minimum Pulse Width, Reset 2 2.0 3.0 4.5 6.0 Maximum Input Rise and Fall Times 1 2.0 3.0 4.5 6.0 www.onsemi.com 4 Max Min Max 75 27 15 13 1000 800 500 400 Min Max 90 32 18 15 1000 800 500 400 Unit ns 1000 800 500 400 ns MC74HC273A SWITCHING WAVEFORMS tr CLOCK tw tf VCC 90% 50% 10% tw GND GND 1/fmax tPHL 50% Q tPHL tPLH Q VCC 50% RESET trec 90% 50% 10% VCC CLOCK tTLH 50% GND tTHL Figure 1. Figure 2. C D0 3 VALID C VCC DATA DR D1 50% 4 DR Q Q 2 5 Q0 Q1 GND tsu th C VCC CLOCK D2 7 DR Q 6 Q2 50% GND C DATA INPUTS Figure 3. D3 8 DR C D4 13 DR C D5 14 C TEST POINT D6 17 OUTPUT DEVICE UNDER TEST DR D7 18 DR C DR Q 9 Q3 NONINVERTING OUTPUTS Q Q Q Q 12 15 16 19 Q4 Q5 Q6 Q7 CL* 11 1 *Includes all probe and jig capacitance Figure 4. Test Circuit Figure 5. Expanded Logic Diagram www.onsemi.com 5 MC74HC273A ORDERING INFORMATION Package Shipping† MC74HC273ADWG SOIC−20 WB (Pb−Free) 38 Units / Rail MC74HC273ADWR2G SOIC−20 WB (Pb−Free) 1000 / Tape & Reel NLV74HC273ADWR2G* SOIC−20 WB (Pb−Free) 1000 / Tape & Reel MC74HC273ADTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74HC273ADTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel NLV74HC273ADTR2G* TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 6 MC74HC273A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B −U− L PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S N A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC273A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SEATING PLANE C T ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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