Elpida EBS25EC8APSA-80L 256mb sdram s.o.dimm Datasheet

DATA SHEET
256MB SDRAM S.O.DIMM
EBS25EC8APSA (32M words × 72 bits, 1 bank)
Description
Features
The EBS25EC8APSA is 32M words × 72 bits, 1 bank
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 9 pieces of
256M bits SDRAM (EDS2508APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology.
Decoupling
capacitors are mounted on power supply line for noise
reduction.
• Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
• 144-pin socket type small outline dual in line memory
module (S.O.DIMM)
 PCB height: 38.10mm (1.5inch )
 Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 100MHz 133MHz (max.)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
 Sequential
 Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
Document No. E0227E20 (Ver. 2.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
EBS25EC8APSA
Ordering Information
Part number
Clock frequency
MHz (max.)
/CAS latency Package
EBS25EC8APSA-7A
EBS25EC8APSA-75 *
EBS25EC8APSA-80
EBS25EC8APSA-7AL
EBS25EC8APSA-75L*
EBS25EC8APSA-80L
133
133
100
133
133
100
2, 3
3
2, 3
2, 3
3
2, 3
144-pin S.O.DIMM
Contact pad
Mounted devices
Gold
EDS2508APTA
Note: 100MHz operation at /CAS latency = 2.
Pin Configurations
Front Side
1pin
59pin
61pin
143pin
2pin
60pin
62pin
144pin
Back Side
Front side
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
73
NC
2
VSS
74
CLK1
3
DQ0
75
VSS
4
DQ32
76
VSS
5
DQ1
77
CB4
6
DQ33
78
CB5
7
DQ2
79
CB6
8
DQ34
80
CB7
9
DQ3
81
VDD
10
DQ35
82
VDD
11
VDD
83
DQ16
12
VDD
84
DQ48
13
DQ4
85
DQ17
14
DQ36
86
DQ49
15
DQ5
87
DQ18
16
DQ37
88
DQ50
17
DQ6
89
DQ19
18
DQ38
90
DQ51
19
DQ7
91
VSS
20
DQ39
92
VSS
21
VSS
93
DQ20
22
VSS
94
DQ52
23
DQMB0
95
DQ21
24
DQMB4
96
DQ53
25
DQMB1
97
DQ22
26
DQMB5
98
DQ54
27
VDD
99
DQ23
28
VDD
100
DQ55
29
A0
101
VDD
30
A3
102
VDD
31
A1
103
A6
32
A4
104
A7
33
A2
105
A8
34
A5
106
BA0
35
VSS
107
VSS
36
VSS
108
VSS
37
DQ8
109
A9
38
DQ40
110
BA1
39
DQ9
111
A10 (AP)
40
DQ41
112
A11
41
DQ10
113
VDD
42
DQ42
114
VDD
Data Sheet E0227E20 (Ver. 2.0)
2
EBS25EC8APSA
Front side
Pin No.
Back side
Pin name
Pin No.
Pin name
43
DQ11
115
DQMB2
45
VDD
117
DQMB3
47
DQ12
119
VSS
49
DQ13
121
51
DQ14
123
53
DQ15
55
57
59
Pin No.
Pin name
Pin No.
Pin name
44
DQ43
116
DQMB6
46
VDD
118
DQMB7
48
DQ44
120
VSS
DQ24
50
DQ45
122
DQ56
DQ25
52
DQ46
124
DQ57
125
DQ26
54
DQ47
126
DQ58
VSS
127
DQ27
56
VSS
128
DQ59
CB0
129
VDD
58
CB1
130
VDD
CB2
131
DQ28
60
CB3
132
DQ60
61
CLK0
133
DQ29
62
CKE0
134
DQ61
63
VDD
135
DQ30
64
VDD
136
DQ62
65
/RAS
137
DQ31
66
/CAS
138
DQ63
67
/WE
139
VSS
68
NC
140
VSS
69
/CS0
141
SDA
70
A12
142
SCL
71
NC
143
VDD
72
NC
144
VDD
Pin Description
Pin name
Function
A0 to A12
Address input
 Row address
A0 to A12
 Column address A0 to A9
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
/CS0
Chip select input
/RAS
Row enable (/RAS) input
/CAS
Column enable (/CAS) input
/WE
Write enable input
DQMB0 to DQMB7
Byte data mask
CLK0, CLK1
Clock input
CKE0
Clock enable input
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
VDD
Primary positive power supply
VSS
Ground
NC
No connection
Data Sheet E0227E20 (Ver. 2.0)
3
EBS25EC8APSA
Serial PD Matrix
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes used by module
manufacturer
1
0
0
0
0
0
0
0
80H
128 bytes
1
Total SPD memory size
0
0
0
0
1
0
0
0
08H
256 bytes
2
Memory type
0
0
0
0
0
1
0
0
04H
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
1
0DH
13
4
Number of column addresses bits
0
0
0
0
1
0
1
0
0AH
10
5
Number of banks
0
0
0
0
0
0
0
1
01H
1
6
Module data width
0
1
0
0
1
0
0
0
48H
72 bits
7
Module data width (continued)
0
0
0
0
0
0
0
0
00H
0
8
Module interface signal levels
0
0
0
0
0
0
0
1
01H
LVTTL
9
SDRAM cycle time at CL = 3
(highest /CAS latency)
(-7A/7AL, -75/75L)
0
1
1
1
0
1
0
1
75H
7.5ns
1
0
0
0
0
0
0
0
80H
8ns
SDRAM access from Clock at CL = 3
(highest /CAS latency)
0
(-7A/7AL, -75/75L)
1
0
1
0
1
0
0
54H
5.4ns
0
1
1
0
0
0
0
0
60H
6ns
(-80/80L)
10
(-80/80L)
11
Module configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8µs
13
SDRAM width
0
0
0
0
1
0
0
0
08H
×8
Error checking SDRAM width
0
0
0
0
1
0
0
0
08H
×8
0
0
0
0
0
0
0
1
01H
1 CLK
1
0
0
0
1
1
1
1
8FH
1, 2, 4, 8, F
0
0
0
0
0
1
0
0
04H
4
0
0
0
0
0
1
1
0
06H
2, 3
0
0
0
0
0
0
0
1
01H
0
0
0
0
0
0
0
0
1
01H
0
SDRAM device attributes
0
0
0
0
0
0
0
0
00H
22
SDRAM device attributes: General
0
0
0
0
1
1
1
0
0EH
23
SDRAM cycle time at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)
0
1
1
1
0
1
0
1
75H
7.5ns
1
0
1
0
0
0
0
0
A0H
10ns
SDRAM access from Clock at CL = 2
0
(2nd highest /CAS latency)
(-7A/7AL)
1
0
1
0
1
0
0
54H
5.4ns
0
1
1
0
0
0
0
0
60H
6ns
0
0
0
0
0
0
0
0
00H
0
0
0
0
1
1
1
1
0FH
15ns
0
0
0
1
0
1
0
0
14H
20ns
14
15
16
17
18
19
20
21
SDRAM device attributes:
minimum clock delay for back-toback random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes: number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
(-75/75L, -80/80L)
24
(-75/75L, -80/80L)
25 to 26
27
Minimum row precharge time
(-7A/7AL)
(-75/75L, -80/80L)
Data Sheet E0227E20 (Ver. 2.0)
4
EBS25EC8APSA
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
28
Row active to row active min
(-7A/7AL, -75/75L)
0
0
0
0
1
1
1
1
0FH
15ns
0
0
0
1
0
0
0
0
10H
16ns
29
/RAS to /CAS delay min
(-7A/7AL)
0
0
0
0
1
1
1
1
0FH
15ns
0
0
0
1
0
1
0
0
14H
20ns
30
Minimum /RAS pulse width
(-7A/7AL, -75/75L)
0
0
1
0
1
1
0
1
2DH
45ns
0
0
1
1
0
0
0
0
30H
48ns
31
Density of each bank on module
0
1
0
0
0
0
0
0
40H
256MB
32
Address and command signal input
setup time
(-7A/7AL, -75/75L)
0
0
0
1
0
1
0
1
15H
1.5ns
0
0
1
0
0
0
0
0
20H
2ns
33
Address and command signal input
hold time
(-7A/7AL, -75/75L)
0
0
0
0
1
0
0
0
08H
0.8ns
0
0
0
1
0
0
0
0
10H
1ns
0
0
0
1
0
1
0
1
15H
1.5ns
0
0
1
0
0
0
0
0
20H
2ns
0
0
0
0
1
0
0
0
08H
0.8ns
1ns
(-80/80L)
(-75/75L, -80/80L)
(-80/80L)
(-80/80L)
(-80/80L)
34
Data signal input setup time
(-7A/7AL, -75/75L)
35
Data signal input hold time
(-7A/7AL, -75/75L)
0
0
0
1
0
0
0
0
10H
36 to 61
Superset information
0
0
0
0
0
0
0
0
00H
62
SPD data revision code
0
0
0
1
0
0
1
0
12H
63
Checksum for Bytes 0 to 62
(-7A/7AL)
1
0
1
0
0
0
1
1
A3H
(-75/75L)
1
1
1
0
0
1
0
0
E4H
(-80/80L)
(-80/80L)
(-80/80L)
0
0
1
0
0
1
0
1
25H
64
Manufacturer’s JEDEC ID code
1
1
1
1
1
1
1
0
FEH
65 to 71
Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
00H
0
1
1
0
0
1
0
0
64H
1
1
0
0
0
1
1
1
C7H
72
Manufacturing location
73 to 90
Manufacturer’s part number
91 to 92
Revision code
93 to 94
Manufacturing date
95 to 98
Assembly serial number
1.2
Elpida Memory
99 to 125 Manufacturer specific data
126
127
Reserved (Intel specification
frequency)
Reserved (Intel specification /CAS#
latency support)
Data Sheet E0227E20 (Ver. 2.0)
5
100MHz
EBS25EC8APSA
Block Diagram
/WE
/CS0
DQMB0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB2
DQ 7 DQM
DQ 6
DQ 5
DQ 4
DQ 0
DQ 1
DQ 2
DQ 3
/CS
/WE
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
D0
/WE
DQ 4 DQM /CS
DQ 5
DQ 6
DQ 7
D4
DQ 3
DQ 2
DQ 1
DQ 0
/WE
DQ 3 DQM /CS
DQ 2
DQ 1
DQ 0
D7
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQ 3 DQM /CS
DQ 2
DQ 1
DQ 0
D8
DQ 4
DQ 5
DQ 6
DQ 7
/WE
DQMB3
DQMB1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 4 DQM /CS
DQ 5
DQ 6
DQ 7
D3
DQ 3
DQ 2
DQ 1
DQ 0
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D1
DQ 7
DQ 6
DQ 5
DQ 4
/WE
DQ 7 DQM
/WE
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQMB6
CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
/CS
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
D2
DQMB7
DQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
D5
DQ 7
DQ 6
DQ 5
DQ 4
/WE
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
D6
DQ 0
DQ 1
DQ 2
DQ 3
/WE
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
CLK0
CLK : D0, D1, D2, D3, D8 A0 to A12
A0 - A12 : D0 to D8
CLK1
CLK : D4, D5, D6, D7
BA0
BA0 : D0 to D8
BA1
BA1 : D0 to D8
/RAS
/RAS : D0 to D8
/CAS
/CAS : D0 to D8
CKE0
CKE : D0 to D8
Serial PD
VCC
D0 to D8
C
VSS
Remarks
SDA
SCL
D0 to D8
1. The value of all resistors is 10W.
2. D0 to D8: EDS2508APTA (8M words ´ 8 bits ´ 4 banks)
Data Sheet E0227E20 (Ver. 2.0)
6
A0
A1
A2
EBS25EC8APSA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VT
–0.5 to VDD + 0.5
(≤ 4.6 (max.))
V
Supply voltage relative to VSS
VDD
–0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
9
W
Operating temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note
1
Notes: 1. SDRAM device specification
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (SDRAM device specification)
Parameter
Symbol
min.
max.
Unit
Note
Supply voltage
VDD
3.0
3.6
V
1
VSS
0
0
V
2
Input high voltage
VIH
2.0
VDD + 0.3
V
3
Input low voltage
VIL
−0.3
0.8
V
4
Notes: 1.
2.
3.
4.
The supply voltage with all VDD pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
VIH (max.) = VDD + 2.0V for pulse width ≤ 3ns at VDD.
VIL (min.) = VSS − 2.0V for pulse width ≤ 3ns at VSS.
Data Sheet E0227E20 (Ver. 2.0)
7
EBS25EC8APSA
DC Characteristics 1 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V)
Parameter
Operating current
Symbol
Grade
max.
Unit
Test condition
Notes
Burst length = 1
tRC = tRC (min.)
1, 2, 3
ICC1
-7A/7AL 1170
mA
ICC1
-75/75L
990
mA
ICC1
-80/80L
955
mA
ICC2P
27
mA
CKE = VIL, tCK = 12ns
6
ICC2N
180
mA
CKE, /CS = VIH,
tCK = 12ns
4
ICC3P
36
mA
CKE = VIL, tCK = 12ns
1, 2, 6
ICC3N
270
mA
CKE, /CS = VIH,
tCK = 12ns
1, 2, 4
Burst operating current
ICC4
1215
mA
tCK = tCK (min.), BL = 4
1, 2, 5
Refresh current
ICC5
-7A/7AL 2250
mA
tRC = tRC (min.)
3
ICC5
-75/75L
1980
mA
ICC5
-80/80L
1910
mA
27
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
7
9
mA
Standby current in power down
Standby current in non power
down
Active standby current in power
down
Active standby current in non
power down
Self refresh current
ICC6
Self refresh current
(L-version)
ICC6
-XXL
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After self refresh mode set, self refresh current.
DC Characteristics 2 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–9
9
µA
0 ≤ VIN ≤ VDD
Output leakage current
ILO
–1.5
1.5
µA
0 ≤ VOUT ≤ VDD
DQ = disable
Output high voltage
VOH
2.4
—
V
IOH = –4mA
Output low voltage
VOL
—
0.4
V
IOL = 4mA
Data Sheet E0227E20 (Ver. 2.0)
8
Notes
EBS25EC8APSA
Pin Capacitance (TA = 25°C, VDD = 3.3V ± 0.3V)
Parameter
Symbol
Input capacitance
Data input/output capacitance
Pins
max.
Unit
CI1
Address
TBD
pF
CI2
/RAS, /CAS, /WE
TBD
pF
CI3
CKE
TBD
pF
CI4
/CAS
TBD
pF
CI5
CLK
TBD
pF
CI6
DQMB
TBD
pF
CI/O1
DQ, CB
TBD
pF
Notes
AC Characteristics (TA = 0 to 70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)
-7A/7AL
-75/75L
-80/80L
Parameter
Symbol min.
max.
min.
max.
min.
max.
Unit
Notes
System clock cycle time
(CL = 2)
tCK
7.5
—
10
—
10
—
ns
1
(CL = 3)
tCK
7.5
—
7.5
—
10
—
ns
CLK high pulse width
tCH
2.5
—
2.5
—
3
—
ns
1
CLK low pulse width
tCL
2.5
—
2.5
—
3
—
ns
1
Access time from CLK
tAC
—
5.4
—
5.4
—
6
ns
1, 2
Data-out hold time
tOH
2.7
—
2.7
—
2.7
—
ns
1, 2
CLK to Data-out low impedance
tLZ
1
—
1
—
1
—
ns
1, 2, 3
CLK to Data-out high impedance
tHZ
—
5.4
—
5.4
—
6
ns
1, 4
Input setup time
tSI
1.5
—
1.5
—
2
—
ns
1
Input hold time
tHI
0.8
—
0.8
—
1
—
ns
1
Ref/Active to Ref/Active command period tRC
60
—
67.5
—
70
—
ns
1
Active to Precharge command period
tRAS
45
120000 45
120000 48
120000 ns
1
Active command to column command
(same bank)
tRCD
15
—
20
—
20
—
ns
1
Precharge to active command period
tRP
15
—
20
—
20
—
ns
1
Write recovery or data-in to precharge
lead time
tDPL
15
—
15
—
20
—
ns
1
Last data into active latency
tDAL
2CLK +
—
15ns
1
2CLK +
—
20ns
2CLK +
—
20ns
Active (a) to Active (b) command period
tRRD
15
—
15
—
20
—
ns
Transition time (rise and fall)
tT
0.5
5
0.5
5
0.5
5
ns
Refresh period
(8192 refresh cycles)
tREF
—
64
—
64
—
64
ms
Notes: 1.
2.
3.
4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
Access time is measured at 1.4V. Load condition is CL = 50pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0227E20 (Ver. 2.0)
9
EBS25EC8APSA
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4V
0.4V
DQ
2.0V
0.8V
CL
tT
tT
Input Waveform and Output Load
Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter
-7A/7AL
-75/75L
-80/80L
Frequency (MHz)
133
133
10
tCK (ns)
7.5
7.5
10
Symbol
CL = 2
CL = 3
CL = 2
Notes
lRCD
2
3
2
1
lRC
8
9
7
1
lRAS
6
6
5
1
lRP
2
3
2
1
lDPL
2
2
2
1
lRRD
2
2
2
1
Self refresh exit time
lSREX
1
1
1
2
Last data in to active command
(Auto precharge, same bank)
lDAL
4
5
4
= [lDPL + lRP]
Self refresh exit to command input
lSEC
8
9
7
= [lRC]
3
Precharge command to high impedance
lHZP
2
3
2
Last data out to active command
(auto precharge) (same bank)
lAPR
1
1
1
Last data out to precharge (early precharge)
lEP
–1
–2
–1
Column command to column command
lCCD
1
1
1
Write command to data in latency
lWCD
0
0
0
DQM to data in
lDID
0
0
0
DQM to data out
lDOD
2
2
2
CKE to CLK disable
lCLE
1
1
1
Register set to active command
lMRD
2
2
2
/CS to command disable
lCDD
0
0
0
Power down exit to command input
lPEC
1
1
1
/CAS latency
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0227E20 (Ver. 2.0)
10
EBS25EC8APSA
Pin Functions
CLK0, CLK1 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
/CS0 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the combination
of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command
cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command
cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge
mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
CKE0 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend
modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the
DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data
is written.
DQ0 to DQ63 (input/output pins): Data is input to and output from these pins.
CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VDD (power supply pins): 3.3V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the EDS2504AC/08AC/16AC, EDS2504AP/08AP/16AP datasheet (E0110E).
Data Sheet E0227E20 (Ver. 2.0)
11
EBS25EC8APSA
Physical Outline
Unit:mm
63.60
3.80 Max
24.50
(Datum -A-)
1
B
23.20
3.30
32.80
4.00 Min
20.00
143
6.00
Component area
(front)
3.20 Min
38.10 ± 0.15
2R3.00 Min
A
1.00 ± 0.10
4.60
2.50
67.6 ± 0.15
2.10
4.60
2- ø1.80
4.00 ± 0.10
32.80
144
23.20
2
3.70
Component area
(back)
2-R2.00
2.00 Min
(Datum -A-)
Detail B
Detail A
(DATUM -A-)
2.5
R0.75
4.00 ± 0.10
2.55 Min
0.25 Max
0.60 ± 0.05
0.80
1.50 ± 0.10
ECA-TS2-0048-01
Data Sheet E0227E20 (Ver. 2.0)
12
EBS25EC8APSA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0227E20 (Ver. 2.0)
13
EBS25EC8APSA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0227E20 (Ver. 2.0)
14