HP HCPL-5231 Hermetically sealed, low if, wide vcc, logic gate optocoupler Datasheet

Hermetically Sealed,
Low IF, Wide VCC,
Logic Gate Optocouplers
Technical Data
HCPL-520x*
5962-88768
HCPL-523x
HCPL-623x
HCPL-625x
5962-88769
*See matrix for available extensions.
Features
• Dual Marked with Device
Part Number and DSCC
Standard Microcircuit
Drawing
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Four Hermetically Sealed
Package Configurations
• Performance Guaranteed
over -55°C to +125 °C
• Wide VCC Range (4.5 to 20 V)
• 350 ns Maximum Propagation Delay
• CMR: > 10,000 V/µs Typical
• 1500 Vdc Withstand Test
Voltage
• Three State Output Available
• High Radiation Immunity
• HCPL-2200/31 Function
Compatibility
• Reliability Data Available
• Compatible with LSTTL,
TTL, and CMOS Logic
Applications
• Military and Space
• High Reliability Systems
• Transportation and Life
Critical Systems
• High Speed Line Receiver
• Isolated Bus Driver (Single
Channel)
• Pulse Transformer
Replacement
• Ground Loop Elimination
• Harsh Industrial
Environments
• Computer-Peripheral
Interfaces
Description
These units are single, dual and
quad channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level
H or K testing or from the
appropriate DSCC Drawing. All
devices are manufactured and
tested on a MIL-PRF-38534
certified line and are included in
the DSCC Qualified Manufacturers List QML-38534 for Hybrid
Microcircuits.
eliminates the potential for
output signal chatter. The
detector in the single channel
units has a tri-state output stage
Truth Tables
(Positive Logic)
Multichannel Devices
Input
Output
On (H)
H
Off (L)
L
Single Channel DIP
Input
Enable
On (H)
H
Off (L)
H
On (H)
L
Off (L)
L
Output
Z
Z
H
L
Functional Diagram
Multiple Channel Devices
Available
VCC
Each channel contains an AlGaAs
light emitting diode which is
optically coupled to an integrated
high gain photon detector. The
detector has a threshold with
hysteresis which provides differential mode noise immunity and
VO
VE
GND
A 0.1 µF bypass capacitor must be connected between VCC and GND pins.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
which allows for direct connection
to data buses. The output is noninverting. The detector IC has an
internal shield that provides a
guaranteed common mode
transient immunity of up to
10,000 V/µs. Improved power
supply rejection eliminates the
need for special power supply
bypass precautions.
Package styles for these parts are
8 pin DIP through hole (case
outline P), 16 pin DIP flat pack
(case outline F), and leadless
ceramic chip carrier (case outline
2). Devices may be purchased
with a variety of lead bend and
plating options, see Selection
Guide Table for details. Standard
Microcircuit Drawing (SMD)
parts are available for each
package and lead style.
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
listed in this data sheet, absolute
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the
figures are identical for all parts.
Occasional exceptions exist due
to package variations and limitations and are as noted. Additionally, the same package assembly
processes and materials are used
in all devices. These similarities
give justification for the use of
data obtained from one part to
represent other part’s performance for die related
reliability and certain limited
radiation test results.
Selection Guide–Package Styles and Lead Configuration Options
Package
Lead Style
Channels
Common Channel
Wiring
Agilent Part # & Options
Commercial
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped
Butt Cut/Gold Plate
Gull Wing/Soldered
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Class K SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
8 Pin DIP
Through Hole
1
None
8 Pin DIP
Through Hole
2
VCC, GND
16 Pin Flat Pack
Unformed Leads
4
VCC, GND
20 Pad LCCC
Surface Mount
2
None
HCPL-5200
HCPL-5201
HCPL-520K
Gold Plate
Option #200
Option #100
Option #300
HCPL-5230
HCPL-5231
HCPL-523K
Gold Plate
Option #200
Option #100
Option #300
HCPL-6250
HCPL-6251
HCPL-625K
Gold Plate
HCPL-6230
HCPL-6231
HCPL-623K
Soldered Pads
59628876801PX
8876801PC
8876801PA
8876801YC
8876801YA
8876801XA
59628876901PX
8876901PC
8876901PA
8876901YC
8876901YA
8876901XA
59628876903FX
8876903FC
596288769022X
59628876802KPX
8876802KPC
8876802KPA
8876802KYC
8876802KYA
8876802KXA
59628876904KPX
8876904KPC
8876904KPA
8876904KYC
8876904KYA
8876904KXA
59628876906KFX
8876906KFC
88769022A
59628876905K2X
8876905K2A
3
Functional Diagrams
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
VCC
VO
2
3
VE
4
GND
8
1
VCC
8
VO1
7
7
2
6
3
5
4
VO2
GND
6
5
15
16
1
1
20 Pad LCCC
Surface Mount
2 Channels
VCC2
2
VCC 15
3
VO1 14
4
VO2 13
5
VO3 12
2
6
VO4 11
3
7
GND 10
19
GND2
VO1
VCC1
12
10
GND1
7
9
8
13
VO2
20
8
Note: Multichannel DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 6. LCCC (leadless
ceramic chip carrier) package has isolated channels with separate VCC and ground connections.
7.24 (0.285)
6.99 (0.275)
Outline Drawings
2.29 (0.090)
MAX.
16 Pin Flat Pack, 4 Channels
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
MIN.
0.89 (0.035)
0.69 (0.027)
5.23
(0.206)
MAX.
0.31 (0.012)
0.23 (0.009)
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
8.13 (0.320)
MAX.
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
7.36 (0.290)
7.87 (0.310)
4
Leaded Device Marking
Agilent LOGO
Agilent P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
Leadless Device Marking
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
COUNTRY OF MFR.
Agilent FSCN*
Agilent LOGO
Agilent P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
*QUALIFIED PARTS ONLY
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Agilent FSCN*
*QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
100
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead
finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
5° MAX.
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
9.65 (0.380)
9.91 (0.390)
5
Absolute Maximum Ratings
Storage Temperature Range, TS .................................. -65°C to +150°C
Operating Temperature, TA ......................................... -55°C to +125°C
Case Temperature, TC ................................................................ +170°C
Junction Temperature, TJ .......................................................... +175°C
Lead Solder Temperature .............................................. 260°C for 10 s
Average Forward Curre, IF AVG (each channel) ............................. 8 mA
Peak Input Current, IF PK (each channel) ............................... 20 mA[1]
Reverse Input Voltage, VR (each channel) ....................................... 3 V
Supply Voltage ,VCC .............................................. 0.0 V min., 20 V max.
Average Output Current, IO (each channel) ................................. 15 mA
Output Voltage, VO (each channel) .................... –0.3 V min., 20 V max.
Package Power Dissipation, Pd (each channel) ......................... 200 mW
Single Channel Product Only
Tri-State Enable Voltage, VE ............................... –0.3 V min., 20 V max.
8 Pin Ceramic DIP Single Channel Schematic
ANODE
CATHODE
Note enable pin 6. An external 0.01 µF to 0.1 µF bypass capacitor is recommended
between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5200/01/0K, HCPL-6230/31/3K ................................ (∆), Class 1
HCPL-5230/31/3K, HCPL-6250/51/5K ............................ (Dot), Class 3
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input Current, High Level,
Each Channel
Input Voltage, Low Level,
Each Channel
Fan Out (TTL Load)
Each Channel
Symbol
VCC
IFH
Min.
4.5
2
Max.
20
8
Units
V
mA
VFL
0
0.8
V
N
Single Channel Product Only
High Level Enable Voltage
VEH
Low Level Enable Voltage
VEL
4
2.0
0
20
0.8
V
V
6
Electrical Characteristics
TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 20 V, 2 mA ≤ IF(ON) ≤ 8 mA, 0 V ≤ VF(OFF) ≤ 0.8 V, unless otherwise
specified.
Test Conditions
Group A[11]
Limit
Subgroups Min. Typ.* Max. Units Fig. Notes
Parameter
Sym.
Logic Low Output Voltage
VOL
IOL = 6.4 mA (4 TTL Loads)
1, 2, 3
VOH
IOH = -2.6 mA
(**VOH = VCC - 2.1 V)
1, 2, 3
Logic High Output Voltage
Output Leakage Current
IOHH
VO = 5.5 V
IF = 8 mA
VO = 20 V
VCC = 4.5 V
IOH = -0.32 mA
(VOUT > VCC)
Logic Low
Supply
Current
2.4
NA
VCC = 5.5 V VF = 0 V
V = 20 V VE = Don't Care
Single
Channel
0.5
CC
**
V
1, 3
2
2, 3
2
V
3.1
1, 2, 3
100
µA
2
500
1, 2, 3
4.5
6
5.3
7.5
9.0
12
10.6
15
14
24
ICCL
Dual
Channel
VCC = 5.5 V
VCC = 20 V
Quad
Channel
VCC = 5.5 V VF1 = VF2 =
VF3 = VF4 = 0 V
VCC = 20 V
Single
Channel
VCC = 5.5 V IF = 8 mA
VE = Don't Care
VCC = 20 V
Logic High
Supply
Current
Dual
Channel
mA
VF1 = VF2 = 0 V
17
30
2.9
4.5
3.3
6
5.8
9
6.6
12
9
18
11
24
1, 2, 3
ICCH
VCC = 5.5 V
VCC = 20 V
IF1 =
IF2 = 8 mA
VCC = 5.5 V IF1 = IF2 =
=
IV
VF3=
= VF4 = 8 mA
Quad
Channel
VCC = 20 V
F3
F3
mA
IF4 = 8 mA
Logic Low Short Circuit
Output Current
VO = VCC = 5.5 V
IOSL
20
VF = 0 V
VO = VCC = 20 V
Logic High Short Circuit
Output Current
VCC = 5.5 V
2, 3
35
IF = 8 mA
VO = GND
-10
IOSH
VCC = 20 V
VF
IF = 8 mA
1, 2, 3
1.0
Input Reverse
Breakdown Voltage
BVR
IR = 10 µA
1, 2, 3
3
Input-Output Insulation
Leakage Current
II-O
VI-O = 1500 Vdc, t = 5s
RH = 45%, TA = 25°C
Input Forward Voltage
mA
1, 2, 3
1, 2, 3
mA
2, 3
-25
1.3
1
1.8
1.0
V
4
2
V
2
µA
4, 5
Logic High Common Mode |CMH| IF = 2 mA, VCM = 50 VP-P
Transient Immunity
9, 10, 11
1000 10,000
V/µs
9
2, 6,
12
Logic Low Common Mode |CML| IF = 0 mA, VCM = 50 VP-P
Transient Immunity
9, 10, 11
1000 10,000
V/µs
9
2, 6,
12
Propagation Delay Time
to Logic Low
tPHL
9, 10, 11
173
350
ns
5,
6
2, 7
Propagation Delay Time
to Logic High
tPLH
9, 10, 11
118
350
ns
5,
6
2, 7
7
Electrical Characteristics Single Channel Product Only
TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 20 V, 2 mA ≤ IF (ON) ≤ 8 mA, 0 V ≤ VF(OFF) ≤ 0.8 V, 2.0 V
≤ VEH ≤ 20 V, 0 V ≤ VEL ≤ 0.8 V, unless otherwise specified.
Parameter
Sym.
High Impedance State
Output Current
IOZL
IOZH
Test Conditions
VO = 0.4 V
VEN = 2 V,
VF = 0 V
VO = 2.4 V
V EN = 2 V,
IF = 8 mA
VO = 5.5 V
Group A[11]
Subgroups
Limits
Min. Typ.* Max. Units
1, 2, 3
-20
µA
20
µA
1, 2, 3
100
VO = 20 V
VEH
1, 2, 3
Logic Low Enable
Voltage
VEL
1, 2, 3
2.0
VEN = 5.5 V
1, 2, 3
IEL
VEN = 0.4 V
0.8
V
20
µA
100
VEN = 20 V
Logic Low Enable
Current
V
VEN = 2.7 V
IEH
Notes
500
Logic High Enable
Voltage
Logic High Enable
Current
Fig.
0.004
1, 2, 3
250
-0.32
mA
*All typical values are at VCC = 5 V, TA = 25°C, IF(ON) = 5 mA unless otherwise specified.
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, IF(ON) = 5 mA unless otherwise specified.
Parameter
Input Current Hysteresis
Input Diode Temperature Coefficient
Resistance (Input-Output)
Capacitance (Input-Output)
Input Capacitance
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Symbol Typ.
IHYS
0.07
∆VF
––––
-1.25
∆TA
RI-O
1013
CI-O
2.0
CIN
20
tr
45
tf
10
Units
mA
Test Conditions
VCC = 5 V
mV/°C
IF = 8 mA
Ω
pF
pF
ns
ns
Fig.
3
Notes
2
2
VI-O = 500 Vdc
f = 1 MHz
VF = 0 V, f = 1 MHz
5, 7
5, 7
2, 8
2, 8
2, 10
2
2
8
Typical Characteristics (cont’d.)
All typical values are at TA = 25°C, VCC = 5 V, IF(ON) = 5 mA, unless otherwise specified.
Single Channel Product Only
Parameter
Symbol
Typ.
Units
tPZH
30
ns
8
Output Enable Time to Logic Low
tPZL
30
ns
8
Output Disable Time from Logic High
tPHZ
45
ns
8
Output Disable Time from Logic Low
tPLZ
55
ns
8
II-I
0.5
nA
RI-I
1013
Ω
Output Enable Time to Logic High
Test Conditions
Fig.
Notes
Dual and Quad Channel Products Only
Input-Input Insulation Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
CI-I
1.5
pF
RH = 45%, TA = 25°C,
V I-I = 500 V, t = 5 s
VI-I = 500 V
f = 1 MH
9
9
9
Notes:
1. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.
2. Each channel of a multichannel device.
3. Duration of output short circuit time not to exceed 10 ms.
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads
or terminals shorted together.
5. This is a momentary withstand test, not an operating condition.
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO
< 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
high state (V O > 2.0 V).
7. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge
of the output pulse. The t PLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V
point on the trailing edge of the output pulse.
8. Measured between each input pair shorted together and all output connections for that channel shorted together.
9. Measured between adjacent input pairs shorted together for each multichannel device.
10. Zero-bias capacitance measured between the LED anode and cathode.
11. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,
and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits
specified for all lots not specifically tested.
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
Figure 2. Typical Logic High Output
Current vs. Temperature.
9
Figure 3. Output Voltage vs. Forward
Input Current.
Figure 4. Typical Diode Input Forward
Characteristic.
VCC
PULSE GEN.
tr = tf = 5 ns
t = 100 kHz
10 % DUTY
CYCLE
OUTPUT VO
MONITORING
NODE
D.U.T.
VCC
IF
INPUT
MONITORING
NODE
Rf
D1
VO
VE
5V
D2
CL=
15 pF
GND
619 Ω
5K
D3
D4
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN CL.
Figure 5. Test Circuit for tPLH, tPHL, tr , and tf.
Figure 6. Typical Propagation Delay
vs. Temperature.
Figure 7. Typical Rise, Fall Time vs.
Temperature.
10
PULSE
GENERATOR
ZO = 50 Ω
tr = tf = 5 ns
CL= 15 pF INCLUDING PROBE
AND JIG CAPACITANCE.
+5 V
VCC
VO
D.U.T.
S1
VCC
IF
D2
CL
VE
D 1-4 ARE 1N916 OR 1N3064
619 Ω
D1
VO
GND
5 KΩ
D3
D4
INPUT VO
MONITORING
NODE
S2
Figure 8. Test Circuit for tPHZ , tPZH, tPLZ, and tPZL.
A
VCC
D.U.T.
B
OUTPUT VO
MONITORING
NODE
VCC
RIN
VO
0.1 µF
BYPASS
VE
VFF
GND
*SEE NOTE 6.
VCM
+
–
PULSE GEN.
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
VCC1
(+5 V)
VCC2
(4.5 TO 20 V)
665 Ω
D.U.T.
VCC
DATA
INPUT
RL
VO
CMOS
TTL OR
LSTTL
VCC2
1
VCC1
(+5 V)
750 Ω
D.U.T.
VE
VCC
GND
TOTEM
POLE
OUTPUT
GATE
DATA
OUTPUT
5V
10 V
15 V
20 V
RL
1.1 K
2.37 K
3.83 K
5.11 K
DATA
INPUT
2
Figure 10. LSTTL to CMOS Interface Circuit.
TTL OR
LSTTL
TOTEM
POLE
OUTPUT
GATE
GND
Figure 11. Recommended LED Drive Circuit.
11
VCC1
(+5 V)
619 Ω
D.U.T.
VCC
4.02 KΩ
DATA
INPUT
TTL OR
LSTTL
GND
OPEN
COLLECTOR
GATE
Figure 12. Series LED Drive with Open Collector Gate
(4.02 kΩ Resistor Shunts IOH from the LED).
VCC2
(+5 V)
DATA
OUTPUT
VCC1
(+5 V)
665 Ω
665 Ω
VCC
DATA
INPUT
TTL OR
LSTTL
DATA
INPUT
TOTEM
POLE
OUTPUT
GATE
UP TO 16 LSTTL
LOADS
OR 4 TTL LOADS
D.U.T.
0.1
µF
DATA
OUTPUT
TTL OR
LSTTL
GND
1
TOTEM
POLE
OUTPUT
GATE
UP TO 16 LSTTL
LOADS
OR 4 TTL LOADS
1
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
VCC + 20 V
D.U.T.*
VCC
IF
+
IO
–
VIN
1.90 V
100 Ω
VE
0.01 µF
1200 Ω
GND
CONDITIONS: IF = 8 mA
IO = -14 mA
TA = +125 °C
*ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 14. Single Channel Operating Circuit for Burn-in and Steady State Life Tests.
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent’s Hi-Rel Optocouplers are
in compliance with MIL-PRF38534 Classes H and K. Class H
and Class K devices are also in
compliance with DSCC drawings
5962-88768 and
5962-88769.
Testing consists of 100% screening and quality conformance
inspection to MIL-PRF-38534.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies, Inc.
Obsoletes 5967-6330E
5980-0280E (10/00)
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