LINER LTC6992IDCB6-1-TRPBF Timerblox voltage-controlled pulse width modulator (pwm) Datasheet

Electrical Specifications Subject to Change
LTC6992-1/-2/-3/-4
TimerBlox
Voltage-Controlled Pulse
Width Modulator (PWM)
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
Pulse Width Modulation (PWM) Controlled by
Simple 0V to 1V Analog Input
Four Available Options Define Duty Cycle Limits
– Minimum Duty Cycle at 0% or 5%
– Maximum Duty Cycle at 95% or 100%
Frequency Range: 3.81Hz to 1MHz
Single Resistor Programs Frequency with < 2.4%
Maximum Error
PWM Duty Cycle Error < 4.5% Maximum
Frequency Modulation (VCO) Capability
2.25V to 5.5V Single Supply Operation
115μA Supply Current at 100kHz
500μs Start-Up Time
CMOS Output Driver Sources/Sinks 20mA
–40°C to 125°C Operating Temperature Range
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
APPLICATIONS
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n
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LED Dimming Control
PWM Servo Loops
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
The LTC®6992 is a silicon oscillator with an easy-to-use
analog voltage-controlled pulse width modulation (PWM)
capability. The LTC6992 is part of the TimerBlox™ family
of versatile silicon timing devices.
A single resistor, RSET, programs the LTC6992’s internal master oscillator frequency. The output frequency
is determined by this master oscillator and an internal
frequency divider, NDIV, programmable to eight settings
from 1 to 16384.
fOUT =
1MHz 50kΩ
•
, N = 1,4,16 …16384
NDIV RSET DIV
Applying a voltage between 0V and 1V on the MOD pin sets
the duty cycle, according to the following formula:
Duty Cycle =
− 100mV
VMOD
1 V
− ≅ MOD
0.8 • VSET 8
800mV
The four versions differ in their minimum/maximum duty
cycle. Note that a minimum duty cycle limit of 0% or
maximum duty cycle limit of 100% allows oscillations to
stop at the extreme duty cycle settings.
DEVICE NAME
LTC6992-1
LTC6992-2
PWM DUTY
CYCLE RANGE
0% to 100%
5% to 95%
LTC6992-3
0% to 95%
LTC6992-4
5% to 100%
OUTPUT DUTY CYCLE LIMITS
MIN
MAX
GND
V+
GND
V+
TYPICAL APPLICATION
1MHz Pulse Width Modulator
ANALOG PWM
DUTY CYCLE
CONTROL
(0V TO 1V)
MOD
GND
MOD
0.5V/DIV
OUT
LTC6992
V+
V+
C1
0.1μF
SET
RSET
50k
DIV
OUT
1V/DIV
6992 TA01a
2μs/DIV
6992 TA01b
69921234p
1
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+) to GND .........…………………….6V
Maximum Voltage On Any Pin
.............................(GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6992C ................................................ 0°C to 70°C
LTC6992I .............................................–40°C to 85°C
LTC6992H .......................................... –40°C to 125°C
Specified Temperature Range (Note 3)
LTC6992C ................................................ 0°C to 70°C
LTC6992I .............................................–40°C to 85°C
LTC6992H .......................................... –40°C to 125°C
Junction Temperature .......................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
6 OUT
V+ 1
DIV 2
7
GND
SET 3
MOD 1
6 OUT
5 GND
GND 2
5 V+
4 MOD
SET 3
4 DIV
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W
EXPOSED PAD (PIN 7) IS GND, PCB CONNECTION IS OPTIONAL
TJMAX = 150°C, θJA = 230°C/W, θJC = 51°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6992CDCB6-1#PBF
LTC6992CDCB6-1#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC6992IDCB6-1#PBF
LTC6992IDCB6-1#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6992HDCB6-1#PBF
LTC6992HDCB6-1#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6992CS6-1#PBF
LTC6992CS6-1#TRPBF
XXXX
6-Lead Plastic TSOT-23
0°C to 70°C
LTC6992IS6-1#PBF
LTC6992IS6-1#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6992HS6-1#PBF
LTC6992HS6-1#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 125°C
LTC6992CDCB6-2#PBF
LTC6992CDCB6-2#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC6992IDCB6-2#PBF
LTC6992IDCB6-2#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6992HDCB6-2#PBF
LTC6992HDCB6-2#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6992CS6-2#PBF
LTC6992CS6-2#TRPBF
XXXX
6-Lead Plastic TSOT-23
0°C to 70°C
LTC6992IS6-2#PBF
LTC6992IS6-2#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6992HS6-2#PBF
LTC6992HS6-2#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 125°C
LTC6992CDCB6-3#PBF
LTC6992CDCB6-3#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC6992IDCB6-3#PBF
LTC6992IDCB6-3#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6992HDCB6-3#PBF
LTC6992HDCB6-3#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6992CS6-3#PBF
LTC6992CS6-3#TRPBF
XXXX
6-Lead Plastic TSOT-23
0°C to 70°C
LTC6992IS6-3#PBF
LTC6992IS6-3#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 85°C
69921234p
2
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6992HS6-3#PBF
LTC6992HS6-3#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 125°C
LTC6992CDCB6-4#PBF
LTC6992CDCB6-4#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC6992IDCB6-4#PBF
LTC6992IDCB6-4#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6992HDCB6-4#PBF
LTC6992HDCB6-4#TRPBF
XXXX
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6992CS6-4#PBF
LTC6992CS6-4#TRPBF
XXXX
6-Lead Plastic TSOT-23
0°C to 70°C
LTC6992IS6-4#PBF
LTC6992IS6-4#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6992HS6-4#PBF
LTC6992HS6-4#TRPBF
XXXX
6-Lead Plastic TSOT-23
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET,
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillation Frequency
fOUT
Output Frequency
ΔfOUT
Frequency Accuracy (Note 4)
ΔfOUT/ΔT
Frequency Drift Over Temperature
ΔfOUT/ΔV+
Frequency Drift Over Supply
Period Jitter (Note 11)
3.81
3.81Hz ≤ fOUT ≤ 1MHz
V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
±0.8
l
l
±0.005
l
l
0.25
0.08
Frequency Modulation Bandwidth
tS,FM
Frequency Change Settling Time
(Note 10)
Hz
±1.7
±2.4
%
%
%/°C
0.65
0.18
%/V
%/V
NDIV = 1
1.2
%P-P
NDIV = 4
0.4
0.07
%P-P
%RMS
NDIV = 16
0.15
0.022
%P-P
%RMS
TBD
ppm/√kHz
TBD
kHz
TBD
μs
Long-Term Stability of Output
Frequency (Note 9)
BWFM
1000000
tMASTER = tOUT/NDIV
Pulse Width Modulation
l
l
ΔD
PWM Duty Cycle Accuracy
VMOD = 0.2 • VSET to 0.8 • VSET
VMOD < 0.2 • VSET or VMOD > 0.8 • VSET
DMAX
Maximum Duty Cycle Limit
LTC6992-1/LTC6992-3, POL = 0, VMOD = 1V l
100
LTC6992-2/LTC6992-4, POL = 0, VMOD = 1V l
90.5
DMIN
Minimum Duty Cycle Limit
PWM Duty Cycle Bandwidth
tS,PWM
Duty Cycle Setting Time (Note 6)
tMASTER = tOUT/NDIV
1
±4.5
±4.9
%
%
%
95
LTC6992-1/LTC6992-4, POL = 0, VMOD = 0V l
LTC6992-2/LTC6992-3, POL = 0, VMOD = 0V l
BWPWM
±1.5
±2.0
5
99
%
0
%
9.5
%
TBD
kHz
TBD
μs
69921234p
3
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET,
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V+
IS
Operating Supply Voltage Range
l
Power-On Reset Voltage
l
Supply Current
2.25
5.5
V
1.95
V
RL = ∞, RSET = 50k,
NDIV = 1
V+ = 5.5V
l
365
450
μA
V+ = 2.25V
l
225
285
μA
RL = ∞, RSET = 50k,
NDIV = 4
V+ = 5.5V
l
350
420
μA
V+ = 2.25V
l
225
280
μA
RL = ∞, RSET = 50k,
NDIV ≥ 16
V+ = 5.5V
l
325
390
μA
V+ = 2.25V
l
215
265
μA
RL = ∞, RSET = 800k,
NDIV = 1 to 16, 384
V+ = 5.5V
l
120
170
μA
V+ = 2.25V
l
105
150
μA
1.00
1.03
Analog Inputs
VSET
Voltage at SET Pin
l
ΔVSET/ΔT
VSET Drift Over Temperature
l
RSET
Frequency-Setting Resistor
l
0.97
±75
50
MOD Pin Input Capacitance
VMOD,HI
VMOD Voltage for Maximum Duty
Cycle
LTC6992-1/LTC6992-4, POL = 0, D = 100%
LTC6992-2/LTC6992-3, POL = 0, D = 95%
l
0.90 • VSET
0.86 • VSET
VMOD,LO
VMOD Voltage for Minimum Duty
Cycle
LTC6992-1/LTC6992-3, POL = 0, D = 0%
LTC6992-2/LTC6992-4, POL = 0, D = 5%
l 0.064 • VSET
0.10 • VSET
0.14 • VSET
VDIV
DIV Pin Voltage
l
DIV Pin Valid Code Range (Note 5)
ΔVDIV/ΔV+
800
kΩ
±10
nA
0.936•VSET
V
V
2.5
l
MOD Pin Input Current
Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
DIV Pin Input Current
V
μV/°C
pF
V
V
V+
V
l
±1.5
%
l
±10nA
0
Digital Output
IOUT(MAX)
VOH
VOL
l
Output Output Current
High Level Output Voltage
Low Level Output Voltage
±20
mA
5.45
4.84
5.48
5.15
V
V
l
l
3.24
2.75
3.27
2.99
V
V
IOUT = –1mA
IOUT = -8mA
l
l
2.17
1.58
2.21
1.88
V
V
V+ = 5.5V
IOUT = 1mA
IOUT = 16mA
l
l
0.02
0.26
0.04
0.54
V
V
V+ = 3.3V
IOUT = 1mA
IOUT = 10mA
l
l
0.03
0.22
0.05
0.46
V
V
V+ = 2.25V
IOUT = 1mA
IOUT = 8mA
l
l
0.03
0.26
0.07
0.54
V
V
V+ = 5.5V
IOUT = –1mA
IOUT = –16mA
l
l
V+ = 3.3V
IOUT = –1mA
IOUT = –10mA
V+ = 2.25V
69921234p
4
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET,
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tr
Output Rise Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
ns
ns
tf
Output Fall Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6992C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6992C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6992C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6992I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6992H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: Duty cycle setting time is the is the amount of time required for
the output to settle within ±1% of the final duty cycle after a ±10% change
in the setting (±80mV step in VMOD).
MIN
TYP
MAX
UNITS
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Long term drift on silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long term drift is specified
as ppm/√kHr due to the typically non-linear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 888ppm at 300ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 30ppm/√kHr for a 300ppm/√kHr device.
Note 10: Frequency change settling time is the amount of time required
for the output to settle within ±1% of the final frequency after a 0.5x or 2x
change in ISET.
Note 11: Jitter is the ratio of the peak-to-peak deviation of the period to
the mean of the period. This specification is based on characterization and
is not 100% tested.
69921234p
5
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
2
2
RSET = 50k
3 PARTS
2
RSET = 200k
3 PARTS
0
–1
–1
–2
–2
75
0
25
50
TEMPERATURE (°C)
–25
100
–1
–2
–3
–50
125
75
0
25
50
TEMPERATURE (°C)
–25
100
GUARANTEED MIN OVER TEMPERATURE
–3
–50
125
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
GUARANTEED MAX OVER TEMPERATURE
0.3
200
DRIFT (%)
1
–1
NUMBER OF UNITS
0.2
RSET = 50k
0.1
0
–0.1
–0.2
RSET = 200k
RSET = 800k
–0.3
–2
GUARANTEED MIN OVER TEMPERATURE
100
200
RSET (k)
400
2
150
100
0
0.98
6
4
5
3
SUPPLY VOLTAGE (V)
VSET Drift vs ISET
VSET Drift vs Supply
0.8
0.8
1.015
0.6
0.6
0.4
0.4
0
–0.2
–0.6
–0.6
–0.8
REFERENCED TO ISET = 10μA
–1.0
0
5
10
ISET (μA)
15
20
6992 G07
1.005
0.2
–0.4
3 PARTS
1.010
VSET (V)
DRIFT (mV)
1.020
–0.4
1.02
1.012
VSET vs Temperature
1.0
0
0.996
1.004
VSET (V)
6992 G06
1.0
–0.2
0.988
6992 G05
6992 G04
0.2
2 LOTS
DFN AND SOT-23
1274 UNITS
REFERENCED TO V+ = 4.5V
–0.5
800
125
50
–0.4
50
100
Typical VSET Distribution
250
0.4
3 PARTS
–3
75
0
25
50
TEMPERATURE (°C)
6992 G03
0.5
3
0
–25
6992 G02
6992 G01
2
0
GUARANTEED MIN OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
–3
–50
RSET = 800k
3 PARTS
1
ERROR (%)
ERROR (%)
ERROR (%)
0
ERROR (%)
GUARANTEED MAX OVER TEMPERATURE
1
1
VSET (mV)
Frequency Error vs Temperature
3
3
1.000
0.995
0.990
0.985
–0.8
REFERENCED TO V+ = 4V
–1.0
2
3
4
SUPPLY (V)
6
5
6992 G08
0.980
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G09
69921234p
6
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
NDIV = 1 Duty Cycle Error vs RSET
4
3
NDIV = 1 Duty Cycle Error vs RSET
ERROR (%)
ERROR (%)
5
2
2
VMOD/VSET = 0.5 (50%)
4 DIVCODE = 0
3 PARTS
3
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 0
3 PARTS
2
1
0
–1
VMOD/VSET = 0.8 (87.5%)
4 DIVCODE = 0
3 PARTS
3
1
0
–1
1
0
–1
–2
–2
–2
–3
–3
–3
–4
–4
–4
–5
–5
50
100
200
RSET (k)
400
50
800
100
200
RSET (k)
400
–5
800
50
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
5
2
2
2
VMOD/VSET = 0.2 (12.5%)
4 DIVCODE = 4
3 PARTS
3
ERROR (%)
ERROR (%)
1
0
–1
1
0
–1
–2
–2
–2
–3
–3
–3
–4
–4
–4
–5
–5
100
200
RSET (k)
400
800
–5
50
100
200
RSET (k)
400
6992 G15
94
93
ERROR (%)
92
8
LTC6992-2/LTC6992-4
VMOD = VSET
LTC6992-2/LTC6992-3
VMOD = VSET
92
8
LTC6992-2/LTC6992-4
VMOD = VSET
7
6
5
5
4
4
3
3
50
100
800
DIVCODE = 4
96 3 PARTS
95
LTC6992-2/LTC6992-3
VMOD = VSET
6
400
NDIV > 1 Duty Cycle Error vs RSET
DIVCODE = 0
96 3 PARTS
95
7
200
RSET (k)
97
97
93
100
6992 G14
NDIV = 1 Duty Cycle Clamps
vs RSET
94
50
800
6992 G13
ERROR (%)
50
800
VMOD/VSET = 0.8 (87.5%)
4 DIVCODE = 4
3 PARTS
3
VMOD/VSET = 0.5 (50%)
4 DIVCODE = 4
3 PARTS
3
–1
400
NDIV > 1 Duty Cycle Error vs RSET
5
0
200
RSET (k)
6992 G12
5
1
100
6992 G11
6992 G10
ERROR (%)
NDIV = 1 Duty Cycle Error vs RSET
5
ERROR (%)
5
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
200
RSET (k)
400
800
6992 G16
50
100
200
RSET (k)
400
800
6992 G17
69921234p
7
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
NDIV = 1 Duty Cycle Error
vs Temperature
NDIV = 1 Duty Cycle Error
vs Temperature
5
5
ERROR (%)
2
1
0
–1
0
–1
–2
–3
–25
75
0
25
50
TEMPERATURE (°C)
100
–25
100
75
0
25
50
TEMPERATURE (°C)
NDIV > 1 Duty Cycle Error
vs Temperature
5
4
4
GUARANTEED MAX
–3
GUARANTEED MIN
100
125
GUARANTEED MIN
–5
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
–4
125
–5
–50
GUARANTEED MIN
–25
75
0
25
50
TEMPERATURE (°C)
6992 G22
100
125
6992 G23
NDIV > 1 Duty Cycle Clamps
vs Temperature
97
DIVCODE = 0
96 3 PARTS
95
DIVCODE = 4
96 3 PARTS
95
92
8
LTC6992-2/LTC6992-4
VMOD = GND
5
94
DUTY CYCLE (%)
LTC6992-2/LTC6992-3
VMOD = VSET
6
0
–1
–3
–4
97
7
1
–2
NDIV = 1 Duty Cycle Clamps
vs Temperature
93
GUARANTEED MAX
VMOD/VSET = 0.8 (87.5%)
DIVCODE = 4
2 3 PARTS
6992 G21
94
125
3
–1
–3
ERROR (%)
4
0
–2
100
5
GUARANTEED MAX
1
–2
75
0
25
50
TEMPERATURE (°C)
75
0
25
50
TEMPERATURE (°C)
NDIV > 1 Duty Cycle Error
vs Temperature
ERROR (%)
ERROR (%)
ERROR (%)
–1
–25
6992 G20
3
0
–25
125
VMOD/VSET = 0.5 (50%)
DIVCODE = 4
2 3 PARTS
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 4
2 3 PARTS
3
1
GUARANTEED MIN
–5
–50
NDIV > 1 Duty Cycle Error
vs Temperature
5
–5
–50
–4
6992 G19
6992 G18
–4
0
–1
–3
GUARANTEED MIN
–5
–50
125
1
–2
–4
GUARANTEED MIN
GUARANTEED MAX
V
/V
= 0.8 (87.5%)
3 MOD SET
DIVCODE = 0
2 3 PARTS
1
–3
–5
–50
4
V
/V
= 0.5 (50%)
3 MOD SET
DIVCODE = 0
2 3 PARTS
–2
–4
GUARANTEED MAX
ERROR (%)
3
5
4
GUARANTEED MAX
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 0
3 PARTS
ERROR (%)
4
NDIV = 1 Duty Cycle Error
vs Temperature
LTC6992-2/LTC6992-3
VMOD = VSET
93
92
8
LTC6992-2/LTC6992-4
VMOD = GND
7
6
5
4
4
3
–50
3
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G24
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G25
69921234p
8
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Duty Cycle Error vs DIVCODE
Duty Cycle Error vs DIVCODE
5
VMOD /VSET = 0.5 (50%)
4 3 PARTS
VMOD /VSET = 0.8 (87.5%)
4 3 PARTS
3
2
2
1
0
–1
ERROR (%)
3
2
ERROR (%)
1
0
–1
1
0
–1
–2
–2
–2
–3
–3
–3
–4
–4
–4
–5
–5
–5
4
2
12
10
6
8
DIVCODE
14
0
4
2
12
10
6
8
DIVCODE
6992 G26
0
NDIV = 1 Duty Cycle vs VMOD/ VSET
NDIV > 1 Duty Cycle vs VMOD/ VSET
DIVCODE = 4
90 3 PARTS
LTC6992-1/
LTC6992-4
NDIV > 1 Duty Cycle vs VMOD/ VSET
LTC6992-1/
LTC6992-4
50
40
LTC6992-2/
LTC6992-4
30
60
50
40
20
10
0.4
0.6
VMOD/VSET (V/V)
0.2
50
40
0.4
0.6
VMOD/VSET (V/V)
0.2
1
0.8
NDIV = 1 Duty Cycle Error vs Ideal
6992 G31
NDIV > 1 Duty Cycle Error vs Ideal
NDIV > 1 Duty Cycle Error vs Ideal
5
5
5
3
3
3
2
2
2
0
PART A
ERROR (%)
PART C
PART B
–1
DIVCODE = 11
4 3 PARTS
DIVCODE = 4
4 3 PARTS
DIVCODE = 0
4 3 PARTS
1
PART C
PART B
0
–1
0
–2
–2
–3
–3
–4
–4
–4
PART A
–5
–5
75
25
50
IDEAL DUTY CYCLE (%)
100
6992 G32
PART B
–1
–3
0
PART A
PART C
1
–2
–5
0
1
0.8
6992 G30
6992 G29
1
LTC6992-2/
LTC6992-3
30
LTC6992-1/
10 DIVCODE = 11
LTC6992-4
3 PARTS
0
0.4
0.6
0
0.2
VMOD/VSET (V/V)
LTC6992-1/LTC6992-3
0
1
0.8
70 LTC6992-2/
LTC6992-4
60
20
0
0
0
LTC6992-2/
LTC6992-4
30
10
LTC6992-1/LTC6992-3
80
LTC6992-2/
LTC6992-3
70
20
LTC6992-1/LTC6992-3
90
DUTY CYCLE (%)
DUTY CYCLE (%)
60
14
100
80
80
LTC6992-2/
LTC6992-3
12
10
6
8
DIVCODE
4
6992 G28
100
70
2
6992 G27
100
DIVCODE = 0
90 3 PARTS
14
ERROR (%)
ERROR (%)
5
3
0
DUTY CYCLE (%)
Duty Cycle Error vs DIVCODE
5
VMOD / VSET = 0.2 (12.5%)
4 3 PARTS
ERROR (%)
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
75
25
50
IDEAL DUTY CYCLE (%)
100
6992 G33
0
75
25
50
IDEAL DUTY CYCLE (%)
100
6992 G34
69921234p
9
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
Linearity Near 100% Duty Cycle
Linearity Near 95% Duty Cycle
100
100
97
97
96
96
95
94
93
92
95
94
93
92
91
91
90
90
89
89
88
0.804
88
0.804
0.9
0.868
0.836
VMOD/VSET (V/V)
70
DUTY CYCLE (%)
DUTY CYCLE (%)
DUTY CYCLE (%)
DIVCODE = 4
71 3 PARTS
DIVCODE = 4
99 LTC6992-2/LTC6992-3
98 3 PARTS
DIVCODE = 4
99 LTC6992-1/LTC6992-4
98 3 PARTS
Linearity Near 0% Duty Cycle
9
9
8
8
6
5
4
1
1
0
0.084
0
0.084
0.18
0.3
0.2
0.2
–0.1
VMOD/VSET = 0.8
VMOD/VSET = 0.2
VMOD/VSET = 0.5
VMOD/VSET = 0.2
0.1
95% CLAMP
0
–0.1
VMOD/VSET = 0.5
VMOD/VSET = 0.8
0.388
LTC6992-2
2
3
4
SUPPLY (V)
5
300
RSET = 50k, ÷1
250
RSET = 50k, ÷16
200
RSET = 100k, ÷4
150
100
RSET = 800k, ÷1
50
REFERENCED TO V+ = 4V
–0.5
6992 G41
0.372
Supply Current vs VMOD
400
5% CLAMP
–0.4
6
0.34
0.356
VMOD/VSET (V/V)
350
–0.3
REFERENCED TO V+ = 4V
0.324
6992 G40
DIVCODE = 4
–0.2
5
29
26
0.308
0.18
0.116
0.148
VMOD/VSET (V/V)
POWER SUPPLY CURRENT (μA)
0.3
DRIFT (%)
DRIFT (%)
0.4
4
SUPPLY (V)
30
27
0.5
DIVCODE = 0
3
31
NDIV > 1 Duty Cycle Drift
vs Supply
0.4
2
32
6992 G39
Duty Cycle Drift vs Supply
–0.5
33
28
6992 G38
–0.4
6992 G37
34
4
2
0.676
0.66
DIVCODE = 4
35 3 PARTS
5
2
0
0.628
0.644
VMOD/VSET (V/V)
Linearity Near 31% Duty Cycle
6
3
95% CLAMP
0.612
36
7
3
–0.3
65
62
0.596
0.9
0.868
0.836
VMOD/VSET (V/V)
DUTY CYCLE (%)
7
–0.2
66
63
DIVCODE = 4
11 LTC6992-2/LTC6992-4
10 3 PARTS
DUTY CYCLE (%)
DUTY CYCLE (%)
DIVCODE = 4
11 LTC6992-1/LTC6992-3
10 3 PARTS
0.1
67
Linearity Near 5% Duty Cycle
12
5% CLAMP
68
6992 G36
12
0.116
0.148
VMOD/VSET (V/V)
69
64
6992 G35
0.5
Linearity Near 67% Duty Cycle
72
6
6992 G42
0
0
0.2
0.4
0.6
VMOD (V)
0.8
1
6992 G43
69921234p
10
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
Supply Current vs Supply Voltage
LTC6992-2
RSET = 50k, ÷1
350
Jitter vs Frequency
RSET = 50k, ÷4
300
RSET = 50k, ÷16
250
200
RSET = 100k, ÷1
150
100
2.0
RSET = 800k, ÷1
PEAK-TO-PEAK PERIOD
1.8 DEVIATION MEASURED
OVER 30s INTERVALS
1.6
VMOD/VSET = 0.5
1.4
5.0V, RSET = 50k, ÷1
350
POWER SUPPLY CURRENT (μA)
POWER SUPPLY CURRENT (μA)
Supply Current vs Temperature
400
5.0V, RSET = 50k, ÷16
300
JITTER (%P-P)
400
2.5V, RSET = 50k, ÷1
250
200
150
5.0V, RSET = 800k, ÷1
100
0
2
3
2.5V, RSET = 800k, ÷1
100
75
0
25
50
TEMPERATURE (°C)
–25
POWER SUPPLY CURRENT (μA)
÷4
300
÷16,384
250
200
150
÷1
100
V+ = 2.5V
300
250
÷4
÷16,384
200
150
÷1
100
50
0.01
100
10
0.1
1
FREQUENCY (kHz)
Output Resistance
vs Supply Voltage
0
0.001
1000
10
0.1
1
FREQUENCY (kHz)
0.01
3.0
1000
2.5
OUTPUT SOURCING CURRENT
25
20
OUTPUT SINKING CURRENT
10
SET PIN SHORTED TO GND
800
2.0
tRISE
ISET (μA)
RISE/FALL TIME (ns)
35
1000
Typical ISET Current Limit vs V+
CLOAD = 5pF
45
40
100
6992 G48
Rise and Fall Time
vs Supply Voltage
50
OUTPUT RESISTANCE (Ω)
1000
6992 G46
6992 G47
15
100
350
50
30
10
1
FREQUENCY (kHz)
0.1
Supply Current vs Frequency, 2.5V
400
V+ = 5V
350
POWER SUPPLY CURRENT (μA)
0
0.01
125
÷16
÷64
6992 G45
Supply Current vs Frequency, 5V
0
0.001
÷4, V+ = 5V
÷4, V+ = 2.5V
0.4
6992 G44
400
0.8
0.2
0
–50
6
4
5
SUPPLY VOLTAGE (V)
÷1, V+ = 2.5V
1.0
0.6
50
50
1.2
÷1, V+ = 5V
1.5
tFALL
600
400
1.0
200
0.5
5
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
6992 G50
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
6992 G51
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
6992 G52
69921234p
11
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Typical Start-Up, POL = 0
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical Start-Up, POL = 1
V+
1V/DIV
V+
1V/DIV
OUT
1V/DIV
OUT
1V/DIV
500μs
100μs/DIV
V+ = 2.5V
DIVCODE = 3 (÷64)
RSET = 50k
VMOD = 0.3V (~25% DUTY CYCLE)
PIN FUNCTIONS
6992 G53
500μs
6992 G54
100μs/DIV
V+ = 2.5V
DIVCODE = 12 (÷64, POL = 1)
RSET = 50k
VMOD = 0.2V (~87.5% DUTY CYCLE)
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply must be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. A V+ referenced A/D converter monitors the DIV
pin voltage (VDIV) to determine a 4-bit result (DIVCODE).
VDIV may be generated by a resistor divider between V+
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit the
capacitance on the DIV pin to less than 100pF so that VDIV
settles quickly. The MSB of DIVCODE (POL) determines
if the PWM signal is inverted before driving the output.
Setting POL = 1 results in a negative transfer function
(duty cycle decreasing as VMOD increases).
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current
range is 1.25μA to 20μA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
V+
MOD
OUT
LTC6992
GND
SET
RSET
V+
V+
C1
0.1μF
R1
DIV
6992 PF
R2
69921234p
12
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PIN FUNCTIONS
(DCB/S6)
MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The
voltage on the MOD pin controls the output duty cycle. The
linear control range is between 0.1 • VSET and 0.9 • VSET
(approximately 100mV to 900mV). Beyond those limits the
output will either clamp at 5% or 95%, or stop oscillating
(0% or 100% duty cycle), depending on the version.
BLOCK DIAGRAM
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
30Ω. The duty cycle is determined by the voltage on the
MOD pin. When driving an LED or other low-impedance
load a series output resistor should be used to limit
source/sink current to 20mA.
(S6 Package Pin Numbers Shown)
V+
5
R1 DIV
POL
4
4-BIT A/D
CONVERTER
DIGITAL
FILTER
R2
OUTPUT
POLARITY
MASTER OSCILLATOR
ISET
VSET
fOSC = 1MHz • 50kΩ •
PULSE WIDTH MODULATOR
MCLK
PROGRAMMABLE DIVIDER
÷1, 4, 16, 64, 256, 1024, 4096, 16384
DUTY CYCLE =
VMOD(LIM) – 0.1•VSET
tON
0.8•VSET
OUT
6
tOUT
DISABLE OUTPUT
UNTIL SETTLED
HALT OSCILLATOR
IF ISET < 500nA
D=
VMOD(LIM)
+
–
VSET = 1V
3
ISET
POR
+
–
VREF
1V
2
SET
GND
tON
tOFF
VOLTAGE LIMITER
VMOD
1
MOD
6992 BD
RSET
69921234p
13
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
The LTC6992 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
I
1
fMASTER =
= 1MHz • 50k • SET
tMASTER
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
1
1MHz • 50k
fMASTER =
=
tMASTER
RSET
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit
A/D converter that monitors the DIV pin voltage (VDIV) to
determine the DIVCODE value. DIVCODE programs two
settings on the LTC6992:
1. DIVCODE determines the output frequency divider
setting, NDIV.
2. DIVCODE determines the output polarity, via the POL
bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
2.25V TO 5.5V
V+
From this equation it is clear that VSET drift will not affect
the output frequency when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and the
inherent frequency accuracy ΔfOUT of the LTC6992.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25μA and 20μA).
LTC6992
R1
DIV
R2
GND
6992 F01
Figure 1. Simple Technique for Setting DIVCODE
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio NDIV is set by a resistor divider attached
to the DIV pin.
1
1MHz • 50k ISET
fOUT =
=
•
tOUT
NDIV
VSET
With RSET in place of VSET/ISET the equation reduces to:
fOUT =
1
tOUT
=
1MHz • 50k
NDIV • RSET
69921234p
14
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Table 1. DIVCODE Programming
DIVCODE
POL
NDIV
RECOMMENDED fOUT
R1 (kΩ)
R2 (kΩ)
VDIV /V+
0
0
1
62.5kHz to 1MHz
Open
Short
≤0.03125 ±0.015
1
0
4
15.63kHz to 250kHz
976
102
0.09375 ±0.015
2
0
16
3.906kHz to 62.5kHz
976
182
0.15625 ±0.015
3
0
64
976.6Hz to 15.63kHz
1000
280
0.21875 ±0.015
4
0
256
244.1Hz to 3.906kHz
1000
392
0.28125 ±0.015
5
0
1024
61.04Hz to 976.6Hz
1000
523
0.34375 ±0.015
6
0
4096
15.26Hz to 244.1Hz
1000
681
0.40625 ±0.015
7
0
16384
3.815Hz to 61.04Hz
1000
887
0.46875 ±0.015
8
1
16384
3.815Hz to 61.04Hz
887
1000
0.53125 ±0.015
9
1
4096
15.26Hz to 244.1Hz
681
1000
0.59375 ±0.015
10
1
1024
61.04Hz to 976.6Hz
523
1000
0.65625 ±0.015
11
1
256
244.1Hz to 3.906kHz
392
1000
0.71875 ±0.015
12
1
64
976.6Hz to 15.63kHz
280
1000
0.78125 ±0.015
13
1
16
3.906kHz to 62.5kHz
182
976
0.84375 ±0.015
14
1
4
15.63kHz to 250kHz
102
976
0.90625 ±0.015
15
1
1
62.5kHz to 1MHz
Short
Open
≥0.96875 ±0.015
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects)
Figure 2 illustrates the information in Table 1, showing that
NDIV is symmetric around the DIVCODE midpoint.
If the voltage is generated by other means (i.e. the output
of a DAC) it must track the V+ supply voltage. The last
POL BIT = 0
POL BIT = 1
15
0
100
fOUT (kHz)
DIVCODE + 0.5
±1.5%
16
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
2. The driving impedance (R1||R2) does not exceed
500kΩ.
1000
=
1
14
2
10
13
3
1
12
11
4
10
5
0.1
7
0.01
0.001
9
6
0V
8
0.5•V+
V+
INCREASING VDIV
6992 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
69921234p
15
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Pulse Width (Duty Cycle) Modulation
Output Polarity (POL Bit)
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle
is proportional to the voltage applied to the MOD pin,
VMOD.
VMOD
1
Duty Cycle = D =
−
0.8 • VSET 8
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as VMOD increases.
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
duty cycle as VMOD increases.
The PWM duty cycle accuracy ΔD specifies that the above
equation is valid to within ±4.5% for VMOD between 0.2 •
VSET and 0.8 • VSET (12.5% to 87.5% duty cycle).
POL = 0
D•tOUT
VMOD − 100mV
800mV
The VMOD control range is approximately 0.1V to 0.9V.
Driving VMOD beyond that range (towards GND or V+) will
have no further affect on the duty cycle.
Duty Cycle Limits
VMOD
0.8 • VSET
1
8
OUT
Since VSET = 1V ±30mV, the duty cycle equation may be
approximated by the following equation.
Duty Cycle = D ≅
D
tOUT
POL = 1
D•tOUT
¥ VMOD
D1 ¦
§ 0.8 • VSET
1´
8 µ¶
OUT
tOUT
6992 F03
Figure 3. POL Bit Functionality
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%, meaning the output can stop
oscillating and rest at GND or V+.
The LTC6992-2 will never stop oscillating, regardless of
the VMOD level. Internal clamping circuits limit its duty
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its VMOD control range is 0.14 • VSET to 0.86 •
VSET (approximately 0.14V to 0.86V).
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
69921234p
16
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
POL = 1 forces a simple logic inversion, so it changes the
duty cycle range of the LTC6992-3 (making it 100% to 5%)
and LTC6992-4 (making it 95% to 0%). These transfer
functions are detailed in Figure 4.
100
Table 2. Duty Cycle Ranges
DUTY CYCLE RANGE vs VMOD = 0V → 1V
PART NUMBER
POL = 0
POL = 1
LTC6992-1
0% to 100%
100% to 0%
LTC6992-2
5% to 95%
95% to 5%
LTC6992-3
0% to 95%
100% to 5%
LTC6992-4
5% to 100%
95% to 0%
100
VMOD /VSET = 0.1
90
90
70
POL = 0
POL = 1
60
50
40
30
20
70
50
40
30
0
VMOD /VSET = 0.86
10
VMOD /VSET = 0.9
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
0
1
0
6992 F04a
1
LTC6992-2
100
100
90
90
VMOD /VSET = 0.1
VMOD /VSET = 0.14
80
80
70
POL = 0
POL = 1
60
DUTY CYCLE (%)
DUTY CYCLE (%)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
6992 F04b
LTC6992-1
50
40
30
70
POL = 1
60
POL = 0
50
40
30
20
20
VMOD /VSET = 0.86
10
0
POL = 0
POL = 1
60
20
10
0
VMOD /VSET = 0.14
80
DUTY CYCLE (%)
DUTY CYCLE (%)
80
0
0
VMOD /VSET = 0.9
10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
6992 F02d
6992 F02c
LTC6992-3
1
LTC6992-4
Figure 4. PWM Transfer Functions for All LTC6992 Family Parts
69921234p
17
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Changing DIVCODE After Start-Up
Start-Up Time
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
When power is first applied to the LTC6992 the power-on
reset (POR) circuit will initiate the start-up time, tSTART.
The OUT pin is held low during this time. The typical value
for tSTART ranges from 0.5ms to 8ms depending on the
master oscillator frequency (independent of NDIV):
tDIVCODE = 16 • (ΔDIVCODE + 6) • tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
A digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
tSTART(TYP) = 500 • tMASTER
The output will begin oscillating after tSTART. If POL = 0
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of tOUT.
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V+. Less than 100pF will not affect performance.
V+
DIV
STABLE VDIV
tDIVCODE
tSTART
OUT
6992 F06
1ST PULSE WIDTH MAY BE INACCURATE
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Start-Up Timing Diagram
69921234p
18
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Basic Operation
The simplest and most accurate method to program the
LTC6992 is to use a single resistor, RSET, between the
SET and GND pins. The design procedure is a four step
process. After choosing the POL bit setting and proper
LTC6992 version, select the NDIV value and then calculate
the value for the RSET resistor.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
Step 1: Selecting the POL Bit Setting
Most applications will use POL = 0, resulting in a positive
transfer function. However, some applications may require a
negative transfer function, where increasing VMOD reduces
the output duty cycle. For example, if the LTC6992 is used
in a feedback loop, POL = 1 may be required to achieve
negative feedback.
1MHz • 50k
NDIV • fOUT
(1b)
Select the standard resistor value closest to the calculated
value.
Example: Design a PWM circuit that satisfies the following
requirements:
• fOUT = 20kHz
Step 2: Selecting the LTC6992 Version
• Positive VMOD to duty cycle response
The difference between the LTC6992 versions is observed
at the endpoints of the duty cycle control range. Applications that require the output never stop oscillating should
use the LTC6992-2. If it is better to allow the output to
rest at GND or V+ (0% or 100% duty cycle, respectively),
select the LTC6992-1.
• Output can reach 100% duty cycle, but not 0%
The LTC6992-3 and LTC6992-4 clamp the duty cycle at
only one end of the control range, allowing the output to
stop oscillating at the other extreme. If POL = 1 the clamp
will swap from low duty cycle to high, or vice-versa. Refer
to Table 2 and Figure 4 for assistance in selecting the
proper version.
• Minimum power consumption
Step 1: Selecting the POL Bit Setting
For positive transfer function (duty cycle increases with
VMOD), choose POL = 0.
Step 2: Selecting the LTC6992 Version
To limit the minimum duty cycle, but allow the maximum
duty cycle to reach 100%, choose LTC6992-4. (Note that
if POL = 1 the LTC6992-3 would be the correct choice.)
Step 3: Selecting the NDIV Frequency Divider Value
Step 3: Selecting the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given output frequency, NDIV should be
selected to be within the following range.
Choose an NDIV value that meets the requirements of
Equation (1a).
1MHz
62.5kHz
≤ NDIV ≤
fOUT
fOUT
(1a)
To minimize supply current, choose the lowest NDIV value
(generally recommended). For faster start-up or decreased
jitter, choose a higher NDIV setting. Alternatively, use Table 1
as a guide to select the best NDIV value for the given application.
3.125 ≤ NDIV ≤ 50
Potential settings for NDIV include 4 and 16. NDIV = 4 is
the best choice, as it minimizes supply current by using a large RSET resistor. POL = 0 and NDIV = 4 requires
DIVCODE = 1. Using Table 1, choose the R1 and R2 values
to program DIVCODE = 1.
69921234p
19
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Calculate the correct value for RSET using Equation (1b).
RSET =
1MHz • 50k
= 625k
4 • 20kHz
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 7.
VMOD
MOD
OUT
LTC6992-4
GND
V+
RSET
625k
DIV
6992 F07
100
90
ΔVSET = –30mV
80
70
60
ΔVSET = 0mV
50
ΔVSET = 30mV
40
30
20
2.25V TO 5.5V
R1
976k
SET
Some applications can eliminate ΔVSET sensitivity by
making VMOD proportional to VSET. For example, Figure 9
shows a simple circuit for generating an arbitrary duty
cycle. The equation for duty cycle does not depend on
VSET at all.
DUTY CYCLE (%)
Step 4: Select RSET
10
0
0
0.2
0.6
0.4
VMOD (V)
0.8
6992 F08
DIVCODE = 1
R2
102k
Figure 7. 20kHz PWM Oscillator
Figure 8. Duty Cycle Variation Due to ΔVSET
MOD
OUT
LTC6992-X
Duty Cycle Sensitivity to ΔVSET
The output duty cycle is proportional to the ratio of VMOD/
VSET. Since VSET can vary up to ±30mV from 1V it can
effectively gain or attenuate VMOD, as shown below when
ΔVSET is added to the equation.
VMOD
1
D=
−
0.8 • ( VSET + ΔVSET ) 8
The simplifying assumption of ΔVSET = 0V creates the potential for additional duty cycle error, which increases with
VMOD, reaching a maximum of 3.4% if ΔVSET = –30mV.
V
ΔV
1 ⎞ ΔV
⎛
ΔD ≅ MOD • SET ≅ − ⎜ Dideal + ⎟ • SET
⎝
800mV VSET
8 ⎠ VSET
Figure 8 demonstrates the worst-case impact of this variation (if VSET is at its 0.97V or 1.03V limits).
This error is in addition to the inherent PWM duty cycle
accuracy spec ΔD (±4.5%), so care should be taken if accuracy at high duty cycles (VMOD near 0.9V) is critical.
1
GND
V+
SET
DIV
2.25V TO 5.5V
R1
6992 F09
RSET1
RSET2
D
RSET2
5
•
4 RSET1 RSET2
R2
1
8
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
ISET Extremes (Master Oscillator Frequency Extremes)
Pushing ISET outside of the recommended 1.25μA to 20μA
range forces the master oscillator to operate outside of the
62.5kHz to 1MHz range in which it is most accurate.
The oscillator will still function with reduced accuracy
for ISET < 1.25μA. At approximately 500nA, the oscillator
output will be frozen in its current state. The output could
halt in a high or low state. This avoids introducing short
pulses while frequency modulating a very low frequency
output.
69921234p
20
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
(TBD • tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 11.
Frequency Modulation and Settling Time
Pulse Width Modulation Bandwidth and Settling Time
The LTC6992 will respond to changes in VMOD up to a –3dB
bandwidth of TBD (see Figure 10). This makes it easy to
stabilize a feedback loop around the LTC6992, since it
does not introduce a low frequency pole.
Duty cycle settling time depends on the master oscillator
frequency. Following a ±100mV step change in VMOD, the
duty cycle takes approximately TBD master clock cycles
In addition to pulse-width modulation, the LTC6992 can
be frequency modulated by varying ISET. The LTC6992
will respond to changes in ISET up to a –3dB bandwidth
of TBD • fOUT (see Figure 12).
Following a 2x or 0.5x step change in ISET, the output
frequency takes approximately TBD master clock cycles
(TBD • tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 13.
R
E
AC
PL
L
HO
E
AC
PL
Figure 10. PWM Frequency Response
Figure 12. Frequency Modulation Bandwidth
R
DE
E
AC
PL
L
HO
Figure 11. PWM Settling Time
R
DE
DE
L
HO
R
DE
E
AC
PL
L
HO
Figure 13. Frequency Change Settling Time
69921234p
21
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
If N DIV = 1 (DIVCODE = 0 or 15):
IS(TYP) ≈ V + • fOUT • ( 39pF + CLOAD )
L+
V+
V+
+
+ 2.2 •ISET + 85µA
320kΩ 2 • RLOAD
If N DIV > 1 (DIVCODE = 1 or 14):
IS(TYP) ≈ V + •
L+
fOUT
NDIV
• 27pF + V + • fOUT • ( 27pF + CLOAD )
V+
V+
+
+ 2.6 •ISET + 90µA
320kΩ 2 • RLOAD
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
Figure 14 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
69921234p
22
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
MOD
OUT
LTC6992
V+
GND
SET
C1
0.1μF
V+
R1
DIV
RSET
R2
V+
R1
R2
V+
C1
C1
V+
OUT
MOD
OUT
DIV
GND
GND
V+
SET
MOD
SET
DIV
R1
RSET
RSET
DFN PACKAGE
R2
TSOT-23 PACKAGE
6992 F14
Figure 14. Supply Bypassing and PCB Layout
TYPICAL APPLICATIONS
Constant On-Time Modulator
VMOD
MOD
VIN
0V TO 2V
RIN*
11.8k
VCTRL
RM1
1.05k
RM2
9.31k
GND
RSET
44.2k
VSET
OUT
OUT
VCC
LTC6992-1
SET
V+
C1
0.1μF
DIV
6992 TA02
R1
182k
DIVCODE = 2
(÷16, POL = 1)
R2
976k
*OPTIONAL RESISTOR ADJUSTS FOR DESIRED VIN RANGE.
IF
R
RM2
0.9 THEN tON = NDIV • 1.125μs • SET
RM1 +RM2
50k
AS VIN INCREASES, tOUT INCREASES AND DUTY CYCLE
DECREASES (BECAUSE POL = 1) TO MAINTAIN A CONSTANT tON.
FOR CONSTANT OFF-TIME, JUST CHANGE DIVCODE SO POL = 0.
69921234p
23
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Digitally Controlled Duty Cycle with Internal VREF Reference Variation Eliminated
MOD
OUT
V+
LTC6992-X
V+
+
1/2
LTC6078
GND
V+
SET
DIV
RSET
C1
0.1μF
R1
R2
6992 TA03
–
V+
VCC
DIN
REF
VOUT
LTC1659
μP
CLK
CS/LD
GND
Programming NDIV Using an 8-Bit DAC
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
OUT
LTC6992-X
RSET
GND
V+
SET
DIV
2.25V TO 5.5V
C1
0.1μF
C2
0.1μF
VCC
SDI
VOUT LTC2630-LZ8 SCK
CS/LD
GND
μP
DIVCODE
DAC CODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
24
40
56
72
88
104
120
136
152
168
184
200
216
232
≥255
6992 TA04
69921234p
24
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Changing Between Two Frequencies
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
LTC6992-X
V+
GND
V+
fMAX
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
OUT
OUT
LTC6992-X
V+
GND
SET
R1
SET
DIV
RSET
V+
V+
R1
RVCO
fMIN
MOD
V+
R2
RSET2
DIV
RSET1
R2
fMIN
‘HC04
fMAX
2N7002
‘HC04
6992 TA05
NOTES
1. WHEN THE NMOSFET IS OFF, THE FREQUENCY IS SET BY RSET = RSET1.
2. WHEN THE NMOSFET IS ON, THE FREQUENCY IS SET BY RSET = RSET1 || RSET2.
3. V+ SUPPLY VARIATION IS NOT A FACTOR AS THE SWITCHING RESISTOR IS
EITHER FLOATING OR CONNECTED TO GROUND.
NOTES
WHILE THIS CIRCUIT IS SIMPLER THAN THE CIRCUIT TO THE RIGHT,
ITS FREQUENCY ACCURACY IS WORSE DUE TO THE EFFECT OF
V+ SUPPLY VARIATION FROM SYSTEM TO SYSTEM AND OVER TEMPERATURE.
Simple Diode Temperature Sensor
R8
84.5k
5V
R6
R7
45.3k 16.9k
D1
1N458
5V
+10mV/C
5V
R9
365Ω
–
+
MOD
LT6003
R2
50k
R3
130k
GND
V+
SET
DIV
6992 TA06
MOC207M
D3
LTC6992-2
R1
130k
ADJUST FOR 50% DUT CYCLE AT 25°C
OUT
5V
R4
1000k
R5
186k
Q1
OUTPUT
R11
422Ω
C1
1μF
NDIV = 16
f = 10kHz
PWM OUTPUT FOR ISOLATED MEASUREMENT
+1% DUTY CYCLE CHANGE PER DEGREE C
–10°C TO 65°C RANGE WITH OPTO-ISOLATOR (DC: 15% TO 95%)
69921234p
25
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Motor Speed/Direction Control for Full H-Bridge (Locked Anti-Phase Drive)
VS
12V
2.6kHz, 5% TO 95% PWM
5% DC = CLOCKWISE
50% DC = STOPPED
95% DC = COUNTER CLOCKWISE
INPUT 0V TO 1V
MOD
A1
CW CURRENT
FLOW
MOTOR
OUT
LTC6992-2
V+
GND
V+
A2
R1
1000k
SET
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R3
300k
R2
280k
6992 TA07
Motor Speed/Direction Control for Full H-Bridge (Sign/Magnitude Drive)
VS
12V
A4
A5
2.6kHz, 5% TO 95% PWM
5% DC = SLOW
95% DC = FAST
INPUT 0V TO 1V
MOD
CW CURRENT
FLOW
MOTOR
OUT
LTC6992-2
R3
300k
GND
V+
SET
DIV
V+
R4
1000k
R5
280k
POWER H-BRIDGE
HIGH = SWITCH ON
A3
DIRECTION
H = CCW, L = CW
6992 TA08
69921234p
26
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Ratiometric Sensor to Pulse Width, Non-Inverting Response
R6
9.09k
VS
R4
90.9k
2.5V TO 5.5V
R5
10M
RSENSOR
MOD
LT1490
K • VS
K=0
C1
0.15μF
–
+
R3
10k
K=1
C2
0.22μF
OUT
OUTPUT
DUTY CYCLE = K • 100%
LTC6992-1
RSET
316k
GND
V+
SET
DIV
6992 TA09
VS
R1
1000k
R2
186k
NDIV = 16
fOUT = 10kHz
Ratiometric Sensor to Pulse Width, Inverting Response
R6
9.09k
VS
VS
R3
100k
K=1
C2
0.22μF
R6
90.9k
2.5V TO 5.5V
C1
0.15μF
RSENSOR
–
+
K • VS
K=0
R4
10k
MOD
LT1490
VS
OUT
OUTPUT
DUTY CYCLE = (1–K) • 100%
LTC6992-1
R5
10k
RSET
316k
GND
V+
SET
DIV
6992 TA10
VS
R1
1000k
R2
186k
NDIV = 16
fOUT = 10kHz
69921234p
27
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Ratio Control Servo Pulse Generator
R6
9.09k
2.5V TO 5.5V
C2
0.22μF
C1
1μF
R6
90.9k
VS
VS
R5
130k
–
+
MOD
LT1490
R6
8.66k
SERVO
CONTROL
POT
10k
OUTPUT
1ms TO 2ms PULSE EVERY 16ms
OUT
LTC6992-1
GND
V+
VS
R1
1000k
2ms
SET
1ms
DIV
R2
681k
6992 TA11
RSET
316k
NDIV = 4096
fOUT = 62.5kHz, 16ms PERIOD
Direct Voltage Controlled PWM Dimming 0 to 15000 Cd/m2 Intensity
R3
90.9Ω
VDIMMING
MOD
OUT
LTC6992-1
D1
V+
GND
5V
R1
1M
SET
RSET
105k
C1
0.1μF
HIGH INTENSITY LED
SSL-LX5093XUWC
DIV
6992 TA12
R2
280k
f = 7.5kHz
NDIV = 64
69921234p
28
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Wide Range LED Dimming (0 to 85000 Cd/m2 Brightness)
R2
7.5k
5V
R1
10k
–
+
VFAST
5V
–
+
LT6004
MOD
LT6004
R4
7.5k
FAST PWM
CONTROLS 6000 TO 85000
Cd/m2 BRIGHTNESS
OUT
LTC6992-4
V+
GND
R3
10k
RDIV1
1M
VREF
SET
RSET1
61.9k
5V
C4
0.1μF
DIV
3.3V
5V
3.3VIN
PVIN
RDIV2
280k
LED+
5–100%
NDIV = 64
f = 12.6kHz
A1
D1
PWM
LT3518UF
D2
VDIMMING
0V TO 1.65V
SLOW PWM
CONTROLS 0 TO 6000
Cd/m2 BRIGHTNESS
VSLOW
MOD
LUMILEDS LXHL-BW02
OUT
LTC6992-1
GND
V+
RDIV3
1M
SET
RSET2
124k
5V
C1
0.1μF
DIV
0–100%
NDIV = 4096
fOUT = 100kHz
RDIV4
681k
6992 TA13
69921234p
29
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PACKAGE DESCRIPTION
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
R = 0.05
TYP
2.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
0.40 ± 0.10
4
6
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
3
0.200 REF
0.75 ±0.05
1
(DCB6) DFN 0405
0.25 ± 0.05
0.50 BSC
1.35 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
69921234p
30
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636 Rev B)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.90 BSC
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
S6 TSOT-23 0302 REV B
69921234p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATION
LED Driver with 5000:1 Dimming Range
L1
6.8μH
VIN
5V TO 16V
SHDN VIN
D1
SW
FB
R2
124k
LT3517
ANALOG PWM
DUTY CYCLE
CONTROL
(0V TO 1V)
MOD
LTC6992-1
GND
PWM
OUT
5V
TGEN
C1
2.2μF
V+
SET
DIV
102k
RSENSE
330mΩ
CTRL
ISN
SYNC
TG
VC
681k
C4
0.1pF
RT
6.04k
2MHz
300mA
ISP
VREF
1M
C1
0.22μF
R1
3.92M
RT
C2
4.7μF
SS GND
C3
0.1pF
6992 TA14
C1: KEMET C0806C225K4RAC
C2: KEMET C1206C475K3RAC
C3, C4: MURATA GRM21BR71H104KA01B
C5: MURATA GRM21BR71H224KA01B
D1: DIODE DFL5160
L1: TOKO B992A5-6RBN
LEDS: LUXEON I (WHITE)
M1: ZETEX ZXMP6A13FTA
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1MHz to 33MHz ThinSOT Silicon Oscillator
Wide Frequency Range
LTC6900
1MHz to 20MHz ThinSOT Silicon Oscillator
Low Power, Wide Frequency Range
LTC6906/LTC6907
10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
Micropower, ISUPPLY = 35μA at 400kHz
LTC6990
TimerBlox, Voltage Controlled Oscillator
Frequency from 488Hz to 1MHz, No Caps, 2% Accurate
LTC6991
TimerBlox, Very Low Frequency Clock with Reset
Cycle Time from 2ms to 9.5 Hours, No Caps, 2% Accurate
LTC6993-1
TimerBlox, Monostable Pulse Generator
Resistor Set Pulse Width from 1μs to 2ms, No Caps, 2% Accurate
LTC6993-2
TimerBlox, Retriggerable Monostable Pulse Generator
Resistor Set Pulse Width from 1μs to 2ms, No Caps, 2% Accurate
LTC6994-1
TimerBlox, Delay Block, First Edge Only Delayed
Resistor Set Delay from 1μs to 2ms, No Caps, 2% Accurate
LTC6994-2
TimerBlox, Delay Block/Debouncer, Both Edges Delayed
Resistor Set Delay from 1μs to 2ms, No Capacitors Required,
2% Accurate
69921234p
32 Linear Technology Corporation
LT 0510 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010