CLARE M-88L70-01T 3v dtmf receiver Datasheet

M-88L70
3V DTMF Receiver
Features
• Operates between 2.7 and 3.6 volts
• Low power consumption
• Power-down mode
• Inhibit mode
• Central office quality and performance
• Inexpensive 3.58 MHz time base
• Adjustable acquisition and release times
• Dial tone suppression
• Functionally compatible with Clare’s M-8870
Description
The M-88L70 monolithic DTMF receiver offers small size,
low power consumption and high performance, with 3 volt
operation. Its architecture consists of a bandsplit filter
section, which separates the high and low group tones,
followed by a digital counting section which verifies the
frequency and duration of the received tones before
passing the corresponding code to the output bus.
Applications
• Telephone switch equipment
• Mobile radio
• Remote control
• Paging systems
• PCMCIA
• Portable TAD
• Remote data entry
Ordering Information
Part #
M-88L70-01P
M-88L70-01S
M-88L70-01T
Description
18-pin plastic DIP
18-pin SOIC
18-pin SOIC, Tape and Reel
Figure 1 Pin Connections
The M-88L70 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-88L70 offers low
power consumption (18 mW max), precise data handling
and 3V operation. Its filter section uses switched capacitor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone pairs
into a 4-bit code. External component count is minimized
by provision of an on-chip differential input amplifier,
clock generator, and latched tri-state interface bus.
Minimal external components required include a low-cost
3.579545 MHz color burst crystal, a timing resistor, and a
timing capacitor.
Figure 2 Block Diagram
DS-M88L70-R1
www.clare.com
1
M-88L70
Filter
The low and high group tones are separated by applying
the dual-tone signal to the inputs of two 9th order
switched capacitor bandpass filters with bandwidths that
correspond to the bands enclosing the low and high
group tones. The filter also incorporates notches at 350
and 440 Hz, providing excellent dial tone rejection. Each
filter output is followed by a single-order switched capacitor section that smoothes the signals prior to limiting.
Signal limiting is performed by high-gain comparators
provided with hysteresis to prevent detection of unwanted low-level signals and noise. The comparator outputs
provide full-rail logic swings at the frequencies of the
incoming tones.
Decoder
The M-88L70 decoder uses a digital counting technique
to determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect
against tone simulation by extraneous signals (such as
voice) while tolerating small frequency variations. The
algorithm ensures an optimum combination of immunity
to talkoff and tolerance to interfering signals (third tones)
and noise. When the detector recognizes the simultaneous presence of two valid tones (known as “signal condi-
tion”), it raises the Early Steering flag (ESt). Any subsequent loss of signal condition will cause ESt to fall.
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as “character-recognition-condition”). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see Figure 3) to rise as the
capacitor discharges. Provided that signal condition is
maintained (ESt remains high) for the validation period
(tGTP), VC reaches the threshold (VTSt) of the steering
logic to register the tone pair, thus latching its corresponding 4-bit code (see Table 2) into the output latch.
At this point, the GT output is activated and drives VC to
VDD. GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output latch
to settle, the “delayed steering” output flag (StD) goes
high, signaling that a received tone pair has been registered. The contents of the output latch are made
available on the 4-bit output bus by raising the threestate control input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
Table 1 Pin Functions
Pin
1
2
3
4
5
6
7
8
9
10
11-14
2
15
Name
IN+
IN
GS
VREF
INH
PD
OSC1
OSC2
VSS
OE
Q1, Q2,
Q3, Q4
StD
16
ESt
17
St/GT
18
VDD
Description
Non-inverting input
Connections to the front-end differential amplifier
-Inverting input
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones representing keys A, B, C, and D. This input is internally pulled down.
Power down. Logic high powers down the device and inhibits the oscillator. This input is internally pulled down.
Clock input
3.579545 MHz crystal connected between these pins completes internal oscillator.
Clock output
Negative power supply (normally connected to 0 V).
Tri-state output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
Tri-state outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received
(see Table 5.)
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair
(signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to
register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new
tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the
voltage on St. (See Figure 5).
Positive power supply
www.clare.com
Rev. 1
M-88L70
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.
Figure 3 Basic Steering Circuit
Guard Time Adjustment
Where independent selection of receive and pause are
not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to
the formula:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 K ohm. A typical circuit using this
steering configuration is shown in Figure 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrangements may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA). This
may be necessary to meet system specifications that
place both accept and reject limits on both tone duration
and interdigit pause.
Guard time adjustment also allows the designer to tailor
system parameters such as talkoff and noise immunity.
Increasing tREC improves talkoff performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition long enough to be registered. On the other hand, a relatively short tREC with a
long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to
dropouts would be required. Design information for
guard time adjustment is shown in Figure 5.
Input Configuration
The input arrangement of the M-88L70 provides a differential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision is
made for connection of a feedback resistor to the opamp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are connected as shown in Figure 4 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD.
Figure 7 shows the differential configuration, which permits gain adjustment with the feedback resistor R5.
Table 2 Tone Decoding
FLOW
FHIGH
ANY
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
697
770
852
941
ANY
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
1633
1633
1633
1633
Key
(ref.)
ANY
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
A
B
C
D
OE
INH
ESt
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
Q4
Q3
Q2
Q1
Z
Z
Z
Z
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
Undetected, the output
code will remain the
same as the previous
detected code.
L = logic low, H = logic high, Z = high impedance, X = don’t care
Rev. 1
www.clare.com
3
M-88L70
Absolute Maximum Ratings
Parameter
Power supply voltage
(VDD - VSS)
Voltage on any pin
Symbol
VDD
Value
6.0 V max
Vdc
Current on any pin
Operating temperature
Storage temperature
IDD
TA
TS
VSS -0.3 Min,
VDD +0.3 Max
10 mA max
-40˚C to + 85˚C
-65˚C to + 150˚C
Absolute Maximum Ratings are stress ratings. Stresses
in excess of these ratings can cause permanent damage to the device. Functional operation of the device at
these or any other conditions beyond those indicated in
the operational sections of this data sheet is not implied.
Exposure of the device to the absolute maximum ratings
for an extended period may degrade the device and
effect its reliability.
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Table 4 DC Characteristics
PARAMETER
Operating supply voltage
Operating supply current
Standby supply current
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Pull down (sink) Curent PD
Pull down (sink) Current INH
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output high (source) current
Output voltage VREF
Output resistance VREF
SYMBOL
VDD
IDD
IDDS
PO
VIL
VIH
IIH/IIL
ISO
IPD
IINH
RIN
VTSt
VOL
VOH
IOH
VREF
ROR
MIN
2.7
-v
2
-12
2.4
1.0
-
TYP
3.0
3.0
5.0
9
0.1
1.0
1.0
10
1.5
0.1
2.6
1.5
10
MAX
3.6
5.0
10
18
1.0
45
45
0.4
-
UNITS
V
mA
µA
mW
V
V
µA
µA
µA
µA
MΩ
V
V
V
mA
V
kΩ
TEST CONDITIONS
PD=VDD
VDD = 3.0 V
VDD = 3.0 V
VIN = VSS or VDD (see Note 2)
OE = 0 V
PD = 3.0 V
INH = 3.0 V
@ 1 kHz
IOL = 1.0 mA
IOH = -400 mA
VOUT = 2.5 V @ VDD = 2.7 V
No load
Notes:
1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 3.0 V + 20%/-10%, VSS = 0 V, TA = 25˚C
2. Input pins defined as IN+, IN-, and OE.
4
www.clare.com
Rev. 1
M-88L70
Table 5 Operating Characteristics - Gain Setting Amplifier
PARAMETER
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Common mode range
SYMBOL
IN
RIN
VOS
PSRR
CMRR
AVOL
fC
VO
CL
RL
VCM
MIN
50
40
32
0.3
50
-
TYP
100
10
15
60
60
65
1.0
2.2
1.5
MAX
25
100
-
UNITS
nA
MΩ
mV
dB
dB
dB
MHz
VP-P
pF
kΩ
V P-P
TEST CONDITIONS
VSS < VIN < VDD
1 kHz
-3.0V < VIN < 3.0V
RL 3 100 kΩ to VSS
No load
All voltages referenced to VSS unless otherwise noted. VDD = 3.0 V +20%/-10%, VSS = 0 V, TA = -40˚C to + +85˚C
Table 6 AC Characteristics
PARAMETER
Valid input signal levels
(each tone of composite signal)
Positive twist accept
Negative twist accept
Frequency deviation accept limit
Frequency deviation reject limit
Third tone tolerance
Noise tolerance
Dial tone tolerance
Tone present detection time
Tone absent detection time
Minimum tone duration accept
Maximum tone duration reject
Minimum interdigit pause accept
Maximum interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data setup (Q to StD)
Propagation delay (OE to Q), enable
Propagation delay (OE to Q), disable
Crystal clock frequency
Clock output (OSC2), capacitive load
SYMBOL
tDP
tDA
tREC
tREC
tID
tDO
tPQ
tPStD
tQStD
tPTE
tPTD
fCLK
CLO
MIN
-36
12.3
±3.5%
5
0.5
20
20
3.5759
-
TYP
MAX
-6.4
370
6
6
1.5% ±2 Hz
-16
-12
+22
8
14
3
8.5
40
40
13
8
3.4
200
500
3.5795
3.5831
30
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 3.0 V, VSS = 0 V, TA = -40˚C to +85˚C, fCLK = 3.579545 MHz.
UNITS
dBm
mVRMS
dB
dB
Nom.
Nom.
dB
dB
dB
ms
ms
ms
ms
ms
ms
µs
µs
µs
ns
ns
MHz
pF
NOTES
1,2,3,4,5,8
2,3,5,8,10
2,3,5
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
2,3,4,5,7,8,9
See Figure 8
User adjustable (see Figures 3
and Figure 5)
OE = VDD
RL = 10kΩ, CL = 50 pF
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600 Ω load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) ± 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias VREF.
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Figure 4. Input DTMF tone level at -28 dBm.
Rev. 1
www.clare.com
5
M-88L70
Figure 4 Single-Ended Input Configuration
Figure 5 Guard Time Adjustment
Figure 6 Timing Diagram
Explanation of Symbols
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not
updated.
(B) Tone #n detected, tone duration valid, tone decoded
and latched in outputs.
(C) End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance).
(F) Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
VIN
DTMF composite input signal.
ESt
Early steering output. Indicates detection of
valid tone frequencies.
St/GT
Steering input/guard time output. Drives
external RC timing circuit.
Q1 - Q4
4-bit decoded tone output.
StD
Delayed steering output. Indicates that valid
frequencies have been present/absent for
the required guard time, thus constituting a
valid signal.
OE
Output enable (input). A low level shifts Q1 Q4 to its high impedance state.
tREC
Maximum DTMF signal duration not detected
as valid.
tREC
Minimum DTMF signal duration required for
valid recognition.
tID
Minimum time between valid DTMF signals.
tDO
Maximum allowable dropout during valid DTMF
signal.
tDP
Time to detect the presence of valid DTMF
signals.
tDA
Time to detect the absence of valid DTMF
signals.
tGTP
Guard time, tone present.
tGTA
Guard time, tone absent.
(G) End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
6
www.clare.com
Rev. 1
M-88L70
Figure 7 Differential Input Configuration
Figure 8 Common Crystal Connection
Figure 9 Package Dimensions
Tolerances
Inches
Min
A
A1
b
b2
C
D
E
E1
e
ec
L
Max
.210
.015
.014
.022
.045
.070
.008
.014
.880
.920
.300
.325
.240
.280
.100 BSC
0˚
15˚
.115
.150
Metric (mm)
Min
Max
5.33
.38
.
36
.56
1.1
1.7
. .20
.36
23.35
23.37
7.62
8.26
6.10
7.11
2.54 BSC
0˚
15˚
2.92
3.81
Tolerances
A
A1
b
D
E
e
H
L
Rev. 1
www.clare.com
Inches
Min
Max
.0926
.1043
.0040
.0118
.013
.020
.4469
.4625
.2914
.2992
.050 BSC
.394
.419
.016
.050
Metric (mm)
Min
Max
2.35
2.65
.10
.30
.33
.51
11.35
11.75
7.4
7.6
1.27 BSC
10.00
10.65
.40
1.27
7
Worldwide Sales Offices
CLARE LOCATIONS
EUROPE
ASIA PACIFIC
Clare Headquarters
78 Cherry Hill Drive
Beverly, MA 01915
Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
European Headquarters
CP Clare nv
Bampslaan 17
B-3500 Hasselt (Belgium)
Tel: 32-11-300868
Fax: 32-11-300890
Clare Micronix Division
145 Columbia
Aliso Viejo, CA 92656-1490
Tel: 1-949-831-4622
Fax: 1-949-831-4628
France
Clare France Sales
Lead Rep
99 route de Versailles
91160 Champlan
France
Tel: 33 1 69 79 93 50
Fax: 33 1 69 79 93 59
Asian Headquarters
Clare
Room N1016, Chia-Hsin, Bldg II,
10F, No. 96, Sec. 2
Chung Shan North Road
Taipei, Taiwan R.O.C.
Tel: 886-2-2523-6368
Fax: 886-2-2523-6369
SALES OFFICES
AMERICAS
Americas Headquarters
Clare
78 Cherry Hill Drive
Beverly, MA 01915
Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
Eastern Region
Clare
P.O. Box 856
Mahwah, NJ 07430
Tel: 1-201-236-0101
Fax: 1-201-236-8685
Toll Free: 1-800-27-CLARE
Central Region
Clare Canada Ltd.
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
Western Region
Clare
1852 West 11th Street, #348
Tracy, CA 95376
Tel: 1-209-832-4367
Fax: 1-209-832-4732
Toll Free: 1-800-27-CLARE
Canada
Clare Canada Ltd.
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
Germany
Clare Germany Sales
ActiveComp Electronic GmbH
Mitterstrasse 12
85077 Manching
Germany
Tel: 49 8459 3214 10
Fax: 49 8459 3214 29
Italy
C.L.A.R.E.s.a.s.
Via C. Colombo 10/A
I-20066 Melzo (Milano)
Tel: 39-02-95737160
Fax: 39-02-95738829
Sweden
Clare Sales
Comptronic AB
Box 167
S-16329 Spånga
Tel: 46-862-10370
Fax: 46-862-10371
United Kingdom
Clare UK Sales
Marco Polo House
Cook Way
Bindon Road
Taunton
UK-Somerset TA2 6BG
Tel: 44-1-823 352541
Fax: 44-1-823 352797
http://www.clare.com
Clare cannot assume responsibility for use of any circuitry other
than circuitry entirely embodied in this Clare product. No circuit
patent licenses nor indemnity are expressed or implied. Clare
reserves the right to change the specification and circuitry, without notice at any time. The products described in this document
are not intended for use in medical implantation or other direct life
support applications where malfunction may result in direct physical harm, injury or death to a person.
Specification: DS-M88L70-R1
©Copyright 2000, Clare, Inc.
All rights reserved. Printed in USA.
1/29/01