LINER LTC3603EUF 2.5a, 15v monolithic synchronous step-down regulator Datasheet

LTC3603
2.5A, 15V Monolithic
Synchronous Step-Down
Regulator
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
Wide Input Voltage Range: 4.5V to 15V
2.5A Output Current
Low RDS(ON) Internal Switches: 45mΩ and 85mΩ
Programmable Frequency: 300kHz to 3MHz
Low Quiescent Current: 75μA
0.6V ±1% Reference Allows Precise,
Low Output Voltage
99% Maximum Duty Cycle
Adjustable Burst Mode® Clamp
Synchronizable to External Clock
Power Good Output Voltage Monitor
Overtemperature Protection
Overvoltage Protection
Available in 16-Lead Thermally Enhanced MSOP
and 4mm × 4mm QFN Packages
APPLICATIONS
n
n
n
Point-of-Load Supplies
Portable Instruments
Communications Infrastructure
The LTC®3603 is a high efficiency, monolithic synchronous
step-down DC/DC converter utilizing a constant-frequency,
current mode architecture. It operates from an input voltage
range of 4.5V to 15V and provides an adjustable regulated
output voltage from 0.6V to 14.5V while delivering up to
2.5A of output current. The internal synchronous power
switch with 45mΩ on-resistance increases efficiency
and eliminates the need for an external Schottky diode.
The switching frequency can either be set by an external
resistor or synchronized to an external clock. OPTI-LOOP®
compensation allows the transient response to be optimized
over a wide range of loads and output capacitors.
The LTC3603 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous
operation reduces noise and RF interference, while Burst
Mode operation provides the highest efficiency at light
loads. In Burst Mode operation, external control of the burst
clamp level allows the output voltage ripple to be adjusted
according to the requirements of the application.
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered
trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5481178,
6580258, 6498466, 6611131, 6177787, 5705919, 5847554.
TYPICAL APPLICATION
3.3V, 2.5A, 1MHz Step-Down Regulator
Efficiency and Power Loss vs Load Current
VIN
4.5V TO 15V
100
95
22μF
1μF
0.22μF
2.2μH
LTC3603
PGOOD
VOUT
3.3V
100μF 2.5A
SW
TRACK/SS
4.32k
1nF
SYNC/MODE VFB
105k
1000
85
80
100
75
POWER LOSS
70
PGND
ITH
EFFICIENCY (%)
105k
BOOST
POWER LOSS (mW)
RT
EFFICIENCY
90
PVIN INTVCC
RUN
10000
VIN = 12V
10
65
475k
60
0.001
10pF
3603 TA01
0.01
0.1
1
LOAD CURRENT (A)
1
10
3603 TA01b
3603fa
1
LTC3603
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PVIN Supply Voltage (DC) .......................... –0.3V to 16V
PVIN Supply Transient Voltage (<1μs) .......................21V
SW .............................................. –0.3V to (PVIN + 0.3V)
BOOST .................................(VSW –0.3V) to (VSW + 6V)
RUN ........................................................... –0.3V to 16V
All Other Pins ............................................... –0.3V to 6V
Peak SW Sink and Source Current (Note 7) .............6.5A
Operating Junction Temperature Range (Notes 2, 5, 6)
LTC3603E ............................................–40°C to 85°C
LTC3603I ........................................... –40°C to 125°C
Lead Temperature (Soldering, 10 seconds)
MSE Package .................................................... 300°C
SW
SW
SW
TOP VIEW
SW
BOOST
PIN CONFIGURATION
20 19 18 17 16
TOP VIEW
15 PGND
PVIN 1
14 PGND
PVIN 2
21
SGND
INTVCC 3
13 PGND
12 PGND
SYNC/MODE 4
11 TRACK/SS
PGOOD 5
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
6
7
8
9 10
RUN
MSE PACKAGE
16-LEAD PLASTIC MSOP
SGND
PVIN
PVIN
BOOST
SW
SW
PGND
PGND
TRACK/SS
VFB
17
SGND
16
15
14
13
12
11
10
9
RT
1
2
3
4
5
6
7
8
ITH
INTVCC
SYNC/MODE
PGOOD
RT
ITH
VFB
SGND
RUN
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3603EMSE#PBF
LTC3603EMSE#TRPBF
3603
16-Lead Plastic MSOP
–40°C to 85°C
LTC3603IMSE #PBF
LTC3603IMSE#TRPBF
3603
16-Lead Plastic MSOP
–40°C to 125°C
LTC3603EUF#PBF
LTC3603EUF#TRPBF
3603
–40°C to 85°C
20-Lead (4mm × 4mm) Plastic QFN
LTC3603IUF#PBF
LTC3603IUF#TRPBF
3603
–40°C to 125°C
20-Lead (4mm × 4mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3603fa
2
LTC3603
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V unless otherwise specified.
SYMBOL
PVIN
VFB
CONDITIONS
ITH = 0.7V (Note 3)
VIN = 5V to 15V, ITH = 0.7V
l
ΔVFB(LINEREG)
PARAMETER
Operating Voltage Range
Regulated Feedback Voltage
Feedback Voltage Line Regulation
ΔVFB(LOADREG)
Feedback Voltage Load Regulation
ITH = 0.36V to 0.84V
l
ΔVPGOOD
RPGOOD
IFB
gm
IS
INTVCC
tON, MIN
VRUN
ITRACK/SS
fOSC
fSYNC
RDS(ON)
ILIM
ILSW
VUVLO
VUVLO, HYS
MIN
4.5
0.594
TYP
0.6
0.005
MAX
15
0.606
UNITS
V
V
%/V
0.02
0.1
%
Power Good Range
±10
±12
%
Power Good Resistance
55
80
FB Input Bias Current
Transconductance Amplifier gm
Supply Current
Active Mode
Sleep Mode
Shutdown
VCC LDO Output Voltage
Minimum Controllable ON-Time
RUN Pin ON Threshold
TRACK/SS Pull-Up Current
Oscillator Frequency
SYNC Capture Range
Top Switch On-Resistance
Bottom Switch On-Resistance
10
1.7
Ω
nA
mS
700
100
1
5.1
115
1
μA
μA
μA
V
ns
V
μA
MHz
MHz
Peak Current Limit
Switch Leakage Current
INTVCC Undervoltage Lockout
INTVCC Undervoltage Lockout Hysteresis
(Note 4)
4.7
VRUN Rising
TRACK/SS = 1V
RT = 105k
l
0.4
0.85
0.3
500
75
0.2
4.9
95
0.7
1.25
1
1.15
3
85
45
3.8
INTVCC Ramping Up
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3603E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3603I is guaranteed
over the –40°C to 125°C operating junction temperature range.
Note 3: The LTC3603 is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
l
4.1
4.5
0.1
4.2
700
5.2
1
4.3
mΩ
mΩ
A
μA
V
mV
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient temperature TA and the power
dissipation as follows: TJ = TA + (PD)(θJAºC/W).
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 7: This limit indicates the current density limitations of the internal
metallization and it is not tested in production.
3603fa
3
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Transient
Forced Continuous
Burst Mode Operation
OUTPUT
VOLTAGE
50mV/DIV
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
500mA/DIV
LOAD
CURRENT
1A/DIV
VIN = 12V
VOUT = 3.3V
LOAD = 50mA
90
VIN = 12V
0.6004
0.5998
75
70
65
60
55
50
0.5996
50
25
75
0
TEMPERATURE (°C)
100
40
125
BOTTOM
40
4
6
5
7
0
–50 –25
8 9 10 11 12 13 14 15
INPUT VOLTAGE (V)
50
25
75
0
TEMPERATURE (°C)
3603 G04
PVIN Leakage Current
vs Input Voltage
100
125
3603 G05
Frequency vs ROSC
VRUN = 0V
45
60
BOTTOM
3603 G03
50
TOP
80
20
45
0.5994
–50 –25
VIN = 12V
100
RESISTANCE (mΩ)
RESISTANCE (mΩ)
VREF (V)
0.6000
120
TOP
80
0.6002
Switch On-Resistance
vs Temperature
VBOOST – VSW = INTVCC
85
3603 G02
10μs/DIV
Switch On-Resistance
vs Input Voltage
VREF vs Temperature
0.6006
VIN = 12V
VOUT = 3.3V
3603 G01
10μs/DIV
Frequency vs Input Voltage
3500
1040
3000
1030
ROSC = 105kΩ
30
25
20
15
10
1020
2500
FREQUENCY (kHz)
35
FREQUENCY (kHz)
INPUT CURRENT (nA)
40
2000
1500
1000
5
6
7
8 9 10 11 12 13 14 15
INPUT VOLTAGE (V)
3603 G06
990
970
960
0
4
1000
980
500
5
0
1010
0
50
100
150 200 250
ROSC (kΩ)
300
350
3603 G07
4
5
6
7 8 9 10 11 12 13 14 15
INPUT VOLTAGE (V)
3603 G08
3603fa
4
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
vs Input Voltage
Frequency vs Temperature
1015
ACTIVE
1005
1000
995
990
400
300
200
100
985
980
–50 –25
0
25
50
75
100
4
6
5
7
0
–50 –25
3.0
1.0
0.5
0
0.4
0.5
0.6
0.7
0.8
0.9
BURST CLAMP VOLTAGE (V)
FIGURE 6 CIRCUIT
3
2
1
VIN = 15V
VIN = 12V
85
80
0
70
0.001
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
0.1
1
0.01
LOAD CURRENT (A)
3603 G13
Efficiency vs Load Current,
Forced Continuous
VIN = 5V
VIN = 15V
Efficiency vs Frequency
100
FIGURE 6 CIRCUIT
95
ILOAD = 1A
90
ILOAD = 2.5A
10
3603 G14
Efficiency vs Input Voltage
100
FIGURE 6 CIRCUIT
FIGURE 6 CIRCUIT
ILOAD = 2A
98
96
EFFICIENCY (%)
80
VIN = 12V
70
VIN = 7.2V
60
50
85
80
94
VIN = 7.2V
92
VIN = 12V
90
88
75
40
30
0.01
90
75
3603 G12
90
VIN = 7.2V
VIN = 5V
95
4
0
1.0
125
100
EFFICIENCY (%)
PEAK INDUCTOR CURRENT (A)
1.5
100
Efficiency vs Load Current,
Burst Mode Operation
5
2.0
50
25
75
0
TEMPERATURE (°C)
3603 G11
Maximum Peak Inductor Current
vs Duty Cycle
2.5
SLEEP
3603 G10
Minimum Peak Inductor Current
vs Burst Clamp Voltage
PEAK INDUCTOR CURRENT (A)
200
8 9 10 11 12 13 14 15
INPUT VOLTAGE (V)
3603 G09
EFFICIENCY (%)
300
100
SLEEP
TEMPERATURE (°C)
100
400
0
125
ACTIVE
500
QUIESCENT CURRENT (μA)
QUIESCENT CURRENT (μA)
500
1010
FREQUENCY (kHz)
600
600
ROSC = 105kΩ
EFFICIENCY (%)
1020
Quiescent Current
vs Temperature
70
0.1
1
LOAD CURRENT (A)
10
3603 G15
86
4
5
6
7
8 9 10 11 12 13 14 15 16
INPUT VOLTAGE (V)
3603 G16
84
0
1000
2000
3000
FREQUENCY (kHz)
3603 G17
3603fa
5
LTC3603
TYPICAL PERFORMANCE CHARACTERISTICS
5V LDO Output Voltage
vs Temperature
Load Regulation
5.10
FIGURE 6 CIRCUIT
VIN = 12V
1.40
LDO OUTPUT VOLTAGE (V)
5.08
0
–0.10
1.35
5.06
TRACK/SS CURRENT (μA)
0.10
$VOUT/VOUT (%)
TRACK/SS Current
vs Temperature
5.04
5.02
5.00
4.98
4.96
4.94
1.30
1.25
1.20
1.15
4.92
–0.20
0
0.5
1
1.5
2
LOAD CURRENT (A)
2.5
3
4.90
–50
–25
50
25
0
75
TEMPERATURE (°C)
3603 G18
PIN FUNCTIONS
100
125
3603 G19
1.10
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3603 G20
MSE/UF Package
INTVCC (Pin 1/Pin 3): Output of Internal 5V LDO.
SYNC/MODE (Pin 2/Pin 4): Mode Select and External
Clock Synchronization Input.
PGOOD (Pin 3/Pin 5): Power Good Output. Open-drain
logic output that is pulled to ground when the output voltage is not within ±10% of regulation point.
RT (Pin 4/Pin 6): Frequency Set Pin.
ITH (Pin 5/Pin 7): Error Amplifier Compensation Point.
VFB (Pin 6/Pin 8): Feedback Pin.
SGND (Pin 7, Exposed Pad Pin 17/Pin 9, Exposed Pad
Pin 21): Signal Ground. Exposed pad is signal ground
and must be soldered to the PCB for rated thermal
performance.
RUN (Pin 8/Pin 10): Run Control Input. This pin may be
tied to PVIN to enable the chip.
TRACK/SS (Pin 9/Pin 11): Tracking Input for the Controller
or Optional External Soft-Start Input. This pin allows the
start-up of VOUT to “track” the external voltage at this pin
using an external resistor divider. An external soft-start can
be programmed by connecting a capacitor between this
pin and ground. Leave this pin floating to use the internal
1ms soft-start clamp. Do not tie this pin to INTVCC or to
PVIN.
PGND (Pins 10, 11/Pins 12, 13, 14, 15): Power
Ground.
SW (Pins 12, 13/Pins 16, 17, 18, 19): Switch Node Connection to the Inductor.
BOOST (Pin 14/Pin 20): Bootstrapped Supply to the Top
Side Floating Gate Driver.
PVIN (Pins 15, 16/Pins 1,2): Power Input Supply. Decouple
this pin with a capacitor to PGND
3603fa
6
LTC3603
BLOCK DIAGRAM
ITH
BOOST
INTVCC
PVIN
1.2μA
0.6V
LDO
VOLTAGE
REFERENCE
SLOPE
COMPENSATION
RECOVERY
TRACK/SS
1ms
SOFT-START
+
+
+
–
VFB
BCLAMP
+
–
BURST
COMPARATOR
+
MAIN
I-COMPARATOR
–
–
SYNC/MODE
0.54V
+
ERROR
AMPLIFIER
SW
+
–
SW
SLOPE
COMPENSATION
OSCILLATOR
SW
OVER-CURRENT
COMPARATOR
+
0.66V
–
LOGIC
–
REVERSE
COMPARATOR
PGOOD
+
+
–
RT
RUN
PGND
PGND
PGND
SYNC/MODE
3602 BD
3603fa
7
LTC3603
OPERATION
Main Control Loop
Burst Mode Operation
The LTC3603 is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal operation, the internal top power switch (N-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.6V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2.5A for forced continuous mode and 0A
for Burst Mode operation.
Connecting the SYNC/MODE pin to a voltage in the range
of 0.42V to 1V enables Burst Mode operation. In Burst
Mode operation, the internal power MOSFETs operate
intermittently at light loads. This increases efficiency by
minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set
by the voltage on the SYNC/MODE pin and the voltage
on the ITH pin is monitored by the burst comparator to
determine when sleep mode is enabled and disabled.
When the average inductor current is greater than the
load current, the voltage on the ITH pin drops. As the ITH
voltage falls below 330mV, the burst comparator trips and
enables sleep mode. During sleep mode, the top power
MOSFET is held off and the ITH pin is disconnected from
the output of the error amplifier. The majority of the internal
circuitry is also turned off to reduce the quiescent current
to 75μA while the load current is solely supplied by the
output capacitor. When the output voltage drops, the ITH
pin is reconnected to the output of the error amplifier and
the top power MOSFET along with all the internal circuitry
is switched back on. This process repeats at a rate that
is dependent on the load demand. Pulse-skipping operation is implemented by connecting the SYNC/MODE pin
to ground. This forces the burst clamp level to be at 0V.
As the load current decreases, the peak inductor current
will be determined by the voltage on the ITH pin until the
ITH voltage drops below 330mV. At this point, the peak
inductor current is determined by the minimum on-time
of the current comparator. If the load demand is less than
the average of the minimum on-time inductor current,
switching cycles will be skipped to keep the output voltage in regulation.
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
3MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±10%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to INTVCC will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable in
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
Frequency Synchronization
The internal oscillator of the LTC3603 can be synchronized
to an external 5V clock connected to the SYNC/MODE pin.
The frequency of the external clock can be in the range of
300kHz to 3MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
When synchronized, the LTC3603 will operate in pulseskipping mode.
3603fa
8
LTC3603
OPERATION
Dropout Operation
Overtemperature and PVIN Overvoltage Protection
When the input supply voltage decreases toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces the
top switch to remain on for more than one cycle until it
attempts to stay on continuously. In order to replenish the
voltage on the floating BOOST supply capacitor, however,
the top switch is forced off and the bottom switch is forced
on for approximately 85ns every sixteen clock cycles. This
achieves an effective duty cycle that can exceed 99%. The
output voltage will then be primarily determined by the
input voltage minus the voltage drop across the upper
internal N-channel MOSFET and the inductor.
When using the LTC3603 in an application circuit, care must
be taken not to exceed any of the ratings specified in the Absolute Maximum Ratings section. As an added safeguard,
however, the LTC3603 does incorporate an overtemperature
shutdown feature. If the junction temperature reaches approximately 150°C, both power switches will be turned off
and the SW node will become high impedance. After the
part has cooled to below 115°C, it will restart. Similarly,
the LTC3603 contains an overvoltage shutdown feature
that monitors the voltage on the PVIN pin. If this voltage
exceeds approximately 16.5V, both power switches will be
turned off until PVIN voltage is reduced below 16V.
Slope Compensation and Inductor Peak Current
Voltage Tracking and Soft-Start
Slope compensation provides stability in constant-frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 30%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3603, however,
slope compensation recovery is implemented to reduce
the variation of the maximum inductor peak current (and
therefore the maximum available output current) over the
range of duty cycles.
Some microprocessors and DSP chips need two power
supplies with different voltage levels. These systems often
require voltage sequencing between the core power supply
and the I/O power supply. Without proper sequencing,
latch-up failure or excessive current draw may occur that
could result in damage to the processor’s I/O ports or the
I/O ports of a supporting system device such as memory,
an FPGA or a data converter. To ensure that the I/O loads
are not driven until the core voltage is properly biased,
tracking of the core supply and the I/O supply voltage is
necessary.
Short-Circuit Protection
When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases to more than 4.5A, the
top power MOSFET will be held off and switching cycles
will be skipped until the inductor current is reduced.
Voltage tracking is enabled by applying a ramp voltage to
the TRACK/SS pin. When the voltage on the TRACK pin
is below 0.6V, the feedback voltage will regulate to this
tracking voltage. When the tracking voltage exceeds 0.6V,
tracking is disabled and the feedback voltage will regulate
to the internal reference voltage.
The TRACK/SS pin is also used to implement an external
soft-start function. A 1.2μA current is sourced from this
pin so that an external capacitor may be added to create
a smooth ramp. If this ramp is slower than the internal
1ms soft-start, then the output voltage will track this ramp
during start-up instead. Leave this pin floating to use the
internal 1ms soft-start ramp. Do not tie the TRACK/SS
pin to INTVCC or to PVIN.
3603fa
9
LTC3603
APPLICATIONS INFORMATION
The basic LTC3603 application circuit is shown on the front
page of this data sheet. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage. The operating frequency
of the LTC3603 is determined by an external resistor that is
connected between the RT pin and ground. The value of the
resistor sets the ramp current that is used to charge and
discharge an internal timing capacitor within the oscillator
and can be calculated by using the following equation:
R OSC =
1.15 • 1011
– 10k
f(Hz)
Although frequencies as high as 3MHz are possible, the
minimum on-time of the LTC3603 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 95ns. Therefore, the minimum duty cycle is
equal to 100 • 95ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
⎛V ⎞ ⎛ V ⎞
ΔIL = ⎜ OUT ⎟ • ⎜ 1– OUT ⎟
⎝ fL ⎠ ⎝
VIN ⎠
Having a lower ripple current reduces the ESR losses
in the output capacitors and the output voltage ripple.
Highest efficiency operation is achieved at low frequency
with small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX), where IMAX is the maximum output
current. The largest ripple current occurs at the highest
VIN. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
⎛ V
⎞ ⎛
⎞
V
L = ⎜ OUT ⎟ • ⎜ 1– OUT ⎟
⎝ fΔIL(MAX ) ⎠ ⎝ VIN(MAX ) ⎠
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of the more expensive ferrite cores. Actual
core loss is independent of core size for a fixed inductor
value but it is very dependent on the inductance selected.
As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of
wire and therefore copper losses will increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the
size/current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy but generally
cost more than powdered iron core inductors with similar
3603fa
10
LTC3603
APPLICATIONS INFORMATION
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for
the maximum RMS current should be used. RMS current
is given by:
IRMS = IOUT(MAX ) •
VOUT
•
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT , where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔVOUT , is determined by:
⎛
1 ⎞
ΔVOUT ≤ ΔIL • ⎜ ESR +
8 fCOUT ⎟⎠
⎝
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics but can have
a high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
⎛ R2 ⎞
VOUT = 0.6 V • ⎜ 1+ ⎟
⎝ R1⎠
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 1.
VOUT
R2
VFB
LTC3603
R1
SGND
3603 F01
Figure 1. Setting the Output Voltage
3603fa
11
LTC3603
APPLICATIONS INFORMATION
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is in the range of
0.42V to 1V, Burst Mode operation is enabled. During
Burst Mode operation, the voltage on the SYNC/MODE
pin determines the burst clamp level. This level sets the
minimum peak inductor current, IBURST, for each switching
cycle according to the following equation:
IBURST
V BURST =
+ 0.42V
6A / V
VBURST is the voltage on the SYNC/MODE pin. IBURST can
be programmed in the range of 0A to 3.5A, which corresponds to a VBURST range of 0.42V to 1V. As the output
load current drops, the peak inductor current decreases
to keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is therefore greater than the output load current,
the voltage on the ITH pin will decrease. When the ITH
voltage drops to 330mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
again when the output voltage drops out of regulation. The
value for IBURST is determined by the desired amount of
output voltage ripple. As the value of IBURST increases, the
sleep time between pulses and the output voltage ripple
increases. The burst clamp voltage, VBURST, can be set
by a resistor divider from the INTVCC pin. Alternatively,
the SYNC/MODE pin may be tied directly to the VFB pin to
set VBURST = 0.6V (IBURST = 1A), or through an additional
divider resistor (R3) to set VBURST = 0.42V to 0.6V (see
Figure 2).
R2
INTVCC
LTC3603
R2
SYNC/MODE
LTC3603
R3 (OPTIONAL)
SYNC/MODE
R1
SGND
VOUT
FB
R1
SGND
3603 F02
VBURST = 0.42V TO 1V
VBURST = 0.42V TO 0.6V
Figure 2. Programing the Burst Clamp
Pulse skipping, which is a compromise between low output
voltage ripple and efficiency, can be implemented by connecting the SYNC/MODE pin to ground. This sets IBURST to
0A. In this condition, the peak inductor current is limited by
the minimum on-time of the current comparator and the
lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3603’s internal oscillator can be synchronized to
an external 5V clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 3MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the RT resistor. Because slope compensation is generated
by the oscillator’s internal ramp, the external frequency
should be set 25% higher than the frequency set by the
RT resistor to ensure that adequate slope compensation
is present. When synchronized, the LTC3603 will operate
in pulse-skipping mode.
INTVCC Regulator
The LTC3603 features an integrated P-channel low dropout
linear regulator (LDO) that supplies power to the INTVCC
supply pin from the PVIN pin. This LDO supply has been
designed to deliver up to 35mA of load current for the
powering of the internal gate drivers and other internal
circuitry. A small external load may also be applied provided
that the total current from the INTVCC supply does not
exceed 35mA. The INTVCC pin should be bypassed with
no less than a 0.22μF ceramic capacitor. A 1μF ceramic
capacitor is suitable for most applications.
Topside MOSFET Driver Supply (BOOST Pin)
The LTC3603 uses a bootstrapped supply to power the
gate of the internal topside MOSFET (Figure 3). When the
topside MOSFET is off and the SW pin is low, diode DBST
charges capacitor CBST to the voltage on the INTVCC supply. In order to turn on the topside MOSFET, the voltage on
the BOOST pin is then applied to its gate. As the topside
MOSFET turns on, the SW pin rises to the PVIN voltage
3603fa
12
LTC3603
APPLICATIONS INFORMATION
and the BOOST pin rises to PVIN + INTVCC, thereby keeping the MOSFET fully enhanced. For most applications, a
0.22μF ceramic capacitor is appropriate for CBST. Schottky
diode DBST should have a reverse breakdown voltage that
is greater than PVIN(MAX).
To implement tracking, a resistor divider is placed between
an external supply (VX) and the TRACK/SS pin as shown
in Figure 5a. This technique can be used to cause VOUT to
ratiometrically track the VX supply (Figure 5b), according
to the following:
INTVCC
DBST
LTC3603
CINTVCC
BOOST
CBST
SW
VOUT RTA RA + RB
=
•
VX
RA RTA + RTB
3603 F03
Figure 3. Topside MOSFET Supply
For coincident tracking, as shown in Figure 5c, (VOUT =
VX during start-up),
Run and Soft-Start/Tracking Functions
The LTC3603 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 0.7V
puts the LTC3603 into a low quiescent current shutdown
mode (IQ < 1μA). When the RUN pin is greater than 0.7V,
the controller is enabled. The RUN pin can be driven directly
from logic as shown in Figure 4.
3.3V OR 5V
When the LTC3603 detects a fault condition (either
undervoltage lockout or overtemperature), the TRACK/SS
pin is quickly pulled to ground and the internal soft-start
timer is also reset. This ensures an orderly restart when
using an external soft-start capacitor.
RTA = RA, RTB = RB
Note that the 1.2μA current that is sourced from the
TRACK/SS pin will cause a slight offset in the voltage seen
on the TRACK/SS pin and consequently on the VOUT voltage during tracking. This VOUT offset due to the TRACK/SS
current is given by:
PVIN
LTC3603
4.7MΩ
RUN
LTC3603
VOS,TRK = (1µA) •
RTARTA RA + RB
•
RTA + RTB
RA
RUN
3603 F04
For most applications, this offset is small and has minimal
effect on tracking performance. For improved tracking accuracy, reduce the parallel impedance of RTA and RTB.
Figure 4. RUN Pin Interfacing
Soft-start and tracking are implemented by limiting the
effective reference voltage as seen by the error amplifier.
Ramping up the effective reference into the error amp in
turn causes a smooth and controlled ramp on the output
voltage of the converter. To use the default, internal 1ms
soft-start ramp, leave the TRACK/SS pin floating. Do not
tie the TRACK/SS pin to INTVCC or to PVIN. To increase the
soft-start time above 1ms, place a cap on the TRACK/SS pin.
A 1.2μA internal pull-up current will charge this capacitor,
resulting in a soft-start ramp time given by:
tSS = CSS •
VOUT
RB
VX
VFB
RTB
LTC3603
RA
TRACK/SS
RTA
3603 F05a
Figure 5a. Using the TRACK/SS Pin to Track VX
0.6 V
1.2µA
3603fa
13
LTC3603
APPLICATIONS INFORMATION
OUTPUT VOLTAGE
VX
VOUT
TIME
Figure 5b. Ratiometric Tracking
OUTPUT VOLTAGE
VX
VOUT
3603 F05b,c
TIME
Figure 5c. Coincident Tracking
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN operating current and I2R losses.
The VIN operating current loss dominates the efficiency loss
at very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents.
1. The VIN operating current comprises three components:
The DC supply current as given in the electrical characteristics, the internal MOSFET gate charge currents
and the internal topside MOSFET transition losses. The
MOSFET gate charge current results from switching the
gate capacitance of the internal power MOSFET switches.
The gates of these switches are driven from the INTVCC
14
supply. Each time the gate is switched from high to
low to high again, a packet of charge, dQ, moves from
INTVCC to ground. The resulting dQ/dt is the current
out of INTVCC that is typically larger than the DC bias
current. In continuous mode, the gate charge current
can be approximated by IGATECHG = f(9.5nC). Since the
INTVCC voltage is generated from VIN by a linear regulator, the current that is internally drawn from the INTVCC
supply can be treated as VIN current for the purposes
of efficiency considerations.
Transition losses apply only to the internal topside
MOSFET and become more prominent at higher input
voltages. Transition losses can be estimated from:
Transition Loss = (1.7) VIN2 • IO(MAX) • (120pF) • f
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode, the average output current flowing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current:
I2R Loss = IO2(RSW + RL)
Other losses, including CIN and COUT ESR dissipative
losses and inductor core losses, generally account for
less than 2% of the total power loss.
Thermal Considerations
In most applications, the LTC3603 does not dissipate much
heat due to its high efficiency. But, in applications where the
LTC3603 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
3603fa
LTC3603
APPLICATIONS INFORMATION
To prevent the LTC3603 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TR = (PD) • (θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3603 in dropout at an
input voltage of 8V, a load current of 2.5A and an ambient
temperature of 70°C. From the Typical Performance graph
of Switch Resistance, the RDS(ON) of the top switch at 70°C
is approximately 85mΩ. Therefore, power dissipated by
the part is:
PD = (ILOAD2)(RDS(ON)) = (2.5A)2(85mΩ) = 0.53W
For the MSOP package, the θJA is 45°C/W. Thus, the junction temperature of the regulator is:
TJ = 70°C + (0.53W)(45°C/W) = 93.85°C
which is below the maximum junction temperature of
125°C.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD•(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components and output capacitor shown in the
front page application will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3603 in
an application with the following specifications: VIN =
12V, VOUT = 3.3V, IOUT(MAX) = 2.5A, IOUT(MIN) = 100mA,
f = 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
1.15 • 1011
– 10k = 105k
ROSC =
1MHz
Next, calculate the inductor value for about 40% ripple
current at maximum VIN:
⎛
3.3V ⎞ ⎛ 3.3V ⎞
L=⎜
⎟ = 2.39µH
⎟ • ⎜ 1–
⎝ (1MHz ) (1A ) ⎠ ⎝ 12V ⎠
Using a 2.2μH inductor results in a maximum ripple current of:
⎛
⎞ ⎛ 3.3V ⎞
3.3V
ΔIL = ⎜
⎟ = 1.1A
⎟ • ⎜ 1–
⎝ (1MHz ) ( 2.2µH) ⎠ ⎝ 12V ⎠
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. In this application, a tantalum capacitor will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower
the total effective ESR. For this design, a 100μF ceramic
capacitor will be used. CIN should be sized for a maximum
current rating of:
IRMS = 2.5A •
3.3V
12V
•
– 1 = 1.12ARMS
12V
3.3V
Decoupling the PVIN pin with a 22μF ceramic capacitor is
adequate for most applications.
The output voltage can now be programmed by choosing
the values of R1 and R2. Choose R1 = 105k and calculate
R2 as:
⎛ VOUT ⎞
R2 = R1 ⎜
– 1⎟ = 472.5 k
⎝ 0.6 V ⎠
3603fa
15
LTC3603
APPLICATIONS INFORMATION
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
PGOOD
INTVCC
PVIN
ROSC
105k
CITH
1nF
PVIN
RT
D1
BOOST
CBST
0.22μF
RITH
4.32k
ITH
R1
105k
R2
475k
VIN
12V
CIN
22μF
CFB
10pF
LTC3603
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1
2.2μH
L1: VISHAY IHLP2525CZER2R2MO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TDK C3225X5ROJ107M
VOUT
3.3V
2.5A
COUT
100μF
3603 F06
Figure 6. 12V to 3.3V, 2.5A Regulator at 1MHz, Burst Mode Operation
Choose a standard value of R2 = 475k. The voltage on
the MODE pin will be set to 0.6V by tying the MODE pin
to the FB pin. This will set the burst current equal to approximately 1A. Figure 6 shows a complete schematic for
this design example.
How to Reduce SW Ringing
As with any switching regulator, there will be voltage ringing on the SW node, especially for high input voltages.
The ringing amplitude and duration is dependent on the
switching speed (gate drive), layout (parasitic inductance)
and MOSFET output capacitance. This ringing contributes
to the overall EMI, noise and high frequency ripple. One
way to reduce ringing is to optimize layout. A good layout
minimizes parasitic inductance. Adding an RC snubber
from SW to GND is also an effective way to reduce ringing.
Finally, adding a resistor (10Ω to 100Ω) in series with the
BOOST pin will slow down the MOSFET turn-on slew rate
and dampen ringing, but at the cost of reduced efficiency.
Note that since the IC is buffered from high frequency
transients by PCB and bondwire inductances, the ringing
by itself is normally not a concern for reliability.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3603. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3603.
2. Connect the (+) terminal of the input capacitor(s), CIN, as
close as possible to the PVIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVIN, INTVCC, VOUT, PGND, SGND, or any other
DC rail in your system).
3603fa
16
LTC3603
TYPICAL APPLICATIONS
1.8V, 2.5A Regulator at 1MHz, Burst Mode Operation
R3
845k
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
R4
ROSC
137k
105k
INTVCC
PGOOD
PVIN
PVIN
RT
CITH
1nF
D1
BOOST
CBST
0.22μF
RITH
4.32k
ITH
R1
105k
CFB
10pF
VIN
12V
CIN
22μF
R2
210k
LTC3603
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1
1μH
VOUT
1.8V
2.5A
COUT
100μF
s2
L1: VISHAY IHLP2525CZER1R0MO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TAIYO YUDEN AMK316BJ107ML
3603 TA02
1.2V, 2.5A Regulator at 750kHz, Burst Mode Operation
VIN
12V
CVCC
1μF
R3
RPG
845k 200k
SYNC/MODE
PGOOD
R4
137k
CITH
1nF
PVIN
RT
ITH
R2
105k
D1
BOOST
CBST
0.22μF
RITH
4.32k
10pF
INTVCC
PVIN
PGOOD
ROSC
143k
R1
105k
CIN
22μF
LTC3603
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1: VISHAY IHLP2525CZER1ROMO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TAIYO YUDEN AMK316BJ107ML
L1
1μH
VOUT
1.2V
2.5A
COUT
100μF
s2
3603 TA03
3603fa
17
LTC3603
TYPICAL APPLICATIONS
Efficiency vs Load Current,
1.8V Regulator at 1MHz, Burst Mode Operation
Efficiency vs Load Current,
1.2V Regulator at 750kHz, Burst Mode Operation
100
100
95
95
VIN = 7.2V
EFFICIENCY (%)
EFFICIENCY (%)
85
VIN = 7.2V
90
90
VIN = 12V
80
75
85
VIN = 12V
80
75
70
65
70
60
65
60
0.001
55
0.1
1
0.01
LOAD CURRENT (A)
50
0.001
10
0.01
0.1
1
LOAD CURRENT (A)
3603 TA04a
10
3603 TA04b
3.3V, 2.5A Regulator, Synchronized to 1.8MHz, Small Size
1.8MHz
EXT. CLK
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
PVIN
RT
CFB
10pF
R2
332k
D1
BOOST
CBST
0.22μF
ITH
R1
105k
INTVCC
PVIN
PGOOD
ROSC
69.8k
CITH
470pF RITH
2.94k
VIN
12V
CIN
22μF
LTC3603
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1: VISHAY IHLP2525CZER1ROMO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: MURATA GRM31CR60J476ME19
L1
1μH
VOUT
2.5V
2.5A
COUT
47μF
3603 TA05
3603fa
18
LTC3603
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev A)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
5.23
(.206)
MIN
2.845 p 0.102
(.112 p .004)
0.889 p 0.127
(.035 p .005)
8
1
1.651 p 0.102
(.065 p .004)
1.651 p 0.102 3.20 – 3.45
(.065 p .004) (.126 – .136)
0.305 p 0.038
(.0120 p .0015)
TYP
16
0.50
(.0197)
BSC
4.039 p 0.102
(.159 p .004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 p 0.076
(.011 p .003)
REF
16151413121110 9
DETAIL “A”
0o – 6o TYP
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1234567 8
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE16) 0608 REV A
3603fa
19
LTC3603
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.00 REF
2.45 p 0.05
2.45 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
4.00 p 0.10
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2.45 p 0.10
4.00 p 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 s 45o
CHAMFER
BOTTOM VIEW—EXPOSED PAD
2
2.00 REF
2.45 p 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 p 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3603fa
20
LTC3603
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/09
Changes to Absolute Maximum Ratings
PAGE NUMBER
2
Changes to Pin Configuration
2
Change to Electrical Characteristics
3
Text Changes to Pin Functions
6
Change to Block Diagram
7
Text Changes to Operation Section
8
Text Changes to Applications Information Section
10, 12, 15
“How to Reduce SW Ringing” Section Added
16
Additions to Related Parts
22
3603fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3603
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3601
15V, 1.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V,
IQ = 300μA, ISD < 14μA, 3mm × 3mm QFN16, MSOP16E
LTC3605
15V, 5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V,
IQ = 2mA, ISD < 15μA, 4mm × 4mm QFN24
LTC3609
32V, 6A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 32V, VOUT(MIN) = 0.6V,
IQ = 900μA, ISD < 15μA, 7mm × 8mm QFN52
LTC3612
6V, 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V,
IQ = 70μA, ISD < 1μA, 3mm × 4mm QFN20, TSSOP20E
LTC3412A
3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
IQ = 60μA, ISD < 1μA, TSSOP16E, 4mm × 4mm QFN16
LTC3413
3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator for DDR/
QDR Memory Termination
90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2,
IQ = 280μA, ISD < 1μA, TSSOP16E
LTC3414
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
IQ = 64μA, ISD < 1μA, TSSOP20E
LTC3415
7A (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V,
IQ = 450μA, ISD < 1μA, 5mm × 7mm QFN38
LTC3416
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
IQ = 64μA, ISD < 1μA, TSSOP20E
LTC3418
8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
IQ = 380μA, ISD < 1μA, 5mm × 7mm QFN38
LTC3602
10V, 2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4.5V to 10V, VOUT(MIN) = 0.6V,
IQ = 75μA, ISD < 1μA, TSSOP16E, 4mm × 4mm QFN20
LTC3608
18V, 8A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 18V, VOUT(MIN) = 0.6V,
IQ = 900μA, ISD < 15μA, 5mm × 7mm QFN52
LTC3610
24V, 12A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 24V, VOUT(MIN) = 0.6V,
IQ = 900μA, ISD < 15μA, 9mm × 9mm QFN64
LTC3611
32V, 10A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 32V, VOUT(MIN) = 0.6V,
IQ = 900μA, ISD < 15μA, 9mm × 9mm QFN64
ThinSOT is a trademark of Linear Technology Corporation.
3603fa
22 Linear Technology Corporation
LT 1209 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009