LMK03000 Family Precision Clock Conditioner with Integrated VCO General Description Features The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family. ■ ■ ■ ■ ■ ■ ■ ■ ■ phase noise contribution of -224 dBc/Hz VCO divider values of 2 to 8 (all divides) Channel divider values of 1, 2 to 510 (even divides) 3 LVDS and 5 LVPECL clock outputs Partially integrated loop filter Dedicated divider and delay blocks on each clock output Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) 200 fs RMS Clock generator performance (10 Hz to 20 MHz) with a clean input clock Part Data Converter Clocking Networking, SONET/SDH, DSLAM Wireless Infrastructure Medical Test and Measurement Military / Aerospace VCO Frequency Range (MHz) RMS Jitter (fs) LMK03000C LMK03000 Target Applications ■ ■ ■ ■ ■ ■ ■ Integrated VCO with very low phase noise floor ■ Integrated Integer-N PLL with outstanding normalized 400 1185 - 1296 800 LMK03000D 1200 LMK03001C 400 LMK03001 LMK03001D 1470 - 1570 800 1200 System Diagram 20211440 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 202114 www.national.com LMK03000 Family Precision Clock Conditioner with Integrated VCO March 26, 2008 LMK03000 Family Functional Block Diagram 20211401 www.national.com 2 LMK03000 Family Connection Diagram 48-Pin LLP Package 20211402 3 www.national.com LMK03000 Family Pin Descriptions Pin # Pin Name I/O 1, 25 GND - Ground 2 Fout O Internal VCO Frequency Output - Power Supply 3, 8, 13, 16, 19, 22, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10, 26, 30, 31, 33, 37, Vcc11, Vcc12, Vcc13, Vcc14 40, 43, 46 Description 4 CLKuWire I MICROWIRE Clock Input 5 DATAuWire I MICROWIRE Data Input 6 LEuWire I MICROWIRE Latch Enable Input 7, 34, 35 NC - No Connection to these pins 9, 10 LDObyp1, LDObyp2 - LDO Bypass 11 GOE I Global Output Enable 12 LD O Lock Detect and Test Output 14, 15 CLKout0, CLKout0* O LVDS Clock Output 0 17, 18 CLKout1, CLKout1* O LVDS Clock Output 1 20, 21 CLKout2, CLKout2* O LVDS Clock Output 2 23, 24 CLKout3, CLKout3* O LVPECL Clock Output 3 27 SYNC* I Global Clock Output Synchronization 28, 29 OSCin, OSCin* I Oscillator Clock Input; Should be AC coupled 32 CPout O Charge Pump Output 36 Bias I Bias Bypass 38, 39 CLKout4, CLKout4* O LVPECL Clock Output 4 41, 42 CLKout5, CLKout5* O LVPECL Clock Output 5 44, 45 CLKout6, CLKout6* O LVPECL Clock Output 6 47, 48 CLKout7, CLKout7* O LVPECL Clock Output 7 DAP DAP - Die Attach Pad is Ground www.national.com 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Symbol VCC Ratings Units -0.3 to 3.6 V VIN -0.3 to (VCC + 0.3) V TSTG -65 to 150 °C Lead Temperature (solder 4 s) TL +260 °C Junction Temperature TJ 125 °C Power Supply Voltage Input Voltage Storage Temperature Range Recommended Operating Conditions Symbol TA Min Typ Max Units Ambient Temperature Parameter -40 25 85 °C Power Supply Voltage VCC 3.15 3.3 3.45 V Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV. Package Thermal Resistance Package θJA θJ-PAD (Thermal Pad) 48-Lead LLP (Note 3) 27.4° C/W 5.8° C/W Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout. 5 www.national.com LMK03000 Family Absolute Maximum Ratings (Notes 1, 2) LMK03000 Family Electrical Characteristics (Note 4) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Symbol Parameter Conditions Min Typ Max Units Current Consumption ICC ICCPD Entire device; CLKout0 & CLKout4 enabled; no divide; no delay. Power Supply Current (Note 5) Power Down Current 161.8 mA Entire device; All Outputs Off (no emitter resistors placed) 86 POWERDOWN = 1 1 mA Reference Oscillator Reference Oscillator Input Frequency fOSCinsquare Range for Square Wave VOSCinsquare Square Wave Input Voltage for OSCin and OSCin* 1 200 MHz 0.2 1.6 Vpp 40 MHz AC coupled; Differential (VOD) PLL fCOMP Phase Detector Frequency VCPout = Vcc/2, PLL_CP_GAIN = 1x ISRCECPout Charge Pump Source Current 100 VCPout = Vcc/2, PLL_CP_GAIN = 4x 400 VCPout = Vcc/2, PLL_CP_GAIN = 16x 1600 VCPout = Vcc/2, PLL_CP_GAIN = 32x 3200 µA PLL (Continued) VCPout = Vcc/2, PLL_CP_GAIN = 1x -100 VCPout = Vcc/2, PLL_CP_GAIN = 4x -400 VCPout = Vcc/2, PLL_CP_GAIN = 16x -1600 VCPout = Vcc/2, PLL_CP_GAIN = 32x -3200 μA ISINKCPout Charge Pump Sink Current ICPoutTRI Charge Pump TRI-STATE® Current 0.5 V < VCPout < Vcc - 0.5 V 2 ICPout%MIS Magnitude of Charge Pump Sink vs. Source Current Mismatch VCPout = Vcc / 2 TA = 25°C 3 % 0.5 V < VCPout < Vcc - 0.5 V TA = 25°C 4 % 4 % Magnitude of Charge Pump ICPoutVTUNE Current vs. Charge Pump Voltage Variation ICPoutTEMP Magnitude of Charge Pump Current vs. Temperature Variation PN10kHz PLL 1/f Noise at 10 kHz Offset (Note 6) Normalized to 1 GHz Output Frequency PLL_CP_GAIN = 1x -117 PLL_CP_GAIN = 32x -122 PN1Hz Normalized Phase Noise Contribution (Note 7) PLL_CP_GAIN = 1x -219 PLL_CP_GAIN = 32x -224 www.national.com 6 10 nA dBc/Hz dBc/Hz Parameter Conditions Min Typ Max LMK03000C/LMK03000/LMK03000D 1185 1296 LMK03001C/LMK03001/LMK03001D 1470 1570 Units VCO fFout VCO Tuning Range |ΔTCL| Allowable Temperature Drift for Continuous Lock pFout Output Power to a 50 Ω load driven by Fout KVtune Fine Tuning Sensitivity (Note 9) JRMSFout Fout RMS Period Jitter (12 kHz to 20 MHz bandwidth) After programming R15 for lock, no changes to output configuration are permitted to guarantee continuous lock. (Note 8) LMK03000C/LMK03000/LMK03000D; TA = 25 °C 3.3 LMK03001C/LMK03001/LMK03001D; TA = 25 °C 2.7 LMK03000C/LMK03000/LMK03000D 7 to 9 LMK03001C/LMK03001/LMK03001D 9 to 11 LMK03000C/LMK03001C 800 1200 Fout Single Side Band Phase Noise LMK03001C fFout = 1570 MHz (Note 10) LMK03001C fFout = 1470 MHz (Note 10) 7 MHz/V 400 LMK03000D/LMK03001D LMK03000C fFout = 1185 MHz (Note 10) °C dBm LMK03000/LMK03001 LMK03000C fFout = 1296 MHz (Note 10) L(f)Fout 125 MHz 10 kHz Offset -91.4 100 kHz Offset -116.8 1 MHz Offset -137.8 10 MHz Offset -156.9 10 kHz Offset -93.5 100 kHz Offset -118.5 1 MHz Offset -139.4 10 MHz Offset -158.4 10 kHz Offset -89.6 100 kHz Offset -115.2 1 MHz Offset -136.5 10 MHz Offset -156.0 10 kHz Offset -91.6 100 kHz Offset -116.0 1 MHz Offset -137.9 10 MHz Offset -156.2 fs dBc/Hz www.national.com LMK03000 Family Symbol LMK03000 Family Symbol Parameter Conditions Min Typ Max Units Clock Distribution Section (Note 11) - LVDS Clock Outputs (CLKout0 to CLKout2) JitterADD RL = 100 Ω Distribution Path = 765 MHz Bandwidth = 12 kHz to 20 MHz Additive RMS Jitter (Note 11) CLKoutX_MUX = Bypass (no divide or delay) 20 CLKoutX_MUX = Divided (no delay) CLKoutX_DIV = 4 fs 75 tSKEW CLKoutX to CLKoutY (Note 12) Equal loading and identical clock configuration RL = 100 Ω -30 ±4 30 ps VOD Differential Output Voltage RL = 100 Ω 250 350 450 mV ΔVOD Change in magnitude of VOD for complementary output states RL = 100 Ω -50 50 mV VOS Output Offset Voltage RL = 100 Ω 1.070 1.370 V ΔVOS Change in magnitude of VOS for complementary output states RL = 100 Ω -35 35 mV ISA ISB Clock Output Short Circuit Current single-ended Single-ended outputs shorted to GND -24 24 mA ISAB Clock Output Short Circuit Current differential Complementary outputs tied together -12 12 mA 1.25 Clock Distribution Section (Note 11) - LVPECL Clock Outputs (CLKout3 to CLKout7) JitterADD RL = 100 Ω Distribution Path = 765 MHz Bandwidth = 12 kHz to 20 MHz Additive RMS Jitter (Note 11) tSKEW CLKoutX to CLKoutY (Note 12) VOH Output High Voltage CLKoutX_MUX = Bypass (no divide or delay) 20 CLKoutX_MUX = Divided (no delay) CLKoutX_DIV = 4 Equal loading and identical clock configuration Termination = 50 Ω to Vcc - 2 V fs 75 -30 Termination = 50 Ω to Vcc - 2 V ±3 30 ps Vcc 0.98 V Vcc 1.8 V VOL Output Low Voltage VOD Differential Output Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage 0.8 V IIH High-Level Input Current VIH = Vcc -5.0 5.0 µA IIL Low-Level Input Current VIL = 0 -40.0 5.0 µA Vcc 0.4 RL = 100 Ω 660 810 965 mV Vcc V Digital LVTTL Interfaces (Note 13) 2.0 VOH High-Level Output Voltage IOH = +500 µA VOL Low-Level Output Voltage IOL = -500 µA VIH High-Level Input Voltage VIL Low-Level Input Voltage 0.4 V IIH High-Level Input Current VIH = Vcc -5.0 5.0 µA IIL Low-Level Input Current VIL = 0 -5.0 5.0 µA V 0.4 V Vcc V Digital MICROWIRE Interfaces (Note 14) www.national.com 1.6 8 Parameter Conditions Min Typ Max Units MICROWIRE Timing tCS Data to Clock Set Up Time See Data Input Timing tCH Data to Clock Hold Time tCWH Clock Pulse Width High tCWL tES 25 ns See Data Input Timing 8 ns See Data Input Timing 25 ns Clock Pulse Width Low See Data Input Timing 25 ns Clock to Enable Set Up Time See Data Input Timing 25 ns tCES Enable to Clock Set Up Time See Data Input Timing 25 ns tEWH Enable Pulse Width High See Data Input Timing 25 ns Note 4: The Electrical Characteristics table lists guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 5: See 3.5 for more current consumption / power dissipation calculation information. Note 6: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). Note 7: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if a low power or noisy source is used. Note 8: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature the device was initially programmed at, the ambient temperature can never drift outside the range of -40 °C ≤ TA ≤ 85 °C without violating specifications. For this specification to be valid, the programmed state of the device must not change after R15 is programmed. Note 9: The lower sensitivity indicates the typical sensitivity at the lower end of the tuning range, the higher sensitivity at the higher end of the tuning range Note 10: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB, assuming the device is not reprogrammed. Reprogramming R15 will run the frequency calibration routine for optimum phase noise. Note 11: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO. Note 12: Specification is guaranteed by characterization and is not tested in production. Note 13: Applies to GOE, LD, and SYNC*. Note 14: Applies to CLKuWire, DATAuWire, and LEuWire. Serial Data Timing Diagram 20211403 Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. It is recommended that the slew rate of CLKuWire, DATAuWire, and LEuWire should be at least 30 V/μs. 9 www.national.com LMK03000 Family Symbol LMK03000 Family Charge Pump Current Specification Definitions 20211431 I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = Vcc - ΔV I5 = Charge Pump Source Current at VCPout = Vcc/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage 20211432 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch 20211433 Charge Pump Output Current Magnitude Variation vs. Temperature 20211434 www.national.com 10 LVDS Peak to Peak Voltage (Single-Ended) LVPECL Peak to Peak Voltage (Differential) 20211407 20211408 LVDS Output Buffer Noise Floor (Note 16) LVPECL Output Buffer Noise Floor (Note 16) 20211409 20211410 Delay Noise Floor (Notes 16, 17) 20211412 Note 15: These plots show performance at frequencies beyond what the part is guaranteed to operate at to give the user an idea of the capabilities of the part, but they do not imply any sort of guarantee. Note 16: To estimate this noise, only the output frequency is required. Divide value and input frequency are not integral. Note 17: The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor due to the distribution section accounting for the delay nise can be calculated as: Total Output Noise = 10 × log(10Output Buffer Noise/10 + 10Delay Noise Floor/10). 11 www.national.com LMK03000 Family Typical Performance Characteristics (Note 15) LMK03000 Family be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0. The duty cycle of the LVDS and LVPECL clock outputs are shown in the table below. 1.0 Functional Description The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks. The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop filter bandwidths. The LMK03000 family has multiple options for VCO frequencies. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through an VCO Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family. VCO_DIV CLKoutX_MUX Duty Cycle Any Divided, or Divided and Delayed 50% 2, 4, 6, 8 Any 50% 3 Bypassed, or Delayed 33% 5 Bypassed, or Delayed 40% 7 Bypassed, or Delayed 43% 1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. The bypassed outputs will continue to operate normally. Shortly after the SYNC* pin goes high, the divided clock outputs are activated and will all transition to a high state simultaneously. All the outputs, divided and bypassed, will now be synchronized. Clocks in the bypassed state are not affected by SYNC* and are always synchronized with the divided outputs. The SYNC* pin must be held low for greater than one clock cycle of the output of the VCO Divider, also known as the distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more cycles. This means that the outputs will be low on the fifth rising edge of the distribution path. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution path clock cycles have passed, which is the fifth rising edge of the distribution path. See the timing diagram in Figure 1 for further detail. The clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4. To synchronize the outputs, after the low SYNC* event has been registered, it is not required to wait for the outputs to go low before SYNC* is set high. 1.1 BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. 1.2 LDO BYPASS To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor. 1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) The purpose of OSCin is to provide the PLL with a reference signal. Due to an internal DC bias the OSCin port should be AC coupled, refer to the System Level Diagram in the Application Information section. The OSCin port may be driven single-endedly by AC grounding OSCin* with a 0.1 µF capacitor. 1.4 LOW NOISE, FULLY INTEGRATED VCO The LMK03000 family of devices contain a fully integrated VCO. In order for proper operation the VCO uses a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the R15 register is programmed. Once R15 is programmed the temperature may not drift more than the maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not guaranteed to stay in lock. For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed. 20211404 FIGURE 1. SYNC* Timing Diagram 1.5 CLKout DELAYS Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay. The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock output synchronization is not guaranteed. 1.6 LVDS/LVPECL OUTPUTS By default all the clock outputs are disabled until programmed. Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may www.national.com 12 CLKoutX _EN bit EN_CLKout _Global bit GOE pin CLKoutX Output State 1 1 Low Low Don't care 0 Don't care Off 0 Don't care Don't care Off 1 High / No Connect Enabled 1 When an LVDS output is in the Off state, the outputs are at a voltage of approximately 1.5 volts. When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt. 1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pin provides an internal pull-up resistor as shown on the functional block diagram. If it is not terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit. By programming the PLL_MUX register to Digital Lock Detect Active High, the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not locked. 1.10 POWER ON RESET When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets all registers to their default values, see the programming section for more information on default register values. Voltage should be applied to all Vcc pins simultaneously. 1.11 DIGITAL LOCK DETECT The PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock, the RC delay is changed to approximately δ. To indicate an out of lock state, the phase error must become greater δ. The values of ε and δ are shown in the table below: ε 10 ns δ 20 ns To utilize the digital lock detect feature, PLL_MUX must be programmed for "Digital Lock Detect (Active High)" or "Digital Lock Detect (Active Low)." When one of these modes is programmed the state of the LD pin will be set high or low as determined by the description above as shown in Figure 2. When the device is in power down mode and the LD pin is programmed for a digital lock detect function, LD will show a "no lock detected" condition which is low or high given active high or active low circuitry respectively. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. 20211405 FIGURE 2. Digital Lock Detect Flowchart 13 www.national.com LMK03000 Family The function of this word is to divide the comparison frequency presented to the lock detect circuit by 4. 1.8 CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Global is set to 0. LMK03000 Family 2.0 General Programming Information The LMK03000 family of devices are programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. During programming, LEuWire is low and serial data is clocked in on the rising edge of CLKuWire (MSB first). When LE goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7, R11, and R13 to R15 need to be programmed for proper device operation. For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed. Any changes to the PLL R divider or OSCin require R15 to be programmed again to activate the frequency calibration routine. 2.1 RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to ensure the device is in a default state. It is not necessary to program R0 again, but if R0 is programmed again, the reset bit is programmed clear (RESET = 0). Registers are programmed in order with R15 being the last register programmed. An example programming sequence is shown below. • Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset bit is set in R0, the other R0 bits are ignored. — If R0 is programmed again, the reset bit is programmed clear (RESET = 0). • Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings. • Program R8 for optimum phase noise performance. • Program R9 with Vboost setting if necessary. Only needed to set Vboost = 1. • Program R11 with DIV4 setting if necessary. • Program R13 with oscillator input frequency and internal loop filter values • Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and PLL R divider. • Program R15 with PLL charge pump gain, VCO divider, and PLL N divider. Also starts frequency calibration routine. www.national.com 14 15 0 R6 0 0 R5 R7 0 R4 0 R2 0 0 R1 R3 0 R0 0 0 0 0 0 0 0 30 31 Register 0 0 0 0 0 0 0 0 29 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 27 2.2 REGISTER MAP RESET www.national.com 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 24 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 19 17 CLKout7 _MUX [1:0] CLKout6 _MUX [1:0] CLKout5 _MUX [1:0] CLKout4 _MUX [1:0] CLKout3 _MUX [1:0] CLKout2 _MUX [1:0] CLKout1 _MUX [1:0] CLKout0 _MUX [1:0] Data [27:0] 18 16 15 14 13 11 CLKout7_DIV [7:0] CLKout6_DIV [7:0] CLKout5_DIV [7:0] CLKout4_DIV [7:0] CLKout3_DIV [7:0] CLKout2_DIV [7:0] CLKout1_DIV [7:0] CLKout0_DIV [7:0] 12 10 9 8 7 5 CLKout7_DLY [3:0] CLKout6_DLY [3:0] CLKout5_DLY [3:0] CLKout4_DLY [3:0] CLKout3_DLY [3:0] CLKout2_DLY [3:0] CLKout1_DLY [3:0] CLKout0_DLY [3:0] 6 4 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 A2 A3 0 2 3 1 1 0 0 1 1 0 0 A1 1 1 0 1 0 1 0 1 0 A0 0 LMK03000 Family CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN 1 0 0 0 PLL_ CP_ GAIN [1:0] R9 www.national.com R11 R13 R14 R15 0 0 0 0 1 0 29 EN_CLKout_Global EN_Fout VCO_DIV [3:0] 0 0 0 1 0 0 1 1 0 0 0 0 0 0 23 24 25 0 0 0 0 26 0 0 0 0 27 POWERDOWN 0 0 0 1 28 0 0 0 21 PLL_MUX [3:0] 0 0 0 0 22 0 0 0 20 0 0 0 0 0 0 18 1 1 0 17 0 PLL_N [17:0] PLL_R [11:0] 0 1 0 Vbo ost 0 0 0 13 14 0 15 0 16 OSCin_FREQ [7:0] 19 DIV4 0 0 0 0 0 Register R8 30 31 0 16 VCO_ R4_LF [2:0] 0 0 0 12 0 1 1 11 0 0 0 10 VCO_ R3_LF [2:0] 0 1 0 9 0 0 1 8 0 0 0 0 0 7 0 0 0 5 0 0 0 0 VCO_ C3_C4_LF [3:0] 0 0 0 6 0 0 0 0 0 4 1 1 1 1 1 1 3 1 1 1 0 0 0 2 1 1 0 1 0 0 1 1 0 1 1 1 0 0 LMK03000 Family Default Register Settings after Power on Reset Bit Name Default Bit Value Bit State Bit Description Register Bit Location RESET 0 No reset, normal operation Reset to power on defaults CLKoutX_MUX 0 Bypassed CLKoutX mux mode CLKoutX_EN 0 Disabled CLKoutX enable CLKoutX_DIV 1 Divide by 2 CLKoutX clock divide CLKoutX_DLY 0 0 ps CLKoutX clock delay Vboost 0 Normal Mode Output Power Control R9 DIV4 0 PDF ≤ 20 MHz Phase Detector Frequency R11 OSCin_FREQ 10 10 MHz OSCin OSCin Frequency in MHz VCO_R4_LF 0 Low (~200 Ω) R4 internal loop filter values VCO_R3_LF 0 Low (~600 Ω) R3 internal loop filter values VCO_C3_C4_LF 0 C3 = 0 pF, C4 = 10 pF C3 and C4 internal loop filter values 7:4 EN_Fout 0 Fout disabled Fout enable 28 EN_CLKout_Global 1 Normal - CLKouts normal Global clock output enable 27 POWERDOWN 0 Normal - Device active Device power down PLL_MUX 0 Disabled Multiplexer control for LD pin PLL_R 10 R divider = 10 PLL R divide value 19:8 PLL_CP_GAIN 0 100 µA Charge pump current 31:30 2 Divide by 2 VCO divide value N divider = 760 PLL N divide value VCO_DIV PLL_N 760 2.3.1 RESET bit -- R0 only This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and RESET = 0. Mode 31 18:17 R0 to R7 16 15:8 7:4 16 15 21:14 R13 13:11 10:8 R14 26 23:20 R15 29:26 25:8 2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned. The Clock Output Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock Output Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. The actual Clock Output Divide value is twice the binary value programmed as listed in the table below. 2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed below. CLKoutX_MUX [1:0] R0 Clock Output Divider value CLKoutX_DIV[7:0] Added Delay Relative to Bypass Mode 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 1 2 (default) 0 Bypassed (default) 0 ps 0 0 0 0 0 0 1 0 4 1 Divided 100 ps 0 0 0 0 0 0 1 1 6 0 0 0 0 1 0 0 8 Delayed 400 ps (In addition to the programmed delay) 0 0 0 0 0 0 1 0 1 10 . . . . . . . . ... Divided and Delayed 500 ps (In addition to the programmed delay) 1 1 1 1 1 1 1 1 510 2 3 17 www.national.com LMK03000 Family Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7. 2.3 REGISTER R0 to R7 Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. LMK03000 Family 2.5.1 DIV4 -- High Phase Detector Frequencies and Lock Detect This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable output from the digital lock detect output in the case of a phase detector frequency frequency greater than 20 MHz. 2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurred in addition to the delay shown in the table below. DIV4 Digital Lock Detect Circuitry Mode 0 Phase Detector Frequency ≤ 20 MHz (default) CLKoutX_DLY[3:0] Delay (ps) 0 0 (default) 1 150 2 300 3 450 4 600 2.6 REGISTER R13 5 750 6 900 7 1050 8 1200 2.6.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4 These bits control the capacitor values for C3 and C4 in the internal loop filter. 9 1350 Loop Filter Capacitors VCO_C3_C4_LF[3:0] C3 (pF) C4 (pF) 0 0 (default) 10 (default) 1 0 60 2 50 10 3 0 110 4 50 110 5 100 110 6 0 160 7 50 160 8 100 10 9 100 60 CLKoutX State 10 150 110 11 150 Disabled (default) 12 to 15 1500 11 1650 1800 13 1950 14 2100 15 2250 2.3.5 CLKoutX_EN bit -- Clock Output Enables These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. CLKoutX_EN bit 0 Conditions EN_CLKout_Global bit = 1 GOE pin = High / No Connect 1 Divided by 4 Phase Detector Frequency > 20 MHz 1 10 12 Not divided 60 Invalid 2.6.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0] = 0 for optimum phase noise and jitter. Enabled 2.4 REGISTER R9 The programming of register R9 is optional. If it is not programmed the the bit Vboost will be defaulted to 0, which is the test condition for all electrical characteristics. VCO_R3_LF[2:0] R3 Value (kΩ) 2.4.1 Vboost -- Voltage Boost By enabling this bit, the voltage output levels for all clock outputs is increased. Also, the noise floor is improved 0 Low (~600 Ω) (default) 1 10 2 20 Typical LVDS Voltage Output (mV) Typical LVPECL Voltage Output (mV) 3 30 0 350 810 1 390 865 Vboost 40 5 to 7 Invalid 2.6.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2:0] = 0 for optimum phase noise and jitter. 2.5 REGISTER R11 This register only has one bit and only needs to be programmed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values. www.national.com 4 18 R4 Value (kΩ) PLL_MUX[3:0] 0 Low (~200 Ω) (default) 8 1 10 9 2 20 3 30 10 4 40 11 5 to 7 Invalid Output Type Invalid N Divider Output/2 (50% Duty Cycle) Push-Pull Invalid R Divider Output/2 (50% Duty Cycle) Push-Pull 12 to 15 2.6.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multiple of 1 MHz, then round to the closest value. LD Pin Function Invalid 2.7.3 POWERDOWN bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of the state of any of the other bits or pins. OSCin Frequency POWERDOWN bit Mode 1 1 MHz 0 Normal Operation (default) 2 2 MHz 1 Entire Device Powered Down ... ... 10 10 MHz (default) OSCin_FREQ[7:0] ... ... 200 200 MHz 201 to 255 Invalid 2.7.4 EN_CLKout_Global bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits. When this bit is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. EN_CLKout_Global bit Clock Outputs 2.7 REGISTER R14 0 All Off 2.7.1 PLL_R[11:0] -- R Divider Value These bits program the PLL R Divider and are programmed in binary fashion. Any changes to PLL_R require R15 to be programmed again to active the frequency calibration routine. 1 Normal Operation (default) 2.7.5 EN_Fout bit -- Fout port enable This bit enables the Fout pin. PLL R Divide Value PLL_R[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 Invalid 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 . . . . . . . . . . . . ... 0 0 0 0 0 0 0 0 1 0 1 0 10 (default) . . . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 1 1 4095 Output Type LD Pin Function 0 Hi-Z Disabled (default) 1 Push-Pull Logic High 2 Push-Pull Logic Low Fout Pin Status 0 Disabled (default) 1 Enabled 2.8 REGISTER R15 Programming R15 also activates the frequency calibration routine. 2.8.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value, N Total, is also influenced by the VCO Divider value. NTotal = PLL N Divider × VCO Divider. The VCO frequency is calculated as, fVCO = fOSCin × PLL N Divider × VCO Divider / PLL R Divider. Since the PLL N divider is a pure binary counter there are no illegal divide values for PLL_N [17:0] except for 0. 2.7.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes. PLL_MUX[3:0] EN_Fout bit PLL N Divider Value 3 Push-Pull Digital Lock Detect (Active High) PLL_N[17:0] Invalid Push-Pull Digital Lock Detect (Active Low) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 5 Push-Pull Analog Lock Detect 6 Open Drain NMOS Analog Lock Detect 7 Open Drain PMOS Analog Lock Detect 19 . . . . . . . . . . . . . . . . . . ... 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 760 (default) . . . . . . . . . . . . . . . . . . ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262143 www.national.com LMK03000 Family VCO_R4_LF[2:0] LMK03000 Family 2.8.2 VCO_DIV[3:0] -- VCO Divider These bits program the divide value for the VCO Divider. The VCO Divider follows the VCO output and precedes the clock distribution blocks. Since the VCO Divider is in the feedback path from the VCO to the PLL phase detector the VCO Divider contributes to the total N divide value, NTotal. NTotal = PLL N Divider × VCO Divider. The VCO Divider can not be bypassed. See the programming section on the PLL N Divider for more information on setting the VCO frequency. VCO Divider Value VCO_DIV[3:0] VCO Divider Value VCO_DIV[3:0] 0 1 1 1 1 0 0 0 7 8 1 0 0 1 Invalid . . . . ... 1 1 1 1 Invalid 2.8.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain These bits set the charge pump gain of the PLL. 0 0 0 0 Invalid PLL_CP_GAIN[1:0] Charge Pump Gain 0 0 0 1 Invalid 0 1x (default) 0 0 1 0 2 (default) 1 4x 0 0 1 1 3 2 16x 0 1 0 0 4 3 32x 0 1 0 1 5 0 1 1 0 6 www.national.com 20 LMK03000 Family 3.0 Application Information 3.1 SYSTEM LEVEL DIAGRAM 20211470 FIGURE 3. Typical Application Figure 3 shows an LMK03000 family device used in a typical application. In this setup the clock may be multiplied, reconditioned, and redistributed. Both the OSCin/OSCin* and CLKoutX/CLKoutX* pins can be used in a single-ended or a differential fashion, which is discussed later in this datasheet. The GOE pin needs to be high for the outputs to operate. One technique sometimes used is to take the output of the LD (Lock Detect) pin and use this as an input to the GOE pin. If this is done, then the outputs will turn off if lock detect circuit detects that the PLL is out of lock. The loop filter actually con- sists of seven components, but four of these components that for the third and fourth poles of the loop filter are integrated in the chip. The first and second pole of the loop filter are external. 3.2 BIAS PIN See section 1.1 for bias pin information. 3.3 LDO BYPASS See section 1.2 for LDO bypass information. 21 www.national.com LMK03000 Family 3.4 LOOP FILTER 20211471 FIGURE 4. Loop Filter The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in Figure 4. When the loop filter is designed, it must be stable over the entire frequency band, meaning that the changes in KVtune from the low to high band specification will not make the loop filter unstable. The design of the loop filter is application specific and can be rather involved, but is discussed in depth in the the Clock Conditioner Owner's Manual provided by National Semiconductor. When designing with the integrated loop filter of the LMK03000 family, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4. Both the www.national.com integrated loop filter resistors and capacitors (C3 and C4) also restrict how wide the loop bandwidth the PLL can have. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In some situations where spurs requirements are very stringent and there is margin on phase noise, it might make sense to design for a loop filter with integrated resistor values that are larger than their minimum value. 22 Table 3.5 - Block Current Consumption Current Consumption at 3.3 V (mA) Power Dissipated in device (mW) Power Dissipated in LVPECL emitter resistors (mW) 86.0 283.8 - Low clock buffer The low clock buffer is enabled anytime one of (internal) CLKout0 through CLKout3 are enabled 9 29.7 - High clock buffer The high clock buffer is enabled anytime one of the (internal) CLKout4 through CLKout7 are enabled 9 29.7 - Fout buffer, EN_Fout = 1 14.5 47.8 - LVDS output, Bypassed mode 17.8 58.7 - 40 72 60 17.4 38.3 19.1 0 0 - Block Condition Entire device, core current All outputs off; No LVPECL emitter resistors connected Output buffers LVPECL output, Bypassed mode (includes 120 Ω emitter resistors) LVPECL output, disabled mode (includes 120 Ω emitter resistors) LVPECL output, disabled mode. No emitter resistors placed; open outputs Divide circuitry per output Divide enabled, divide = 2 5.3 17.5 - Divide enabled, divide > 2 8.5 28.0 - Delay circuitry per output Delay enabled, delay < 8 5.8 19.1 - 9.9 32.7 - Entire device CLKout0 & CLKout4 enabled in Bypassed mode 161.8 474 60 Delay enabled, delay > 7 From Table 3.5 the current consumption can be calculated in any configuration. For example, the current for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) output in Bypassed mode can be calculated by adding up the following blocks: core current, low clock buffer, high clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switched in, then the additional current for these stages needs to be added as well. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout4) operating at 3.3 volts, we calculate 3.3 V × (86 + 9 + 9 + 17.8 + 40) mA = 3.3 V × 161.8 mA = 533.9 mW. Because the LVPECL output (CLKout4) has the emitter resistors hooked up and the power dissipated by these resistors is 60 mW, the total device power dissipation is 533.9 mW - 60 mW = 473.9 mW. When the LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL Voh & Vol typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW. 23 www.national.com LMK03000 Family calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3 V, TA = 25 °C. 3.5 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to LMK03000 Family 3.6 THERMAL MANAGEMENT Power consumption of the LMK03000 family of devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 5. More information on soldering LLP packages can be obtained at www.national.com. 3.7 TERMINATION AND USE OF CLOCK OUTPUTS (DRIVERS) When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: • Transmission line theory should be followed for good impedance matching to prevent reflections. • Clock drivers should be presented with the proper loads. For example: — LVDS drivers are current drivers and require a closed current loop. — LVPECL drivers are open emitter and require a DC path to ground. • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled. It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK03000 family, OSCin/OSCin* should be AC coupled because OSCin/ OSCin* biases the signal to the proper DC level, see Figure 3. This is only slightly different from the AC coupled cases described in 3.7.2 because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same, which is the receiver (OSCin/OSCin*) set the input to the optimum DC bias voltage (common mode voltage), not the driver. 20211473 3.7.1 Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 6. To ensure proper LVDS operation when DC coupling it is recommend to use LVDS receivers without fail-safe or internal input bias such as DS90LV110T. The LVDS driver will provide the DC bias level for the LVDS receiver. For operation with LMK03000 family LVDS drivers it is recommend to use AC coupling with LVDS receivers that have an internal DC bias voltage. Some fail-safe circuitry will present a DC bias (common mode voltage) which will prevent the LVDS driver from working correctly. This precaution does not apply to the LVPECL drivers. FIGURE 5. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 5 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 20211420 FIGURE 6. Differential LVDS Operation, DC Coupling For DC coupled operation of an LVPECL driver, terminate with 50 Ω to Vcc - 2 V as shown in Figure 7. Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as shown in Figure 8 for Vcc = 3.3 V. www.national.com 24 20211418 FIGURE 7. Differential LVPECL Operation, DC Coupling 20211419 FIGURE 9. Differential LVDS Operation, AC Coupling LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 10. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to Vcc and a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is a valid termination as shown in Figure 10 for Vcc = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 8. 20211421 FIGURE 8. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 20211417 FIGURE 10. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent 25 www.national.com LMK03000 Family 3.7.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level. When driving LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 9. LMK03000 Family When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a 50 ohm termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See 3.7.2). If the other driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 V DC) is expected for safe and proper operation. The internal 50 ohm termination the test equipment correctly terminates the LVPECL driver being measured as shown in . When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. 3.7.3 Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal. It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the LMK03000 family clock LVPECL drivers, the termination should still be 50 ohms to Vcc - 2 V as shown in Figure 11. Again the Thevenin equivalent circuit (120 Ω resistor connected to Vcc and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) is a valid termination as shown in Figure 12 for Vcc = 3.3 V. 20211415 FIGURE 11. Single-Ended LVPECL Operation, DC Coupling 20211414 FIGURE 13. Single-Ended LVPECL Operation, AC Coupling 3.7.4 Conversion to LVCMOS Outputs To drive an LVCMOS input with an LMK03000 family LVDS or LVPECL output, an LVPECL/LVDS to LVCMOS converter such as National Semiconductor's DS90LV018A, DS90LV028A, DS90LV048A, etc. is required. For best noise performance, LVPECL provides a higher voltage swing into input of the converter. 20211416 3.8 OSCin INPUT In addition to LVDS and LVPECL inputs, OSCin can also be driven with a sine wave. The OSCin input can be driven single-ended or differentially with sine waves. The configurations for these are shown in Figure 14 and Figure 15. FIGURE 12. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent 20211422 FIGURE 14. Single-Ended Sine Wave Input www.national.com 26 20211424 FIGURE 15. Differential Sine Wave Input 20211413 FIGURE 16. Recommended OSCin Power for Operation with a Sine Wave Input using an LMK03000 device with eight LMK01000 family devices up to 64 clocks may be distributed in many different LVDS / LVPECL combinations. It's possible to distribute more than 64 clocks by adding more LMK01000 family devices. 3.9 MORE THAN EIGHT OUTPUTS WITH AN LMK03000 FAMILY DEVICE The LMK03000 family devices include eight or less outputs. When more than 8 outputs are required the footprint compatible LMK01000 family may be used for clock distribution. By 27 www.national.com LMK03000 Family Figure 16 shows the recommended power level for sine wave operation for both differential and single-ended sources over frequency. The part will operate at power levels below the recommended power level, but as power decreases the PLL noise performance will degrade. The VCO noise performance will remain constant. At the recommended power level the PLL phase noise degradation from full power operation (8 dBm) is less than 2 dB. LMK03000 Family Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Ordering Information Order Number VCO Version LMK03000CISQ 400 fs LMK03000CISQX LMK03000ISQ LMK03000ISQX Performance Grade 1.24 GHz 800 fs LMK03000DISQE 1200 fs LMK03000DISQ LMK03000DISQX LMK03001CISQ 400 fs LMK03001CISQX LMK03001ISQ LMK03001ISQX 1.52 GHz 800 fs LMK03001DISQE LMK03001DISQ 1200 fs LMK03001DISQX www.national.com 28 Packing Package Marking 250 Unit Tape and Reel K3000CI 2500 Unit Tape and Reel K3000CI 250 Unit Tape and Reel K3000 I 2500 Unit Tape and Reel K3000 I 250 Unit Tape and Reel K3000DI 1000 Unit Tape and Reel K3000DI 2500 Unit Tape and Reel K3000DI 250 Unit Tape and Reel K3001CI 2500 Unit Tape and Reel K3001CI 250 Unit Tape and Reel K3001 I 2500 Unit Tape and Reel K3001 I 250 Unit Tape and Reel K3001DI 1000 Unit Tape and Reel K3001DI 2500 Unit Tape and Reel K3001DI LMK03000 Family Notes 29 www.national.com LMK03000 Family Precision Clock Conditioner with Integrated VCO Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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