TI CY74FCT240T 8-bit buffers/line drivers with 3-state output Datasheet

CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
CY54FCT240T . . . D PACKAGE
CY74FCT240T . . . Q OR SO PACKAGE
(TOP VIEW)
OEA
DA0
OB0
DA1
OB1
DA2
OB2
DA3
OB3
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OEB
OA0
DB0
OA1
DB1
OA2
DB2
OA3
DB3
CY54FCT240T . . . L PACKAGE
(TOP VIEW)
OB0
DA 0
OEA
VCC
OEB
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
CY54FCT240T
– 48-mA Output Sink Current
12-mA Output Source Current
CY74FCT240T
– 64-mA Output Sink Current
32-mA Output Source Current
3-State Outputs
DA1
OB1
DA2
OB2
DA3
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
OA0
DB0
OA1
DB1
OA2
OB 3
GND
DB 3
OA 3
DB 2
D
description
The ’FCT240T devices are octal buffers and line
drivers designed to be employed as memory
address
drivers,
clock
drivers,
and
bus-oriented transmitters/receivers. These devices provide speed and drive capabilities equivalent to their
fastest bipolar logic counterparts, while reducing power consumption. The input and output voltage levels allow
direct interface with TTL, NMOS, and CMOS devices without external components.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
4.3
CY74FCT240CTSOC
Tape and reel
4.3
CY74FCT240CTSOCT
Tape and reel
4.3
CY74FCT240CTQCT
Tube
4.8
CY74FCT240ATSOC
Tape and reel
4.8
CY74FCT240ATSOCT
Tape and reel
4.8
CY74FCT240ATQCT
Tube
8
CY74FCT240TSOC
Tape and reel
8
CY74FCT240TSOCT
QSOP – Q
Tape and reel
8
CY74FCT240TQCT
CDIP – D
Tube
4.7
CY54FCT240CTDMB
CDIP – D
Tube
5.1
CY54FCT240ATDMB
LCC – L
Tube
5.1
CY54FCT240ATLMB
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
Tube
SOIC – SO
–40°C to 85°C
SPEED
(ns)
PACKAGE†
TA
TOP-SIDE
MARKING
FCT240C
FCT240C
FCT240A
FCT240A
FCT240
FCT240
CDIP – D
Tube
9
CY54FCT240TDMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OEA
OEB
D
OUTPUT
O
L
L
L
H
L
L
H
L
H
H
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance state
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
logic diagram (positive logic)
OEA
1
2
18
DA1
4
16
DA2
6
14
8
12
DA0
DA3
OEB
DB0
DB1
DB2
DB3
OA0
OA1
OA2
OA3
19
17
3
15
5
13
7
11
9
OB0
OB1
OB2
OB3
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
recommended operating conditions (see Note 2)
CY54FCT240T
CY74FCT240T
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–32
mA
IOL
TA
Low-level output current
48
64
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–55
2
125
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
4
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–40
V
V
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT240T
TYP† MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOZH
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 2.7 V
VOUT = 2.7 V
10
IOZL
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0.5 V
–10
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
0.3
3.3
0.55
IOL = 64 mA
0.3
0.2
0.55
0.2
±1
±1
10
–10
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
VCC = 5.25 V,
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
0.1
0.5
VCC = 5.5 V, One input switching at 50% duty cycle,
Outputs open, OEA = OEB = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
0.06
V
V
5
–60
V
V
2
IOH = –15 mA
IOL = 48 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT240T
TYP† MAX
MIN
–225
±1
0.2
0.1
0.2
0.5
2
2
µA
µA
µA
µA
µA
mA
µA
mA
mA
0.12
mA/
MHz
VCC = 5.25 V, One input switching at 50% duty cycle,
Outputs open, OEA = OEB = GND,
0.06
0.12
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
ICCD¶
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
CY54FCT240T
TYP† MAX
TEST CONDITIONS
MIN
One bit switching VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
at f1 = 10 MHz
at 50% duty cycle V = 3.4 V or GND
IN
IC#
VCC = 5.5 V,
Outputs open,
Eight bits
VIN = 0.2 V or
OEA = OEB = GND switching
VIN ≥ VCC – 0.2 V
at f1 = 2.5
2 5 MHz
at 50% duty cycle VIN = 3.4 V or GND
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
UNIT
mA
One bit switching VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
at f1 = 10 MHz
at 50% duty cycle V = 3.4 V or GND
IN
VCC = 5.25 V,
Outputs open,
Eight bits
VIN = 0.2 V or
OEA = OEB = GND switching
VIN ≥ VCC – 0.2 V
at f1 = 2.5
2 5 MHz
at 50% duty cycle VIN = 3.4 V or GND
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
Ci
5
10
5
10
pF
Co
9
12
9
12
pF
† Typical values are at VCC = 5 V, TA = 25°C.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
= Total supply current
IC
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
6
CY74FCT240T
TYP† MAX
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
CY54FCT240T
CY54FCT240AT
CY54FCT240CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
9
1.5
5.1
1.5
4.7
1.5
9
1.5
5.1
1.5
4.7
1.5
10.5
1.5
6.5
1.5
5.7
1.5
10.5
1.5
6.5
1.5
5.7
1.5
10
1.5
5.9
1.5
4.6
1.5
10
1.5
5.9
1.5
4.6
UNIT
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
POST OFFICE BOX 655303
CY74FCT240T
CY74FCT240AT
CY74FCT240CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
8
1.5
4.8
1.5
4.3
1.5
8
1.5
4.8
1.5
4.3
1.5
10
1.5
6.2
1.5
5
1.5
10
1.5
6.2
1.5
5
1.5
9.5
1.5
5.6
1.5
4.5
1.5
9.5
1.5
5.6
1.5
4.5
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
7
CY54FCT240T, CY74FCT240T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS017A – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9220301M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9220301MRA
ACTIVE
CDIP
J
20
1
TBD
5962-9220301MSA
ACTIVE
CFP
W
20
1
TBD
5962-9220302M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9220302MRA
ACTIVE
CDIP
J
20
1
TBD
5962-9220302MSA
ACTIVE
CFP
W
20
1
TBD
5962-9220303M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9220303MRA
ACTIVE
CDIP
J
20
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
5962-9220303MSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
5962-9221301MRA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9221303M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9221303MRA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9221305MRA
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CY54FCT240ATDMB
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
CY54FCT240ATLMB
ACTIVE
LCCC
FK
20
1
TBD
CY54FCT244ATDMB
ACTIVE
CDIP
J
20
1
TBD
CY54FCT244ATLMB
ACTIVE
LCCC
FK
20
1
TBD
CY54FCT244ATW
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
CY54FCT244CTDMB
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CY54FCT244CTW
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
CY54FCT244TDMB
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
CY54FCT244TLMB
ACTIVE
LCCC
FK
20
1
TBD
CY54FCT244TW
ACTIVE
CFP
W
20
1
TBD
CY74FCT240ATQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240ATQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240ATQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240ATSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240ATSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240ATSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240ATSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240ATSOCTE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240ATSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240CTQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240CTQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CY74FCT240CTQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
CY74FCT240CTSOC
ACTIVE
SOIC
DW
20
25
CY74FCT240CTSOCE4
ACTIVE
SOIC
DW
20
CY74FCT240CTSOCG4
ACTIVE
SOIC
DW
20
CY74FCT240CTSOCT
ACTIVE
SOIC
DW
CY74FCT240CTSOCTE4
ACTIVE
SOIC
CY74FCT240CTSOCTG4
ACTIVE
CY74FCT240TQCT
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240TQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240TQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT240TSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240TSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240TSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240TSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240TSOCTE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT240TSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244ATPC
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CY74FCT244ATPCE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CY74FCT244ATQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244ATQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244ATQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244ATSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244ATSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244ATSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244ATSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244ATSOCTE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CY74FCT244ATSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244CTQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244CTQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244CTQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244CTSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244CTSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244CTSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244CTSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244CTSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244DTQCTE4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244DTQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244DTSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTSOCTE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244DTSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TQCT
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244TQCTG4
ACTIVE
SSOP/
QSOP
DBQ
20
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CY74FCT244TSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TSOCT
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TSOCTE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY74FCT244TSOCTG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 3
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CY74FCT240ATQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT240ATSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT240CTQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT240CTSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT240TQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT240TSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT244ATQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT244ATSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT244CTQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT244CTSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT244DTQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT244DTSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
CY74FCT244TQCT
DBQ
20
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CY74FCT244TSOCT
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CY74FCT240ATQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT240ATSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT240CTQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT240CTSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT240TQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT240TSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT244ATQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT244ATSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT244CTQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT244CTSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT244DTQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT244DTSOCT
DW
20
SITE 41
346.0
346.0
41.0
CY74FCT244TQCT
DBQ
20
SITE 41
346.0
346.0
33.0
CY74FCT244TSOCT
DW
20
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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