ON ESD1014 Low capacitance esd protection array for high speed data lines protection Datasheet

ESD1014
Low Capacitance ESD
Protection Array for High
Speed Data Lines
Protection
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The ESD1014 transient voltage suppressor is designed to protect
high speed data lines from ESD, EFT, and lightning.
Features
• Low Capacitance (6 pF Maximum Between I/O Lines and GND)
• ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model
•
•
and Class C (Exceeding 400 V) per Machine Model
Protection for the Following IEC Standards:
IEC 61000−4−2 (ESD) Level 4 − 30 kV (Contact)
This is a Pb−Free Device
LOW CAPACITANCE
DIODE TVS ARRAY
PIN CONFIGURATION
AND SCHEMATIC
Typical Applications
•
•
•
•
•
10
1
2
3
4
5
High Speed Communication Line Protection
USB 1.1 and 2.0 Power and Data Line Protection
Digital Video Interface (DVI)
Monitors and Flat Panel Displays
T1/E1 and T3/E3
9
8
7
6
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Peak Power Dissipation
Ppk
450
W
Maximum Peak Pulse Current
8 x 20 mS @ TA = 25°C
IPP
25
A
Operating Junction Temperature Range
TJ
−40 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
16000
400
30000
V
Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Contact (ESD)
MARKING
DIAGRAM
1014
AYW
G
UDFN10
CASE 517AN
1014
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Device
ESD1014MUTAG
Package
Shipping†
UDFN10
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 0
1
Publication Order Number:
ESD1014/D
ESD1014
ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise specified)
Parameter
Symbol
Reverse Working Voltage
Conditions
VRWM
Breakdown Voltage
Min
Typ
(Note 1)
VBR
IT=1 mA, (Note 2)
5.0
Max
Unit
3.3
V
5.3
V
Reverse Leakage Current
IR
VRWM = 3.3 V
5.0
mA
Clamping Voltage
VC
IPP = 1 A
7.5
V
Clamping Voltage
VC
IPP = 10 A
9.0
V
Clamping Voltage
VC
IPP = 25 A
11
V
Maximum Peak Pulse Current
IPP
8x20 ms Waveform
25
A
Junction Capacitance
CJ
VR = 0 V, f=1 MHz between I/O Pins and GND
3.8
6.0
pF
Junction Capacitance
CJ
VR = 0 V, f=1 MHz between I/O Pins
1.5
3.0
pF
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC
or continuous peak operating voltage level.
2. VBR is measured at pulse test current IT.
TYPICAL PERFORMANCE CURVES
100
100
90
90
% OF PEAK PULSE CURRENT
PEAK POWER DISSIPATION (%)
(TJ = 25°C unless otherwise noted)
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
150
175
PEAK VALUE IRSM @ 8 ms
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
200
tr
0
20
40
60
t, TIME (ms)
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Pulse Derating Curve
Figure 2. 8 × 20 ms Pulse Waveform
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2
80
ESD1014
PACKAGE DIMENSIONS
UDFN10 2.6x2.6, 0.5P
CASE 517AN−01
ISSUE O
D
PIN ONE
REFERENCE
0.10 C
2X
2X
A
ÍÍÍ
ÍÍÍ
ÍÍÍ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
A3
0.10 C
A
10X
0.08 C
A1
SIDE VIEW
NOTE 4
10X
L
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.20
0.30
2.60 BSC
2.00
2.25
2.60 BSC
1.11
1.36
0.50 BSC
0.20
--0.30
0.40
C
SEATING
PLANE
SOLDERING FOOTPRINT*
D2
2.25
1
5
10X
E2
0.58
1.42 2.90
10X
K
10
6
e
BOTTOM VIEW
10X
b
0.10 C A
0.05 C
B
NOTE 3
10X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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ESD1014/D
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