HV1816 8-Channel High Voltage Analog Switch Ordering Information Package Options VPP VNN VSIG 28-pin Plastic DIP 28-lead Plastic Chip Carrier Die +80V -80V 130VP-P HV1816P HV1816PJ HV1816X Features ■ HVCMOS®` General Description Not recommended for new designs. Please use HV202 instead. technology ■ Up to 130V peak to peak output switching This device is an 8-channel high-voltage integrated circuit (HVIC) intended for use in applications requiring high voltage switching controlled by low voltage signals; e.g., ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. Using HVCMOS technology, this HVIC combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. ■ Output On-resistance typically 40 ohms ■ Low parasitic capacitances ■ DC to 10MHz analog signal frequency ■ -45dB typical output off isolation at 5MHz ■ CMOS logic circuitry for low power and excellent noise immunity ■ On-chip shift register, latch and clear logic circuitry Absolute Maximum Ratings* VDD Logic power supply voltage VPP - VNN supply voltage -0.5V to +18V 174V VPP Positive high voltage supply -0.5V to +90V VNN Negative high voltage supply +0.5V to -90V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel Storage temperature Power dissipation 1.5A -65°C to +150°C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-17 HV1816 Electrical Characteristics (over operating conditions, VPP = +80V, VNN = -80V and VDD = 15V unless otherwise noted) DC Characteristics Characteristics 0°C Sym min +25°C max min +70°C typ max min max Units Test Conditions Switch (ON) Resistance RONS 50 40 50 60 ohms ISW = 5mA, VSIG = 0V Switch (ON) Resistance RONS 35 25 35 45 ohms ISW = 200mA, VSIG = 0V Switch (ON) Resistance RONS 55 45 55 65 ohms VPP = +50V, VNN = -50V ISW = 5mA, VSIG = 0V Switch (ON) Resistance RONS 40 25 40 50 ohms VPP = +50V, VNN = -50V ISW = 200mA, VSIG = 0V Switch (ON) Resistance Matching ∆RONS 15 15 15 % VPP = +50V, VNN = -50V ISW = 5mA, VSIG = 0V Switch Off Leakage Per Switch ISOL 50 0.5 50 150 µA VSIG = VPP -10V thru 10KΩ with 8 SWS in parallel DC Offset Switch Off 500 100 500 500 mV RL = 100KΩ DC Offset Switch On 500 100 500 500 mV RL = 100KΩ 10 4.5 10 10 pF DC Bias = 40V f = 1MHz Pole to Pole Switch Capacitance CSW Logic Input Capacitance CIN Pos. HV Supply Current IPPQ 200 50 200 200 Neg. HV Supply Current INNQ -200 -50 -200 -200 Pos. HV Supply Current IPPQ 0.8 1.6 mA 1 SW ON, ISW = 5mA Neg. HV Supply Current INNQ -0.8 -1.6 mA VSIG = 0V Pos. HV Supply Current IPPQ 0.6 1.2 mA VPP = +50V, VNN = -50V, Neg. HV Supply Current INNQ -0.6 -1.2 mA 1 SW ON, ISW = 5mA 3.5 Switch Output Peak Current pF 1.5 µA ALL SWS OFF µA A VSIG ≤ 0.1% Duty Cycle, f = 10KHz Logic Supply Average Current IDD 4 6 mA Logic Supply Quiescent Current IDDQ 10 500 µA Data Out Source Current ISOR 0.7 0.8 0.9 0.7 mA VOUT = VDD - 0.7V Data Out Sink Current ISINK 0.7 0.8 0.9 0.7 mA VOUT = 0.7V fCLK = 3MHz AC Characteristics 0°C min max +25°C typ +70°C min max Characteristics Sym Set Up Time Before LE Rises tSD 260 ns Time Width of LE tWLE 300 ns min max Units Test Conditions Clock Delay Time to Data Out tDO 250 330 Turn On Time tON 5.0 2.5 5.0 5.0 µs RL =10KΩ Turn Off Time tOFF 10 5.0 10 10 µs RL =10KΩ Time Width of CL tWCL 150 -35 ns ns Off Isolation KO Max Clock Freq fCLK Set Up Time Data to Clock tSU 0 ns Hold Time Data from Clock th 35 ns Switch Crosstalk -45 dB 3.0 -45 KCR 13-18 MHz dB Signal Freq. = 5MHz 50% Duty Cycle fDATA = fCLK/2 Signal Freq. = 5MHz HV1816 Operating Conditions Symbol Parameter Value VDD Logic power supply voltage +10.0V to +15.5V VPP Positive high voltage supply +50V to +80V VNN Negative high voltage supply -50V to -80V VIH High level input voltage VDD -2V to VDD VIL Low-level input voltage 0 to 2.0V VSIG Analog signal voltage peak to peak VNN +15V to VPP -15V TA Operating free air-temperature 0° to 70°C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤VPP or floating during power up/down transition. Test Circuits VPP -15V VIN = 10 VP-P @5MHz ISOL 10KΩ RL VOUT VPP -15V VOUT 50Ω NC 50Ω VNN +15V +80V VPP VDD -80V VNN GND 15V +80V VPP VDD -80V VNN GND KCR = 20Log Switch OFF Leakage 15V +80V VPP VDD -80V VNN GND VOUT VIN TON/TOFF Crosstalk VIN = 10 VP-P @5MHz VOUT VOUT RL 100KΩ +80V VPP -80V VNN KO = 20Log VDD 15V GND RL +80V VPP VDD -80V VNN GND VOUT VIN OFF Isolation DC Offset ON/OFF 13-19 15V 15V HV1816 Logic Timing Waveforms DN DN – 1 DATA IN 50% LE 50% DN + 1 50% 50% tWLE tSD 50% CLOCK 50% t SU th tDO DATA OUT 50% tOFF VOUT OFF (TYP) tON 90% 10% ON CLR 50% 50% t WCL Logic Diagram LATCHES LEVEL SHIFTERS OUTPUT SWITCHES DIN D LE CL SW0 CLK D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 8 BIT SHIFT REGISTER DOUT VNN VPP CL VDD LE 13-20 HV1816 Truth Table LE CL SW0 L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON L L L OFF H L L ON D0 D1 D2 D3 D4 D5 D6 D7 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF H L L ON X X X X X X X X X H X X X X X X X X H L OFF OFF OFF OFF OFF OFF OFF OFF HOLD PREVIOUS STATE Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L → H transition CLK. 3. The clear input over rides all other inputs. 4. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 5. DOUT is high when switch 7 is on. 6. Shift register clocking has no effect on the switch states if LE is H. 13-21 HV1816 Pin Configurations 28-Pin DIP Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 VPP 10 VNN 11 N/C 12 GND 13 VDD 14 N/C Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Package Outlines Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 top view 28-pin DIP 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 VPP 10 VNN 11 N/C 12 GND 13 VDD 14 N/C 25 Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 24 23 22 21 20 26 18 27 17 28 16 1 15 2 14 3 13 4 12 5 6 7 8 9 10 top view 28-pin J-Lead Package 13-22 19 11