CML Semiconductor Products
CTCSS/DCS/SELCALL Processor
FX828
D/828/4 August 2009
1.0
•
•
•
•
•
Features
Fast CTCSS Detection
Full 23/24 Bit DCS Codec
Non-Predictive Tone Detection
Low Power 3.3V/5V Operation
Variable Gain Audio Filter
1.1
Provisional Issue
•
•
•
•
•
Programmable Tone Decoder
Programmable Comparator for RSSI
Programmable Modulator Drivers
Programmable Tone Encoders
Full Duplex CTCSS and Selcall
Brief Description
The FX828 is an innovative CTCSS, DCS and Selcall Codec, designed for the latest generation of Land
Mobile Radio equipment. Designed to complement the FX829, the FX828 has many advanced features
which assist the operation of modern SUBAUDIO and INBAND based signalling systems. The FX828 is
electrically, physically and software compatible with the FX818 and FX829. It permits manufacturers to
add new features to their equipment with minimal design changes.
The FX828 incorporates a programmable tone decoder which can be set to respond to between 1 and 15
CTCSS or Selcall tones with minimum software intervention. In addition, a 'Fast' CTCSS detector can
respond to a single programmed tone in 60 ms, or can be used to provide an output if any CTCSS tone is
present at the detector input. Two high resolution tone encoders perform accurate generation of any
CTCSS or Selcall tone in current use. Full 23 or 24 bit DCS encoding and decoding complements the
CTCSS/Selcall line-up. A timer is included which, for example, may be used for timing Selcall
transmissions and a comparator is provided to assist with carrier or RSSI monitoring. The device can
operate full duplex in all operating modes except for DCS.
The FX828 along with the FX818 and FX829 is offered in a choice of small SSOP, DIL and SOIC 24-pin
packages. It may be used with 3.0 to 5.5 volt supply.
© 2009 CML Microsystems Plc
CTCSS/DCS/SELCALL Processor
FX828
CONTENTS
Page
Section
1.0
Features ................................................................................................ 1
1.2
Block Diagram .................................................................................... 3
1.3
Signal List ............................................................................................ 4
1.3
Signal List ............................................................................................ 4
1.4
External Components ..................................................................... 6
1.4
External Components............................................................................. 6
1.5
General Description ......................................................................... 7
1.5.1
1.6
Software Description................................................................. 7
Application Notes ........................................................................... 20
1.6.1 General...................................................................................... 20
1.6.2 Transmitter ............................................................................... 20
1.6.3 Receiver (Decode).................................................................... 21
1.6.4 Receiver (Fast Detect) ............................................................. 21
1.6.5 Receiver (DCS Decoder).......................................................... 21
1.6.6 General Purpose Timer ........................................................... 22
1.6.7 Full Duplex Modes ................................................................... 22
1.6.8 Tx / Fast Rx Tone Table........................................................... 23
1.6.9 Rx Program Tone Table........................................................... 23
1.6.10 Tx Tone Program Table : Selcall ............................................ 24
1.6.11 Rx Tone Program Table : Selcall ............................................ 25
1.6.12 Tx DCS Code Table.................................................................... 26
1.7
Performance Specification ......................................................... 27
1.7.1
1.7.2
Electrical Performance ............................................................ 27
Packaging ................................................................................. 33
© 2009 CML Microsystems Plc
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D/828/4
CTCSS/DCS/SELCALL Processor
1.2
FX828
Block Diagram
Figure 1 Block Diagram
© 2009 CML Microsystems Plc
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D/828/4
CTCSS/DCS/SELCALL Processor
1.3
FX828
Signal List
Package
D2/D5/P4
Signal
Pin No.
Name
Description
Type
1
XTALN
O/P
The inverted output of the on-chip oscillator.
2
XTAL/CLOCK
I/P
The input to the on-chip oscillator, for external
Xtal circuit or clock.
3
SERIAL CLOCK
I/P
The "C-BUS" serial clock input. This clock,
produced by the µController, is used for transfer
timing of commands and data to and from the
device. See "C-BUS" Timing Diagram (Figure
4).
4
COMMAND DATA
I/P
The "C-BUS" serial data input from the
µController. Data is loaded into this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last,
synchronised to the SERIAL CLOCK. See
"C-BUS" Timing Diagram (Figure 4).
5
REPLY DATA
O/P
The "C-BUS" serial data output to the
µController. The transmission of REPLY DATA
bytes is synchronised to the SERIAL CLOCK
under the control of the CSN input. This 3-state
output is held at high impedance when not
sending data to the µController. See "C-BUS"
Timing Diagram (Figure 4).
6
CSN
I/P
The "C-BUS" data loading control function: this
input is provided by the µController. Data
transfer sequences are initiated, completed or
aborted by the CSN signal. See "C-BUS"
Timing Diagram (Figure 4).
7
IRQN
O/P
This output indicates an interrupt condition to
the µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection of
up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a highimpedance when inactive. An external pullup
resistor is required.
The conditions that cause interrupts are
indicated in the IRQ FLAG register and are
effective if not masked out by a corresponding
bit in the IRQ MASK register.
© 2009 CML Microsystems Plc
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D/828/4
CTCSS/DCS/SELCALL Processor
1.3
FX828
Signal List (continued)
Package
D2/D5/P4
Signal
Pin No.
Name
Description
Type
8
COMPOUT
O/P
The output of the comparator.
9
COMPIN
I/P
The input to the comparator.
10
A/D CAP 1
O/P
An internal reference voltage for the CTCSS A
to D. Decouple to VSS with an external
capacitor.
11
A/D CAP 2
O/P
An internal reference voltage for the DCS A to
D. Decouple to VSS with an external capacitor.
12
Vss
13
VBIAS
O/P
A bias line for the internal circuitry, held at ½
VDD. This pin must be decoupled by a capacitor
mounted close to the device pins.
14
RX AMP IN
I/P
The inverting input to the Rx input amplifier.
15
RX AMP OUT
O/P
The output of the Rx input amplifier and the
input to the audio filter section.
16
RX AUDIO OUT
O/P
Output of the Rx audio filter section.
17
TX AUDIO OUT
O/P
Output of the selcall tone generator.
18
SUM IN
I/P
Input to the audio summing amplifier.
19
SUM OUT
O/P
Output of the audio summing amplifier.
20
MOD1 IN
I/P
Input to MOD1 audio gain control.
21
TX SUB AUDIO OUT
O/P
Output of the CTCSS or DCS Tx tone generator.
22
MOD1
O/P
Output of MOD1 audio gain control.
23
MOD2
O/P
Output of MOD2 audio gain control.
24
VDD
Notes: I/P =
O/P =
© 2009 CML Microsystems Plc
Power
Power
The negative supply rail (ground).
The positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to VSS by a capacitor.
Input
Output
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CTCSS/DCS/SELCALL Processor
1.4
FX828
External Components
C1
C2
C3
C4
C5
C6
C7
C8
C9
Notes:
22pF
22pF
100pF
0.1µF
100pF
0.1µF
Note 2
0.1µF
1.0 to 3.3µF
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
R1
R2
R3
R4
R5
R6
R7
1MΩ
100kΩ
100kΩ
Note 2
22kΩ
Note 1
Note 1
±5%
±10%
±10%
±10%
±10%
±10%
±10%
X1
4.032MHz
(tolerance depends upon
system requirements)
1. R2, R6, R7 and C3 form the gain components for the Summing Amplifier. R6 and R7
should be chosen as required from the system specification, using the following formula:
Tx Sub Audio Gain
= −
Tx Audio Gain
= −
R2
R6
R2
R7
2. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be
chosen as required by the signal level, using the following formula:
Gain
= −
R3
R4
C7 x R4 should be chosen so as not to compromise the low frequency performance of this
product.
Figure 2 Recommended External Components
© 2009 CML Microsystems Plc
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CTCSS/DCS/SELCALL Processor
1.5
FX828
General Description
The FX828 is a signalling encoder/decoder for use in land mobile radio equipment, see Figure 1.
The transmitter section of this device has independently controllable tone generators for subaudio (CTCSS) and inband (Selcall) signalling. It also features a DCS code generator, which may
be used in place of the CTCSS tone generator.
The receiver section of the FX828 has a fast/predictive CTCSS tone detector which operates in
parallel with a DCS decoder and a CTCSS/Selcall tone decoder. The latter is switchable to
perform either CTCSS or Selcall tone decoding of a user-programmable set of up to 15 tones. In
the CTCSS mode it performs a more accurate (but slower) analysis of the tones detected by the
fast/predictive CTCSS tone detector, which is a single detector that is switchable to provide either
a fast response to any CTCSS tone (FAST DETECT mode) or a fast response to a single userprogrammed CTCSS tone (PREDICTIVE mode).
Other functions on the FX828 are a comparator with programmable threshold level, a general
purpose timer and a summing amplifier with two adjustable gain blocks, which may be used for
two point modulation, for example. All FX828 functions are controlled by an external µC over the
C-BUS interface, a serial interface designed to reduce interference levels in radio equipment.
1.5.1
Software Description
Address/Commands
Instructions and data are transferred, via "C-BUS", in accordance with the timing information
given in Figure 4.
Instruction and data transactions to and from the FX828 consist of an Address/Command (A/C)
byte followed by either:
(i)
(ii)
© 2009 CML Microsystems Plc
a further instruction or data (1 or 2 bytes) or
a status or Rx data reply (1 byte)
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D/828/4
CTCSS/DCS/SELCALL Processor
FX828
8-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
$01
GENERAL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SUBAUDIO
TX
ENABLE
TONE
DECODER
ENABLE
FAST
DETECT
ENABLE
0
SELCALL
TX
ENABLE
0
DCS
RX
ENABLE
RESET
$80
SIGNALLING
CONTROL
0
TONE DECODER BANDWIDTH
$82
SIGNALLING
MSB
SET-UP
BIT 3
DCS
OPTIONAL
MSB
BYTE 3
BIT 23
FAST CTCSS
MODE
LSB
BIT 2
BIT 1
BIT 0
TONE
DECODER
MODE
SUBAUDIO
DCS
TX MODE
23/24
BIT 18
BIT 17
BIT 16
BIT 10
BIT 9
BIT 8
BIT 3
BIT 2
BIT 1
BIT 0
DETECT/
PREDICTIVE
DCS BYTE 3
$85
BIT 22
BIT 21
BIT 20
BIT 19
DCS BYTE 2
$86
DCS
BYTE 2
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
DCS BYTE 1
$87
$88
DCS
LSB
BYTE 1
BIT 7
BIT 6
GENERAL
BPF
BPF
CONTROL
ENABLE
UN-MUTE
BIT 5
BIT 4
BPF
MSB
6dB
DAC
DAC
DAC
GP TIMER
GP TIMER
PAD
BIT 2
BIT 1
BIT 0
ENABLE
RE-CYCLE
BIT 2
BIT 1
BIT 0
GENERAL PURPOSE TIMER
GENERAL
$8B
$8E
PURPOSE
MSB
TIMER
BIT 7
IRQ
0
MASK
$9C
© 2009 CML Microsystems Plc
LSB
LSB
BIT 6
BIT 5
BIT 4
BIT 3
GP TIMER
COMP
COMP
TONE
CTCSS
IRQ
0 to 1
1 to 0
IRQ
FAST IRQ
MASK
IRQ MASK
IRQ MASK
MASK
MASK
DCS
0
IRQ
MASK
Reserved for later use
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CTCSS/DCS/SELCALL Processor
FX828
16-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 2
(D2)
BIT 1
(D1)
FAST RX
CTCSS (TX)
FREQUENCY (1)
NOTONE
0
0
MSB
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 1
BIT 0
CTCSS TX/FAST RX FREQUENCY
CTCSS TX/
FAST RX
FREQUENCY (2)
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LSB
MSB
BIT 0
BIT 11
TONE ADDRESS
RX TONE
$84
PROGRAM
MSB
(1)
BIT 3
BIT 2
BIT 1
BIT 2
TONE FREQUENCY
BIT 10
BIT 9
BIT 8
BIT 2
BIT 1
BIT 0
BIT 1
BIT 0
BIT 1
BIT 0
TONE FREQUENCY
RX TONE
PROGRAM
(2)
LSB
BIT 7
BIT 6
BIT 5
BIT 4
0
0
MOD 1
MSB
ENABLE
BIT 4
BIT 3
MOD 1
AUDIO
$8A
CONTROL
(1)
LSB
BIT 3
BIT 2
MOD 2
AUDIO
CONTROL
BIT 0
(D0)
CTCSS TX/FAST RX FREQUENCY
CTCSS TX/
$83
BIT 3
(D3)
0
0
(2)
MOD 2
MSB
ENABLE
BIT 4
0
MSB
LSB
BIT 3
BIT 2
SELCALL TX TONE
$8D
SELCALL TX
SELCALL
(1)
NOTONE
0
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 2
BIT 1
BIT 0
SELCALL TX TONE
SELCALL TX
(2)
© 2009 CML Microsystems Plc
LSB
BIT 7
BIT 6
BIT 5
9
BIT 4
BIT 3
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
Write Only Register Description
GENERAL RESET (Hex address $01)
The reset command has no data attached to it.
powersaved) states as listed below:
REGISTER NAME
SIGNALLING CONTROL
SELCALL & SUB-AUDIO STATUS
SIGNALLING SET-UP
CTCSS TX / FAST RX FREQUENCY
CTCSS TX / FAST RX FREQUENCY
RX TONE PROGRAM
RX TONE PROGRAM
DCS BYTE 3
DCS BYTE 2
DCS BYTE 1
GENERAL CONTROL
AUDIO CONTROL
AUDIO CONTROL
GENERAL PURPOSE TIMER
SELCALL TX
SELCALL TX
IRQ MASK
IRQ FLAG
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
HEX
ADDRESS
$80
$81
$82
$83
$84
$85
$86
$87
$88
$8A
$8B
$8D
$8E
$8F
It sets the device registers into the specific (all
BIT 7
(D7)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 6
(D6)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 5
(D5)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 4
(D4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 3
(D3)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 2
(D2)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 1
(D1)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 0
D0)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X = undefined
SIGNALLING CONTROL Register (Hex address $80)
This register is used to control the functions of the device as described below:
SUBAUDIO TX
ENABLE
(Bit 7)
Bit 7 should be set to “1” to enable the CTCSS/DCS subaudio transmitter. The
subaudio Tx type will depend on the state of the SUBAUDIO TX MODE (Bit 1
SIGNALLING SET-UP Register $82).
TONE DECODER
ENABLE
(Bit 6)
Bit 6 should be set to “1” to enable the CTCSS/Selcall tone decoder or the DCS
decoder. Note: See also Bit 0 for DCS decoder operation.
Bits 7 and 6 should not both be set to “1” when Bit 0 is set to “1” because the
DCS function is half-duplex only.
CTCSS FAST
DETECT ENABLE
(Bit 5)
When this bit is "1", the FAST CTCSS DETECT or FAST CTCSS PREDICTIVE
mode is enabled, depending upon the setting of FAST CTCSS MODE (Bit 3
SIGNALLING SET-UP Register, $82). When this bit is "0", both FAST CTCSS
DETECT and FAST CTCSS PREDICTIVE tone detectors are disabled.
SELCALL TX
ENABLE
(Bit 2)
When this bit is "1" the Selcall transmitter is enabled. When this bit is "0" the
Selcall transmitter is disabled and powersaved.
DCS RX ENABLE
(Bit 0)
When this bit is "1" and Bit 6 is “1”, the DCS decoder is enabled. When this bit
is "0" the DCS decoder is disabled.
The DCS decoder and the subaudio (CTCSS or DCS) transmitter should not be
enabled at the same time.
(Bits 4, 3, and 1)
© 2009 CML Microsystems Plc
Reserved for future use. These bits should be set to "0".
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D/828/4
CTCSS/DCS/SELCALL Processor
FX828
SIGNALLING SET-UP Register (Hex address $82)
This register is used to define the signalling parameters, as described below:
TONE DECODER
BANDWIDTH
(Bits 7, 6, 5 and 4)
These four bits set the bandwidth of the CTCSS/Selcall tone decoder according
to the table below:
Recommended for CTCSS
Recommended for CCIR
Recommended for ZVEI
FAST CTCSS MODE
(Bit 3)
Bit 7
1
1
1
1
1
1
1
1
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
BANDWIDTH
Will Decode
Will Not Decode
±1.1%
±2.4%
±1.3%
±2.7%
±1.6%
±2.9%
±1.8%
±3.2%
±2.0%
±3.5%
±2.2%
±3.7%
±2.5%
±4.0%
±2.7%
±4.2%
When CTCSS FAST DETECT ENABLE (Bit 5 SIGNALLING CONTROL
Register, $80) is "1", this bit selects the FAST CTCSS DETECT or the FAST
CTCSS PREDICTIVE mode, according to the table below:
DETECT/
PREDICTIVE
Bit 3
0
1
Function
DETECT mode
PREDICTIVE mode
If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are
deselected.
TONE DECODER
MODE
(Bit 2)
When this bit is "1" the CTCSS/Selcall tone decoder is set to detect inband
(Selcall) tones. When this bit is "0" the tone decoder is set to detect subaudio
(CTCSS) tones.
SUBAUDIO TX MODE
(Bit 1)
When this bit is "1" the subaudio transmitter will be set to transmit DCS signals,
if enabled. When this bit is "0" the subaudio transmitter will be set to transmit
CTCSS signals, if enabled.
DCS 23/24
(Bit 0)
When this bit is "1" the DCS transmitter and decoder are configured for a 23-bit
code. When this bit is "0" they are configured for a 24-bit code.
DCS BYTE 3 Register (Hex address $85)
DCS BYTE 2 Register (Hex address $86)
DCS BYTE 1 Register (Hex address $87)
These three bytes set the code that is transmitted or received in the DCS mode. The LSB bit 0 of the
DCS BYTE 1 is transmitted first and the last bit is the MSB bit 23 of DCS BYTE 3 in the 24-bit mode or bit
22 in the 23-bit mode.
© 2009 CML Microsystems Plc
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CTCSS/DCS/SELCALL Processor
FX828
GENERAL CONTROL Register (Hex address $88)
This register is used to control the functions of the device as described below:
BPF ENABLE
(Bit 7)
When this bit is "1" the audio band-pass filter is enabled. When this bit is "0" the
audio band-pass filter is disabled (powersaved).
BPF UN-MUTE
(Bit 6)
When this bit is "1" the audio band-pass filter output is switched to the RX
AUDIO OUT pin. When this bit is "0" the output of the filter is disconnected from
RX AUDIO OUT, which is then in a high impedance state.
This control, along with BPF ENABLE, allows the filter to power up and settle
internally before switching the output on, to avoid clicks when coming out of
powersave.
BPF 6dB PAD
(Bit 5)
When this bit is "1" a 6dB attenuator is inserted into the output of the audio
band-pass filter. When this bit is "0" the output of the audio band-pass filter is
not attenuated.
DAC
(Bits 4, 3 and 2)
These three bits set the level of the digital to analogue converter that feeds the
negative input of the comparator. The DAC can be set to one of eight levels
equally spaced between VSS and VBIAS, not including VSS, but including VBIAS,
i.e. with a 5V supply, the lowest level would be 312.5mV set by "000" in bits 2, 3
and 4 and the highest level would be 2.5V set by "111" in bits 2, 3 and 4.
TIMER ENABLE
(Bit 1)
When this bit goes to a "1" the general purpose timer is restarted and its internal
register is re-loaded from the value specified in the GENERAL PURPOSE
TIMER Register (Hex address $8B). It will then count down from the count held
in its internal register. When this bit is "0" the count down is disabled and the
last pre-programmed value is retained in the timer's internal register.
TIMER RE-CYCLE
(Bit 0)
When this bit is "1" the general purpose timer will re-load its internal register
from the value specified in the GENERAL PURPOSE TIMER Register (Hex
Address $8B) when the count in the internal register reaches zero (i.e. the
timeout has expired). It then restarts the count down, so that the timer
continuously cycles.
When this bit is "0" the general purpose timer will stop when the count in the
internal register reaches zero (i.e. the timeout has expired). The timer can only
be restarted by reloading a value into the GENERAL PURPOSE TIMER
Register (Hex address $8B).
If this bit is switched from "1" to "0" whilst the timer is enabled then the timer will
complete the present count before stopping.
GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B)
This register is used to preset the value of a countdown timer. Once a binary value has been loaded into
this register, it will be automatically transferred to an internal register within the timer. This internal
register is then decremented at each count interval (1ms) until it reaches zero. On reaching zero, the
GPT IRQ FLAG in the IRQ FLAG Register (Hex address $8F) is set to "1". An interrupt is generated on
the IRQN pin if the GPT IRQ MASK in the IRQ MASK Register (Hex address $8E) is "1" otherwise the
GPT IRQ FLAG remains set to "1" and no interrupt is generated.
© 2009 CML Microsystems Plc
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D/828/4
CTCSS/DCS/SELCALL Processor
FX828
When the internal register has reached a count of zero, the action of the timer depends on the setting of
the TIMER RE-CYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RECYCLE bit is "1" then the timer will re-load the countdown value from the GENERAL PURPOSE TIMER
Register and restart the countdown from this value. If the TIME RE-CYCLE bit is "0" then the timer will
stop and no further action or timer interrupts will take place until the GENERAL PURPOSE TIMER
Register is re-loaded. Loading the GENERAL PURPOSE TIMER with "0" will cause the timer circuitry to
be disabled (i.e. powersaved).
IRQ MASK Register (Hex address $8E)
This register is used to control the interrupts (IRQs) as described below:
(Bits 7 and 1)
Reserved for future use. These should be set to "0".
GPT IRQ MASK
(Bit 6)
When this bit is set to "1" it enables an interrupt that occurs when GPT
IRQ FLAG (Bit 6, IRQ FLAG Register, $8F) changes from "0" to "1".
When this bit is "0" the interrupt is masked.
COMP 0 to 1
IRQ MASK
(Bit 5)
When this bit is set to "1" it enables an interrupt that occurs when the
comparator output goes from "0" to "1". When this bit is set to "0" the
interrupt is masked.
COMP 1 to 0
IRQ MASK
(Bit 4)
When this bit is set to "1" it enables an interrupt that occurs when the
comparator output goes from "1" to "0". When this bit is set to "0" the
interrupt is masked.
TONE IRQ MASK
(Bit 3)
When this bit is set to "1" it enables an interrupt that occurs when the
TONE IRQ FLAG (Bit 3, IRQ FLAG Register, $8F) changes from "0" to "1".
When this bit is "0" the interrupt is masked.
CTCSS FAST IRQ
MASK
(Bit 2)
When this bit is set to "1" it enables an interrupt that occurs when the
CTCSS FAST IRQ FLAG (Bit 2, IRQ FLAG Register, $8F) changes from
"0" to "1". When this bit is "0" the interrupt is masked.
DCS IRQ MASK
(Bit 0)
When this bit is set to "1" it enables an interrupt that occurs when the DCS
DECODE/NO DECODE FLAG (Bit 7, SELCALL & SUB-AUDIO STATUS
Register $81) changes state. When this bit is set to "0" the interrupt is
masked.
CTCSS TX/FAST RX FREQUENCY Register (Hex address $83)
This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12
define the receive frequency the fast predictive detector is looking for according to the formula below.
When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS
tones according to the formula below.
When the fast detector and the transmitter are both enabled, the bits 0 to 12 define the receive frequency
the fast predictive detector is looking for and the frequency of the transmitted tone according to the
formula below (i.e. Tx tone = predictive tone).
A=
fXTAL (Hz)
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
© 2009 CML Microsystems Plc
13
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
When Bit 7 in byte (1) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the
bits 0 to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved
by disabling the SUBAUDIO Tx and the CTCSS FAST DETECT.
RX TONE PROGRAM Register (Hex address $84)
This is a 16-bit register. Byte (1) is sent first. The two bytes are used to program the centre frequencies of
up to 15 tones in either the audio or sub-audio band that will be decoded by the receiver.
Each tone is identified by its address in bits 7, 6, 5 and 4 of byte (1). The remaining 12 bits contain the
data representing the tone frequency according to the formula below. If a tone is not required the 12 bits
should be set to zero.
Byte 1
Bit
7
Bit
6
Bit
5
Bit
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit
3
Byte 2
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
<------------------------ N ----------------------->
<----------------------- R ------------------------>
N is the binary representation of the
following decimal number (n):
R is the nearest 6-bit binary
representation of (r), where:
SUBAUDIO (CTCSS)
SUBAUDIO (CTCSS)
n = INT (948982 x fTONE / fXTAL)
r = ((237245/fXTAL) - (n/(4 x fTONE))) x 8400
INBAND (SELCALL)
INBAND (SELCALL)
n = INT (83036 x fTONE / fXTAL)
r = ((20759/fXTAL) - (n/(4 x fTONE))) x 96000
Example: To program 100Hz when using the recommended 4.032MHz Xtal in SUBAUDIO
(CTCSS) mode.
n =
=
N =
INT (948982 x 100 / 4.032 x 10^6)
INT (23.536) = 23
010111 (binary)
r
((237245 / 4.032 x 10^6) - (23 / (4 x 100))) x 8400
11.26 (round up if exactly halfway)
=
=
R =
=
11
001011 (binary)
Thus the 12-bit code is 010111001011
The Hex address represented by bits 7, 6, 5 and 4 in byte (1) is used as the code to indicate which tone
has been decoded. This code appears in bits 3, 2, 1 and 0 of the SELCALL and SUB-AUDIO STATUS
Register (Hex address $81). The 15 programmed tones use Hex addresses $0 - $E.
© 2009 CML Microsystems Plc
14
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
AUDIO CONTROL Register (Hex address $8A)
This is a 16-bit register. Byte (1) is sent first. Bits 0 - 5 of the first byte in this register are used to set the
attenuation of the Modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to set
the attenuation of the Modulator 2 amplifier, according to the tables below:
BYTE 1
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BYTE 2
Mod. 1 Attenuation
Disabled (VBIAS)
>40dB
12.0dB
11.6dB
11.2dB
10.8dB
10.4dB
10.0dB
9.6dB
9.2dB
8.8dB
8.4dB
8.0dB
7.6dB
7.2dB
6.8dB
6.4dB
6.0dB
5.6dB
5.2dB
4.8dB
4.4dB
4.0dB
3.6dB
3.2dB
2.8dB
2.4dB
2.0dB
1.6dB
1.2dB
0.8dB
0.4dB
0dB
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mod. 2 Attenuation
Disabled (VBIAS)
>40dB
6.0dB
5.8dB
5.6dB
5.4dB
5.2dB
5.0dB
4.8dB
4.6dB
4.4dB
4.2dB
4.0dB
3.8dB
3.6dB
3.4dB
3.2dB
3.0dB
2.8dB
2.6dB
2.4dB
2.2dB
2.0dB
1.8dB
1.6dB
1.4dB
1.2dB
1.0dB
0.8dB
0.6dB
0.4dB
0.2dB
0dB
X = don't care
MOD1 ENABLE
(Bit 5, first byte)
When this bit is "1" the MOD1 attenuator is enabled.
When this bit is "0" the MOD1 attenuator is disabled (i.e. powersaved).
MOD2 ENABLE
(Bit 5, second byte)
When this bit is "1" the MOD2 attenuator and the SUMMING AMP are enabled.
When this bit is "0" they are both disabled (i.e. powersaved).
(Bits 7 and 6, first
and second bytes)
Reserved for future use. These should be set to "0".
SELCALL TX Register (Hex address $8D)
This is a 16-bit register. Byte (1) is sent first.
When the SELCALL transmitter is enabled, bits 0 to 12 control the frequency of the transmitted SELCALL
tones according to the formula overleaf:
© 2009 CML Microsystems Plc
15
D/828/4
CTCSS/DCS/SELCALL Processor
A=
FX828
fXTAL (Hz)
4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the
bits 0 to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved
by disabling the SELCALL Tx.
8-bit Read Only Registers
HEX
ADDRESS/
COMMAND
$81
$8F
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
SELCALL &
DCS
CTCSS
SUB-AUDIO
DECODE/
FAST
STATUS
NO DECODE
TONE
IRQ FLAG
0
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
BIT 1
BIT 0
RX TONE
0
TONE
MSB
DECODE
BIT 3
BIT 2
LSB
GP TIMER
COMP
COMP
TONE
CTCSS FAST
IRQ
0 to 1
1 to 0
IRQ
IRQ
FLAG
IRQ FLAG
IRQ FLAG
FLAG
FLAG
DCS
0
IRQ
FLAG
Read Only Register Description
SELCALL and SUB-AUDIO STATUS Register (Hex address $81)
This register is used to indicate the status of the device as described below:
DCS DECODE/NO
DECODE
(Bit 7)
When the DCS decoder is enabled this bit is continuously updated with the
result. A "1" indicates a successful decode (with 3 or less errors). A "0"
indicates a failure to decode.
CTCSS FAST TONE
(Bit 6)
When Bit 5 in the SIGNALLING CONTROL Register and Bit 3 in the
SIGNALLING SET-UP Register are set to enable FAST CTCSS DETECT mode,
this bit will be set to "1" if a periodic tone is detected. If no periodic tone is
detected this bit will be "0".
When bits 5 and 3 are set to enable FAST CTCSS PREDICTIVE mode, this bit
will be set to "1" if a periodic tone that matches the frequency programmed in
the CTCSS TX/FAST RX FREQUENCY Register is detected. If no match is
found this bit will be "0".
When Bit 5 in the SIGNALLING CONTROL Register is set to "0" this bit will be
"0".
(Bit 5)
Reserved for future use. This will be set to "0" but should be ignored by the
user's software.
TONE DECODE
(Bit 4)
This bit indicates the status of the tone decoder. A "1" indicates a tone has
been detected (TONE DECODE) and a "0" indicates the loss of the tone
(NOTONE).
© 2009 CML Microsystems Plc
16
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
TONE DECODE means that a tone has been decoded and its characteristics
are defined by the bandwidth (See SIGNALLING SET-UP Register bits 7, 6, 5
and 4) and the RX TONE number (See SELCALL and SUB-AUDIO STATUS
Register bits 3, 2, 1 and 0).
When Bit 6 in the SIGNALLING CONTROL Register is set to "0" the TONE
DECODE bit 4 will be set to "0".
Identification of a valid tone which is not in the pre-programmed list of up to 15
tones will cause the decoder to move to the TONE DECODE state with the RX
TONE address of "1111" in bits 3, 2, 1 and 0; indicating a valid, but
unrecognised, tone. Loss of tone, will cause the NOTONE timer to be started.
If loss of tone continues for the duration of the timeout period, then the decoder
will move to NOTONE state and the identification of pre-programmed tones will
start again. The time-out period is not user-adjustable.
RX TONE
(Bits 3, 2, 1 and 0)
These four bits hold a Hex number from $0 to $F. Numbers $0 to $E represent
the address of the tone decoded according to the tones programmed in the RX
TONE PROGRAM Register, $84. The Hex number $F indicates the presence
of any tone that is not described by DECODER BANDWIDTH (Bits 7, 6, 5 and 4,
SIGNALLING SET-UP Register, $82) and FREQUENCY (Bits 11 - 0, RX TONE
PROGRAM Register, $84).
IRQ FLAG Register (Hex address $8F)
This register is used to indicate when the device requires attention as below:
(Bits 7 and 1)
Reserved for future use. These will be set to "0" but should be ignored by user's
software.
GPT IRQ FLAG
(Bit 6)
When the general purpose timer has reached zero in its internal register, this bit
will be set to "1" to indicate the timeout has expired. This bit is cleared to "0" by
a read of the IRQ FLAG Register (Hex address $8F).
COMP 0 to 1
IRQ FLAG
(Bit 5)
When the comparator output goes from "0" to "1" (i.e. when the input voltage is
above the DAC output voltage) this bit will be set to "1" and an interrupt
generated (if bit 5 of the IRQ MASK Register $8E is set to "1"). This bit is set to
"0" when the IRQ FLAG Register $8F is read.
COMP 1 to 0
IRQ FLAG
(Bit 4)
When the comparator output goes from "1" to "0" this bit will be set to "1" and an
interrupt generated (if bit 4 of the IRQ MASK Register $8E is set to "1"). This bit
is set to "0" when the IRQ FLAG Register $8F is read.
TONE IRQ FLAG
(Bit 3)
When RX TONE DECODE (Bit 4, SELCALL and SUB-AUDIO STATUS
Register, $81) or Rx TONE (the decoded 4 bit tone address in Register $81)
changes state this bit will be set to "1". This bit is cleared to "0" by a read of the
IRQ FLAG Register (Hex address $8F).
CTCSS FAST IRQ
FLAG
(Bit 2)
When CTCSS FAST TONE (Bit 6, SELCALL and SUB-AUDIO STATUS
Register, $81) changes state this bit will be set to "1". This bit is cleared to "0"
by a read of the IRQ FLAG Register (Hex address $8F).
DCS IRQ FLAG
(Bit 0)
When DCS DECODE/NO DECODE (Bit 7 SELCALL and SUB-AUDIO STATUS
Register, $81) changes state this bit will be set to "1". This bit is cleared to "0"
by a read of the IRQ FLAG Register (Hex address $8F).
© 2009 CML Microsystems Plc
17
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
The flow chart shows the following modes of operation for the example below:
1.
2.
3.
4.
Decode
Decode and Fast Detect
Decode & Fast Predictive
Transmit, e.g. Tx = 100Hz
)
) e.g. Address 3 = 100Hz, bandwidth = ±2.7%, interrupt enabled
)
Note: $8X is the Hex address/command.
© 2009 CML Microsystems Plc
18
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
The flow chart shows the decoder, fast detect/fast predictive and transmitter enabled with the following
example.
1.
2.
3.
4.
Tx tone generator = 100Hz
Decoder programmed with 100Hz in address 3
Bandwidth setting = ±2.7%
Interrupt enabled
Note: $8X is the Hex address/command.
© 2009 CML Microsystems Plc
19
D/828/4
CTCSS/DCS/SELCALL Processor
1.6
FX828
Application Notes
1.6.1 General
The FX828 is intended for use in radio systems where signalling is required for functions such as
trunking, control, selective calling or group calling.
The CTCSS fast/predictive detector is useful for the detection of occupied channels indicating either the
presence of any sub-audio tone, or range of tones, depending if it is set in fast detect or predictive mode.
This will increase the efficiency of scanning and trunking systems, reducing the average time allocated to
assessing each channel.
The facility to decode any of up to 15 programmed tones allows the use of tones for various signalling
functions such as masking a free channel or identifying sub groups within a user's groups.
Adjustable decoder bandwidths permit certainty and signal to noise performance to be traded when
congestion or range limits the system performance.
1.6.2 Transmitters
The CTCSS transmitter is enabled with Bit 7 in the SIGNALLING CONTROL Register ($80) and bit 1 in
the SIGNALLING SET UP Register ($82).
The Tx frequency is set using Bit 0 to Bit 12 in the CTCSS TX/FAST RX FREQUENCY Register ($83)
using the formula below:
fXTAL (Hz)
A=
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the
bits 0 to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved
by disabling the SUBAUDIO Tx and the CTCSS FAST DETECT (Bits 7 and 5 in the SIGNALLING
CONTROL Register $80).
The SELCALL transmitter is enabled with Bit 2 in the SIGNALLING CONTROL Register ($80).
The Tx frequency is set using Bit 0 to Bit 12 in the SELCALL TX Register ($8D) using the formula below:
A=
fXTAL (Hz)
4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the
bits 0 to 12 to "0" puts the Selcall Tx into powersave and the output goes to VBIAS. Powersave is also
achieved by disabling the SELCALL TX ENABLE (Bit 2 in the SIGNALLING CONTROL Register $80).
The DCS transmitter is enabled by setting Bit 7 to "1" in the SIGNALLING CONTROL Register ($80)
having already set Bit 1 to "1" in the SIGNALLING SET UP Register ($82). Note that Bit 0 of this
SIGNALLING SET UP Register is used to select either 23-bit or 24-bit mode.
© 2009 CML Microsystems Plc
20
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
The Tx data is set in the DCS BYTE 3, DCS BYTE 2 and DCS BYTE 1 Registers ($85, $86 and $87).
Note that the DCS transmitter produces an inverted output. When the signal is fed through the summing
amp, in an inverting configuration, the correct polarity of the DCS signal will be restored (the modulator
gain blocks do not invert).
1.6.3 Receiver (CTCSS/Selcall Decoder)
The CTCSS/Selcall decoder should first be set up according to the desired characteristics. This entails
setting the TONE DECODER MODE Bit 2 of the SIGNALLING SET UP Register ($82), and setting the
TONE decoder bandwidth in the SIGNALLING SET-UP Register ($82), also programming the centre
frequencies of the desired tones in the RX TONE PROGRAM Register ($84). (It can hold up to 15
different tones). Any tone can be in any location. When the device is decoding, the tones are scanned in
the sequence of their location, i.e. $0 first and $E last. Once a tone is detected the remaining tones are
not checked. Therefore if two tones are close enough in frequency for their bandwidths to overlap then
the one in the lowest location will be detected.
The TONE IRQ MASK in the IRQ MASK Register ($8E) should also be set as required.
The TONE DECODER ENABLE in the SIGNALLING CONTROL Register ($80) should then be set to "1".
Whilst in the CTCSS/Selcall decoder mode the fast/predictive detector may be enabled (see below) (Bit 5
in the SIGNALLING CONTROL Register $80).
When the CTCSS/Selcall decoder detects a change in its present state an IRQ will be generated and Bit 3
of the IRQ FLAG Register ($8F) will indicate this. To reduce the likelihood of false or missed CTCSS
decodes, it is recommended that pre-emphasis and external audio pass-band filtering (300 to 3000Hz, for
example) be used in the Tx path.
The change that occurred can be read from Bit 4 of the SELCALL and SUB-AUDIO STATUS Register
($81) and if a tone is indicated by these bits then the number of that tone can be read from Bits 3, 2, 1
and 0 of the same register.
1.6.4 Receiver (CTCSS Fast/Predictive Detector)
This is used for detecting, in the fastest possible time, that sub-audio tones are present on the Rx
channel. Response time is optimised for speed at the expense of frequency resolution.
It can operate in parallel to the CTCSS/Selcall decoder. It is enabled using Bit 5 of the SIGNALLING
CONTROL Register ($80). It has an IRQ which may be unmasked with Bit 2 of the IRQ MASK Register
($8E). The FAST CTCSS MODE DETECT/PREDICTIVE Bit 3 in the SIGNALLING SET-UP Register
($82) allows for one of two alternatives in the FAST mode. In DETECT mode it will detect any periodic
tone in the sub-audio band and when in PREDICTIVE mode it will detect specific tones determined by the
frequency set in the CTCSS TX/FAST RX FREQUENCY Register ($83) and the fixed PREDICTIVE mode
bandwidth. Successful detection is indicated by the CTCSS FAST IRQ FLAG Bit 2 in the IRQ FLAG
Register ($8F), and the CTCSS FAST TONE Bit 6 in the SELCALL and SUB-AUDIO STATUS Register
($81).
1.6.5 Receiver (DCS Decoder)
The incoming signal is matched with the DCS code programmed into the DCS BYTE 1/2/3 Registers.
When the DCS decoder is enabled, the DCS DECODE/NO DECODE FLAG in Bit 7 of the SELCALL and
SUB-AUDIO STATUS Register ($81) will be set if the decode is successful (3 or fewer errors). A ''0" flag
indicates a failure to decode. This flag is updated for every bit of the incoming signal.
In order to detect the DCS turn-off code (134Hz), the CTCSS Tone Decoder should also be enabled and
programmed with this value. Once detected this will cause a CTCSS tone decode interrupt; the receiver
audio output should then be muted.
© 2009 CML Microsystems Plc
21
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
1.6.6 General Purpose Timer (GPT)
This may be used in conjunction with the CTCSS/Selcall decoder to form part of the decode algorithm or
as a timer for any other purpose. It has an 8-bit value in the GENERAL PURPOSE TIMER Register ($8B)
set in units of 1msec, an IRQ FLAG in Bit 6 of the IRQ FLAG Register ($8F) and an IRQ MASK in Bit 6 of
the IRQ MASK Register ($8E).
1.6.7 Full Duplex Modes
The only functions that must operate as half duplex are:
DCS Tx
or DCS Rx
DCS Tx
or CTCSS Tx
CTCSS decode or SELCALL decode
All other functions are totally independent and therefore a full duplex CTCSS or full duplex SELCALL
along with many other combinations are possible.
© 2009 CML Microsystems Plc
22
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
1.6.8 Tx / Fast Rx Tone Table : CTCSS
The following table lists the commonly used CTCSS tones and the corresponding values for programming
the transmitter frequency / fast predictive frequency register (Hex address $83).
Freq.
(Hz)
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
Byte 1
(hex)
E
E
D
D
C
C
B
B
B
A
A
A
9
9
9
8
Byte 2
(hex)
B1
34
B1
3B
C9
5A
EF
87
1F
C2
62
1B
D8
83
2F
E0
Freq.
(Hz)
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
Byte 1
(hex)
8
8
8
7
7
7
6
6
6
6
6
6
5
5
5
5
Byte 2
(hex)
93
49
1
BC
78
36
F7
BC
80
48
29
12
DD
AA
79
5D
Freq.
(Hz)
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
Byte 1
(hex)
5
5
5
5
4
4
4
4
4
4
4
4
4
3
3
Byte 2
(hex)
49
2F
1B
2
EF
D6
C4
AC
83
5D
4C
37
12
EF
E0
1.6.9 Rx Tone Program Tables : CTCSS
The following table lists the commonly used CTCSS tones together with the values for programming the
“RX TONE PROGRAM” register (Hex address $84).
N.B.
The values for byte 1 and 2 below apply to tone address 0 only.
depending on the location they are programmed into.
Freq.
(Hz)
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
Byte 1
(hex)
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
© 2009 CML Microsystems Plc
Byte 2
(hex)
D8
9
1B
4E
83
94
CB
2
14
4C
87
94
CB
7
45
82
Freq.
(Hz)
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
Byte 1
(hex)
6
6
7
7
7
8
8
8
8
9
9
9
9
A
A
A
23
Byte 2
(hex)
C0
D1
10
50
C0
2
44
86
C9
C
48
82
C6
B
84
C2
Freq.
(Hz)
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
These values will vary
Byte 1
(hex)
A
B
B
B
B
B
C
C
C
D
D
D
E
E
E
Byte 2
(hex)
C9
8
44
83
8A
C9
6
46
C3
41
48
89
8
88
C7
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
1.6.10 Tx Tone Program Table : Selcall
The following two tables list commonly used Selcall tonesets together with the values for programming the
‘SELCALL TX’ register ($8D).
Freq.
(Hz)
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
2110
EEA
Byte 1
(hex)
01
03
03
03
02
02
02
02
02
02
03
04
01
03
01
Byte 2
(hex)
FD
81
4A
17
E6
B9
8F
67
41
1E
BB
3C
C1
F9
DE
Freq.
(Hz)
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
885
2600
ZVEI 1
Byte 1
(hex)
01
03
03
03
02
02
02
02
01
01
01
04
04
04
01
Byte 2
(hex)
A4
B7
65
1A
D0
93
5C
27
F8
CA
68
DC
0F
73
84
© 2009 CML Microsystems Plc
Freq.
(Hz)
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
2110
CCIR
Byte 1
(hex)
01
03
03
03
02
02
02
02
02
02
01
04
01
03
01
Byte 2
(hex)
FD
81
4A
17
E6
B9
8F
67
41
1E
A4
3C
C1
F9
DE
Freq.
(Hz)
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
885
810
740
680
970
ZVEI 2
Byte 1
(hex)
01
03
03
03
02
02
02
02
01
01
04
04
04
05
04
Byte 2
(hex)
A4
B7
65
1A
D0
93
5C
27
F8
CA
73
DC
0F
CA
0F
24
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
1.6.11 Rx Tone Program Table : Selcall
The following two tables list commonly used Selcall tonesets together with the values for programming the
‘RX TONE PROGRAM’ register ($84) in each Tone Address location as shown.
Tone
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Freq.
(Hz)
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
2110
EEA
Byte 1
(hex)
A
15
26
36
46
57
67
78
88
99
A5
B4
CB
D5
EA
Byte 2
(hex)
A
C3
D
85
D1
4D
CB
4B
CD
84
51
C4
83
A
C5
Freq.
(Hz)
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
2110
CCIR
Byte 1
(hex)
A
15
26
36
46
57
67
78
88
99
AC
B4
CB
D5
EA
Byte 2
(hex)
A
C3
D
85
D1
4D
CB
4B
CD
84
44
C4
83
A
C5
Tone
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Freq.
(Hz)
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
885
2600
ZVEI 1
Byte 1
(hex)
C
15
25
36
47
57
68
79
8A
9B
AE
B4
C4
D4
ED
Byte 2
(hex)
44
53
D2
83
E
C8
86
49
42
43
46
14
D8
86
45
Freq.
(Hz)
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
885
810
740
680
970
ZVEI 2
Byte 1
(hex)
C
15
25
36
47
57
68
79
8A
9B
A4
B4
C3
D3
E4
Byte 2
(hex)
44
53
D2
83
E
C8
86
49
42
43
86
14
C8
80
D8
© 2009 CML Microsystems Plc
25
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
1.6.12 DCS Code Table
The following table gives a list of DCS codes together with the corresponding values (in Hex) which
should be programmed into the DCS BYTE registers for a 23-bit DCS sequence.
DCS
Code
023
025
026
031
032
043
047
051
054
065
071
072
073
074
114
115
116
125
131
132
134
143
152
155
156
162
165
172
174
205
223
226
243
244
245
251
261
263
265
271
306
311
DCS
Byte 3
($85)
76
6B
65
51
5F
5B
0F
7C
6F
5D
67
69
2E
74
35
72
7C
07
3D
33
2E
37
1E
44
4A
6B
31
05
18
6E
68
7B
45
1F
58
62
17
5E
43
79
0C
38
© 2009 CML Microsystems Plc
DCS
Byte 2
($86)
38
78
D8
F8
58
68
D8
A8
48
18
98
38
68
78
E8
B8
18
B8
38
98
D8
A8
C8
D8
78
C8
D8
F8
B8
98
E8
08
B8
A8
F8
78
78
88
C8
48
F8
D8
DCS
Byte 1
($87)
13
15
16
19
1A
23
27
29
2C
35
39
3A
3B
3C
4C
4D
4E
55
59
5A
5C
63
6A
6D
6E
72
75
7A
7C
85
93
96
A3
A4
A5
A9
B1
B3
B5
B9
C6
C9
DCS
Code
315
331
343
346
351
364
365
371
411
412
413
423
431
432
445
464
465
466
503
506
516
532
546
565
606
612
624
627
631
632
654
662
664
703
712
723
731
732
734
743
754
26
DCS
Byte 3
($85)
6C
23
29
3A
0E
68
2F
15
77
79
3E
4B
6C
62
7B
27
60
6E
3C
2F
41
0E
19
0C
5D
67
0F
01
72
7C
4C
24
39
22
0B
39
1E
10
0D
14
20
DCS
Byte 2
($86)
68
E8
78
98
B8
58
08
88
69
C9
99
99
59
F9
89
E9
B9
19
69
89
B9
39
E9
79
99
19
59
F9
89
29
39
79
39
B9
D9
89
49
E9
A9
D9
F9
DCS
Byte 1
($87)
CD
D9
E3
E6
E9
F4
F5
F9
09
0A
0B
13
19
1A
25
34
35
36
43
46
4E
5A
66
75
86
8A
94
97
99
9A
AC
B2
B4
C3
CA
D3
D9
DA
DC
E3
EC
D/828/4
CTCSS/DCS/SELCALL Processor
1.7
Performance Specification
1.7.1
Electrical Performance
FX828
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Min.
-0.3
-0.3
-30
-20
Max.
7.0
VDD + 0.3
+30
+20
Units
V
V
mA
mA
P4 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
1660
16.6
+125
+85
Units
mW
mW/°C
°C
°C
D2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
600
6.0
+125
+85
Units
mW
mW/°C
°C
°C
D5 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
1490
14.9
+125
+85
Units
mW
mW/°C
°C
°C
Max.
5.5
+85
4.0324032
Units
V
°C
MHz
Supply (VDD - VSS)
Voltage on any pin to VSS
Current into or out of VDD and VSS pins
Current into or out of any other pin
-55
-40
-55
-40
-55
-40
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (VDD - VSS)
Operating Temperature
Xtal Frequency
© 2009 CML Microsystems Plc
27
Min.
3.0
-40
4.0315968
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz
Audio Level 0dB ref = 308mVrms at 1kHz
VDD = 3.3V to 5.0V, Tamb = -40°C to +85°C.
Composite Signal = 308mVrms at 1kHz + 75mVrms Noise + 31mVrms Sub-Audio Signal
Noise Bandwidth = 5kHz Band Limited Gaussian
Notes
Min.
Typ.
Max.
Units
2
2
2
-
0.5
0.7
1.0
1.0
2.5
4.5
mA
mA
mA
2
-
0.7
3.0
mA
2
-
0.8
4.0
mA
2
2
2
-
1.0
1.1
1.7
1.5
4.5
7.5
mA
mA
mA
2
-
1.2
6.0
mA
2
-
1.3
6.5
mA
6
70%
-1.0
90%
-
-
30%
1.0
7.5
10%
10
VDD
VDD
µA
pF
VDD
VDD
µA
5
-
-26.0
-
dB
(Composite Signal)
(Composite Signal)
60
140
145
-
253
ms
ms
Hz
(Good Signal)
(Good Signal)
625
14
22
-
3000
ms
ms
Hz
58
2
-
116
edges
mVp-p
DC Parameters
At VDD = 3.3V
IDD (all powersaved)
IDD (FAST DETECT Enabled)
IDD (Rx Operating - DCS, FAST DETECT and
CTCSS or Selcall)
IDD (Tx Operating - DCS or Selcall or SUB
AUDIO)
IDD (Tx Operating - DCS and Selcall)
At VDD = 5V
IDD (all powersaved)
IDD (FAST DETECT Enabled)
IDD (Rx Operating - DCS, FAST DETECT and
CTCSS or Selcall)
IDD (Tx Operating - DCS or Selcall or SUB
AUDIO)
IDD (Tx Operating - DCS and Selcall)
"C-BUS" Interface
Input Logic "1"
Input Logic "0"
Input Leakage Current (Logic "1" or "0")
Input Capacitance
Output Logic "1" (IOH = 120µA)
Output Logic "0" (IOL = 360µA)
"Off" State Leakage Current (Vout = VDD)
AC Parameters
TONE Decoder
Sensitivity
CTCSS
Response Time
De-response Time
Frequency Range
SELCALL
Response Time
De-response Time
Frequency Range
(Pure Tone)
DCS Decoder
Bit-Rate Sync Time
Sensitivity
© 2009 CML Microsystems Plc
1
28
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
Notes
Min.
Typ.
Max.
Units
5
60.0
-26.0
56.0
-
253
dB
ms
Hz
5
7
60.0
-
-26.0
37.0
40.0
253
-
dB
ms
Hz
Hz
1
9
60.0
-1.0
-
2.0
253
0.2
+1.0
-
Hz
%
dB
%
SELCALL Encoder
Frequency Range
Tone Frequency Resolution
Tone Amplitude Tolerance
Total Harmonic Distortion
1
9
208
-1.0
-
2.0
3000
0.2
+1.0
-
Hz
%
dB
%
DCS Encoder
Bit Rate
Amplitude Tolerance
Amplitude
1
1
-1.0
134.4
871
+1.0
bits/s
dB
mVp-p
8
8
8
8
300
-2
33.0
-
0
-50.0
63
3000
+0.5
-
Hz
dB
dB
dB
dBp
kHz
10
-
2.0
500
-
kΩ
kΩ
10
-
70.0
5.0
6.0
-
dB
MHz
MΩ
kΩ
CTCSS Detector - Fast Detect
Sensitivity
(Pure CTCSS Tone)
Response Time
(Composite Signal)
Frequency Range
CTCSS Detector - Fast Predictive
Sensitivity
(Pure CTCSS Tone)
Response Time
(Composite Signal)
Frequency Range
Decode Bandwidth
CTCSS Encoder
Frequency Range
Tone Frequency Resolution
Tone Amplitude Tolerance
Total Harmonic Distortion
Audio Band-Pass Filter
Passband
Passband Gain (at 1.0kHz)
Passband Ripple (w.r.t. gain at 1.0kHz)
Stopband Attenuation
Residual Hum and Noise
Alias Frequency
Output Impedances
TX AUDIO OUT, TX SUB AUDIO
OUT and RX AUDIO OUT
) Enabled
) Disabled
Rx Amp and Summing Amp
Open Loop Gain
(I/P = 1mV at 100Hz)
Unity Gain Bandwidth
Input Impedance
(at 100Hz)
Output Impedance
(Open Loop)
© 2009 CML Microsystems Plc
29
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
Notes
Transmitter Modulator Drives:
Mod.1 Attenuator
Attenuation (at 0dB)
Cumulative Attenuation Error
(wrt attenuation at 0dB)
Output Impedance
Input Impedance (at 100Hz)
Min.
Typ.
Max.
Units
-0.3
-1.0
0
-
0.2
1.0
dB
dB
-
600
15.0
-
Ω
kΩ
-0.3
-0.6
0
-
0.2
0.6
dB
dB
-
600
-
Ω
1
-
1
255
-
ms
ms
4
40.0
10.0
20.0
-
-
ns
MΩ
dB
1
1
1
312.5
-30.0
-
312.5
10
1
2500
+30.0
-
mV
mV
mV
MΩ
kΩ
3
Mod.2 Attenuator
Attenuation (at 0dB)
Cumulative Attenuation Error
(wrt attenuation at 0dB)
Output Impedance
3
General Purpose Timer
Timing Period Range
Count Interval
Xtal/Clock Input
Pulse Width ('High' or 'Low')
Input Impedance (at 100Hz)
Gain (I/P = 1mVrms at 100Hz)
DAC
Range
Step Size
Step Accuracy
Input Impedance (COMPIN)
Output Impedance (COMPOUT)
Notes:
At VDD = 5.0V only. Signal levels or currents are proportional to VDD.
At Tamb = 25°C, not including any current drawn from the device pins by external
circuitry.
3. Small signal impedance, at VDD = 5.0V and Tamb = 25°C.
4. Timing for an external input to the XTAL/CLOCK pin.
5. With input gain components set as recommended in Figure 2.
6. IRQN pin.
7. From one tone to another tone.
8. See filter response (Figure 3).
9. Measured at MOD1 or MOD2 output.
10. SUBAUDIO, SELCALL and DCS.
1.
2.
© 2009 CML Microsystems Plc
30
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
10
0
-20
250Hz
Gain (dB)
-10
-30
-40
-60
10
3kHz
300Hz
-50
100
1000
10000
100000
Frequency (Hz)
Figure 3 Typical Audio Band-Pass Filter Frequency Response
Timing Diagrams
Figure 4 "C-BUS" Timing
© 2009 CML Microsystems Plc
31
D/828/4
CTCSS/DCS/SELCALL Processor
FX828
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz, VDD = 3.3V to 5.0V, Tamb = -40°C to +85°C.
Parameter
Notes
Min.
Typ.
Max.
Units
tCSE
"CS-Enable to Clock-High"
2.0
-
µs
tCSH
Last "Clock-High to CS-High"
4.0
-
µs
tHIZ
"CS-High to Reply Output 3-state"
-
2.0
µs
tCSOFF
"CS-High" Time between transactions
2.0
-
µs
tNXT
"Inter-Byte" Time
4.0
-
µs
tCK
"Clock-Cycle" time
2.0
-
µs
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB
(Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µController serial interface formats "C-BUS" compatible ICs are able
to work with either polarity SERIAL CLOCK pulses.
© 2009 CML Microsystems Plc
32
D/828/4
CTCSS/DCS/SELCALL Processor
1.7.2
FX828
Packaging
Figure 5 Mechanical Outline: Order as part no. FX828D2
Figure 6 Mechanical Outline: Order as part no. FX828D5
© 2009 CML Microsystems Plc
33
D/828/4
CTCSS/DCS/SELCALL Processor
1.7.2
FX828
Packaging (continued)
Figure 7 Mechanical Outline: Order as part no. FX828P4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage
from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit
patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product
specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this
product specification. Specific testing of all circuit parameters is not necessarily performed.