ON NCV7708FDWR2G Double hex driver Datasheet

NCV7708F
Double Hex Driver
The NCV7708F is a fully protected Hex Half Bridge Driver
designed specifically for automotive and industrial motion control
applications. The six low and high side drivers are freely configurable
and can be controlled separately. This allows for high side, low side,
and H−Bridge control. H−Bridge control provides forward, reverse,
brake, and high impedance states. The drivers are controlled via a
standard SPI interface.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Quiescent Current Sleep Mode
Six Independent High−Side and Six independent Low−Side Drivers
Integrated Freewheeling Protection (LS and HS)
Internal Upper and Lower Clamp Diodes
Configurable as H−Bridge Drivers
RDS(on) = 0.6 W (typ)
5 MHz SPI Control
SPI Valid Frame Detection
Compliance with 5 V and 3.3 V Systems
Overvoltage Lockout
Undervoltage Lockout
Fault Reporting
Current Limit
Overtemperature Protection
Internally Fused Lead in SOIC−28
SSOP−24 NB EPAD
These are Pb−Free Devices
Typical Applications
• Automotive
• Industrial
• DC Motor Management
NCV7708F
AWLYYWWG
SOIC−28
DW SUFFIX
CASE 751F
NCV7708F
AWLYYWWG
SSOP−24 NB EP
DQ SUFFIX
CASE 940AK
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCV7708FDWR2G*
SOIC−28W
(Pb−Free)
1000 /
Tape & Reel
NCV7708FDQR2G
SSOP−24N
(Pb−Free)
1000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*Contact your local sales representative for the
NCV7708F device availability in SOIC−28 package.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 2
1
Publication Order Number:
NCV7708F/D
NCV7708F
VS2
VS1
EN
VS1’
ANALOG
BIAS
ENABLE
CP
VS2’
DRIVE 1
VS
VS
Charge
Pump
High−Side
Driver
OUTH1
Waveshaping
Control
Logic
VCC
VRAIL POR
LOGIC
BIAS
VRAIL Low−Side
Driver
Fault
Detect
SPI
Control
VRAIL
SI
Fault
SO
16 Bit
Logic
and
Latch
SPI
SCLK
OUTL1
Waveshaping
Under−load
Overcurrent
Thermal
Warning/Shutdown
OUTH2
VS
DRIVE 2
CSB
OUTL2
CP
VS
OUTH3
DRIVE 3
CP
OUTL3
VS
OUTH4
VS1
Undervoltage
Lockout
VS2
DRIVE 4
OUTL4
CP
VS
VS1
Overvoltage
Lockout
OUTH5
DRIVE 5
VS2
CP
OUTL5
VS
OUTH6
DRIVE 6
CP
GND
Figure 1. Block Diagram
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2
OUTL6
NCV7708F
OUTL5
OUTH5
OUTH4
OUTL4
VS2
GND
GND
GND
GND
VS1
OUTL3
OUTH3
OUTH2
OUTL2
1
OUTH6
OUTL6
SI
SCLK
CSB
GND
GND
GND
GND
VCC
SO
EN
OUTL1
OUTH1
1
OUTL5
OUTH5
OUTH4
OUTL4
VS2
GND
GND
VS1
OUTL3
OUTH3
OUTH2
OUTL2
SOIC−28
OUTH6
OUTL6
SI
SCLK
CSB
GND
GND
VCC
SO
EN
OUTL1
OUTH1
SSOP−24
Figure 2. Pin Connection
PIN DESCRIPTION
Pin No.
SSOP−24
SOIC−28
Symbol
1
1
OUTL5
Output Low Side 5. Open drain output driver with internal reverse diode.
2
2
OUTH5
Output High Side 5. Open source output driver with internal reverse diode. Drain connected to
VS2’.
3
3
OUTH4
Output High Side 4. Open source output driver with internal reverse diode. Drain connected to
VS2’.
4
4
OUTL4
Output Low Side 4. Open drain output driver with internal reverse diode.
5
5
VS2
Power Supply input for the High−Side Output Drivers 4, 5, and 6.
6
6
GND
Ground
7
7
GND
Ground
−
8
GND
Ground
−
9
GND
Ground
8
10
VS1
Power Supply input for the High−Side Output Drivers 1, 2, and 3
9
11
OUTL3
Output Low Side 3. Open drain output driver with internal reverse diode.
10
12
OUTH3
Output High Side 3. Open source output driver with internal reverse diode. Drain connected to
VS1’.
11
13
OUTH2
Output High Side 2. Open source output driver with internal reverse diode. Drain connected to
VS1’.
12
14
OUTL2
Output Low Side 2. Open drain output driver with internal reverse diode.
13
15
OUTH1
Output High Side 1. Open source output driver with internal reverse diode. Drain connected to
VS1’.
14
16
OUTL1
Output Low Side 1. Open drain output driver with internal reverse diode.
15
17
EN
Enable. Input high wakes the IC up from sleep mode.
16
18
SO
Serial Output. 16 bit serial communications output.
17
19
VCC
Power supply input for Logic.
18
20
GND
Ground
19
21
GND
Ground
−
22
GND
Ground
−
23
GND
Ground
20
24
CSB
Chip Select Bar. Active low serial port operation.
21
25
SCLK
Serial Clock. Clock input for use with SPI communication.
22
26
SI
23
27
OUTL6
Output Low Side 6. Open drain output driver with internal reverse diode.
24
28
OUTH6
Output High Side 6. Open source output driver with internal reverse diode. Drain connected to
VS2’.
Description
Serial Input. 16 bit serial communications input.
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3
NCV7708F
MAXIMUM RATINGS
Rating
Value
Power Supply Voltage (VS1, VS2)
(DC)
(AC), t < 500 ms, Ivsx > −2 A
−0.3 to 40
−1.0
Output Pin OUTHx
(DC)
(AC – inductive clamping)
−0.3 to 40
−8.0
Output Pin OUTLx
(DC)
(AC), t < 500 ms, IOUTLx > −2 A
(AC Inductive Clamping)
−0.3 to 36
−1.0
45
Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
−0.3 to 5.5
Unit
V
V
V
Output Current (OUTL1, OUTL2, OUTL3, OUTL4, OUTL5, OUTL6, OUTH1, OUTH2, OUTH3, OUTH4,
OUTH5, OUTH6)
(DC) Vds = 12 V
(DC) Vds = 20 V
(DC) Vds = 40 V
(AC) Vds = 12 V, (50 ms pulse, 1 s period)
(AC) Vds = 20 V, (50 ms pulse, 1 s period)
(AC) Vds = 40 V, (50 ms pulse, 1 s period)
V
A
−1.5 to 1.5
−0.7 to 0.7
−0.25 to 0.25
−2.0 to 2.0
−0.9 to 0.9
−0.3 to 0.3
Electrostatic Discharge, Human Body Model, VS1, VS2, OUTx (Note 1)
4.0
kV
Electrostatic Discharge, Human Body Model, all other pins
2.0
kV
Electrostatic Discharge, Machine Model
200
V
Electrostatic Discharge, Charged Device Model
1.0
kV
Short Circuit Reliability Characterization (AEC−Q10x)
GRADE A
−
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−55 to 150
°C
MSL 3
MSL 2
−
260
°C
Moisture Sensitivity Level
SOIC−28
SSOP−24 EPAD
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested with a VS1/VS2 power supply common point.
2. For additional information, please see or download the ON Semiconductor Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
THERMAL CONDITIONS
Test Conditions, Typical Value
Board Details (Note 3)
Board Details (Note 4)
Unit
Junction−to−Lead (psi−JL8, YJL8) or Pins 6−9, 20−23
10
11
°C/W
Junction−to−Ambient (RqJA, qJA)
78
63
°C/W
Junction−to−Board (RYB)
−
2
°C/W
Junction−to−Ambient (RqJA)
−
54
°C/W
Junction−to−Lead (RYJL)
−
7
°C/W
Thermal Parameters
SOIC−28
SSOP−24 EPAD
3. 1−oz copper, 240 mm2 copper area, 0.062″ thick FR4. This is the minimum pad board size.
4. 1−oz copper, 986 mm2 copper area, 0.062″ thick FR4.
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4
NCV7708F
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Min
Max
Unit
Digital Supply Input Voltage (VCC)
VCCmax
3.15
5.25
V
Battery Supply Input Voltage (VS)
VSmax
5.5
28
V
DC Output Current (I(OUTLx), I(OUTHx))
DCmax
−
0.5
A
TJ
−40
150
°C
Rating
Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Symbol
Test Conditions
Supply Current (VS1 + VS2)
Sleep Mode (Note 5)
Ivs_sleep
Supply Current (VS1)
Active Mode
Ivs1_act
Characteristic
Min
Typ
Max
Unit
VS1 = VS2 = 13.2 V,
VCC = CSB = 5 V,
EN = SI = SCLK = 0 V
(−40°C to 85°C)
−
1.0
2.5
mA
EN = VCC,
5.5 V < VSx < 35 V
No Load
−
1.25
2.5
mA
CSB = VCC,
EN = SI = SCLK = 0 V
(−40°C to 85°C)
−
1.0
2.5
mA
−
1.5
3.0
mA
−
1.25
2.5
mA
−
2.55
2.9
V
3.7
4.1
4.5
V
GENERAL
Supply Current (VCC) − Sleep Mode (Note 5)
Ivcc_sleep
Supply Current (VCC) − Active Mode
Ivcc_act
EN = CSB = VCC,
SI = SCLK = 0 V
Supply Current (VS2)
Active Mode
Ivs2_act
EN = VCC,
5.5 V < VSx < 35 V
No Load
VCC Power−On−Reset Threshold
VCCpor
VSx Undervoltage Detection Threshold
VSuv
VSx Undervoltage Detection Hysteresis
VSuv_hys
100
365
450
mV
33
36.5
40.0
V
VSov_hys
1
2.5
4.0
V
VSx Overvoltage Detection Threshold
VSov
VSx Overvoltage Detection Hysteresis
Thermal Warning (Note 6)
Thermal Warning Hysteresis (Note 6)
Thermal Shutdown (Note 6)
Ratio of Thermal Shutdown to Thermal
Warning (Note 6)
VSx decreasing
VSx increasing
Ttw
120
140
170
°C
Ttw_hys
−
20
−
°C
Ttsd
155
175
195
°C
Ttsd/Ttw
1.05
1.20
−
−
−
−
0.6
−
1.3
1.7
−5.0
−
−
−1.0
−
−
OUTPUTS
Output High RDS(on) (source and sink)
Source Leakage Current
RDSon_src
RDSon_snk
Iout = −500 mA
25°C
−40°C < TJ < 150°C
Isrc
OUTH(1−6) = 0 V,
Vsx = 40 V, VCC = 5 V
OUTH(1−6) = 0 V,
Vsx = 13.2 V, VCC = 5V
W
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. For temperatures above 85°C, refer to graphs for VSx and VCC Sleep Current vs. Temperature on page 17.
6. Thermal characteristics are not subject to production test.
7. Refer to “Typical High−Side Negative Clamp Voltage” graph on page 17.
8. Current limit is active with and without overcurrent detection.
9. Not production tested.
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5
NCV7708F
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
−
−
5.0
−
−
1.0
−
0.9
1.3
V
OUTPUTS
Sink Leakage Current
Isnk
Power Transistor Body Diode Forward Voltage
Vbd_fwd
High−Side Clamping Voltage (Note 7)
Vclp_hs
OUTL(1−6) = 34 V,
VCC = 5 V
OUTL(1−6) = 34 V,
VCC = 5 V, T = 25°C
IF = 500 mA
−
−
−0.7
V
I(OUTLx) = 50 mA
36
−
45
V
Iul_ls
VCC = 5 V, Vsx = 13.2 V
2.0
8.0
16
mA
Under Load Detection Threshold (OUTHx)
Iul_hs
VCC = 5 V, Vsx = 13.2 V
−16
−8.0
−2.0
mA
Under Load Detection Delay Time
tul_del
VCC = 5 V, Vsx = 13.2 V
200
350
600
ms
Overcurrent Shutdown Threshold (OUTHx)
Iocsd_hs
VCC = 5 V, Vsx = 13.2 V,
Bit13 = 1
−2.0
−1.45
−1.1
A
Overcurrent Shutdown Threshold (OUTLx)
Iocsd_ls
VCC = 5 V, Vsx = 13.2 V,
Bit13 = 1
1.1
1.45
2.0
A
Low−Side Clamping Voltage
Vclp_ls
I(OUTHx) = −50 mA
mA
UNDER LOAD
Under Load Detection Threshold (OUTLx)
OVERCURRENT
Overcurrent Shutdown Delay Time
tocsd_0
tocsd_1
VCC = 5 V, Vsx = 13.2 V,
Bit13 = 0
Bit13 = 1
80
10
200
25
400
50
ms
ms
Current Limit (OUTHx)
Ilim_hs
VCC = 5 V, Vsx = 13.2 V
−5.0
−3.0
−2.0
A
Current Limit (OUTLx)
Ilim_ls
VCC = 5 V, Vsx = 13.2 V
2.0
3.0
5.0
A
Vinth
2.0
−
−
−
−
0.8
V
Input Hysteresis (SI, SCLK, CSB)
Vinhys_spi
100
300
600
mV
Input Hysteresis (EN)
Vinhys_en
100
400
800
mV
CURRENT LIMIT (Note 8)
LOGIC INPUTS (EN, SI, SCLK, CSB)
Input Threshold − High
Input Threshold − Low
Pull−down Resistance (EN, SI, SCLK)
Rpd
EN = SI = SCLK = VCC
50
125
250
kW
Pull−up Resistance (CSB)
Rpu
CSB = 0 V
50
125
250
kW
Input Capacitance (Note 9)
CIN
−
10
15
pF
VCC – 1.0
VCC – 0.7
−
V
LOGIC OUTPUT (SO)
Output High
Vsoh
Iout = 1 mA
Output Low
Vsol
Iout = −1.6 mA
Tri−state Leakage
Iso
CSB = VCC,
0 V < SO < VCC
Tri−state Input Capacitance (Note 9)
Cso
High Side Turn On Time
−
0.2
0.4
V
−10
−
10
mA
CSB = VCC,
0 V < VCC < 5.25 V
−
10
15
pF
thson
Vs = 13.2 V, Rload = 25 W
−
7.5
13
ms
High Side Turn Off Time
thsoff
Vs = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
Low Side Turn On Time
tlson
Vs = 13.2 V, Rload = 25 W
−
6.5
13
ms
TIMING SPECIFICATIONS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. For temperatures above 85°C, refer to graphs for VSx and VCC Sleep Current vs. Temperature on page 17.
6. Thermal characteristics are not subject to production test.
7. Refer to “Typical High−Side Negative Clamp Voltage” graph on page 17.
8. Current limit is active with and without overcurrent detection.
9. Not production tested.
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6
NCV7708F
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Low Side Turn Off Time
tlsoff
Vs = 13.2 V, Rload = 25 W
−
2.0
5.0
ms
High Side Rise Time
thsr
Vs = 13.2 V, Rload = 25 W
−
4.0
8.0
ms
High Side Fall Time
thsf
Vs = 13.2 V, Rload = 25 W
−
2.0
3.0
ms
Low Side Rise Time
tlsr
Vs = 13.2 V, Rload = 25 W
−
1.0
2.0
ms
Low Side Fall Time
tlsf
Vs = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
Non−Overlap Time
thsOfflsOn
High Side Turn Off To Low
Side Turn On
1.5
−
−
ms
Non−Overlap Time
tlsOffhsOn
Low Side Turn Off To High
Side Turn On
1.5
−
−
ms
TIMING SPECIFICATIONS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. For temperatures above 85°C, refer to graphs for VSx and VCC Sleep Current vs. Temperature on page 17.
6. Thermal characteristics are not subject to production test.
7. Refer to “Typical High−Side Negative Clamp Voltage” graph on page 17.
8. Current limit is active with and without overcurrent detection.
9. Not production tested.
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VSx < 40 V, EN = VCC = 5 V, unless otherwise specified)
Conditions
Symbol
Min
Typ
Max
Unit
fSCLK
−
−
5.0
MHz
tSCLK
200
500
−
−
−
−
ns
SCLK High Time
tCLKH
85
−
−
ns
SCLK Low Time
tCLKL
85
−
−
ns
tCLKSU1
tCLKSU2
85
85
−
−
−
−
ns
SI Setup Time
tSISU
50
−
−
ns
SI Hold Time
tSIHT
50
−
−
ns
CSB Setup Time
tCSBSU1
tCSBSU2
100
100
−
−
−
−
ns
CSB High Time (Note 10)
tCSBHT
5.0
−
−
ms
SO enable after CSB falling edge
tSOCSBF
−
−
200
ns
Characteristic
SERIAL PERIPHERAL INTERFACE (VCC = 5 V)
SCLK Frequency
SCLK Clock Period
VCC = 5 V
VCC = 3.3 V
SCLK Setup Time
SO disable after CSB rising edge
tSOCSBR
−
−
200
ns
SO Rise Time (10% to 90%)
Cload = 40 pF
tSORISE
−
10
25
ns
SO Fall Time (90% to 10%)
Cload = 40 pF
tSOFALL
−
10
25
ns
SO Valid Time (Note 11)
SCLK High to SO 50%
tSOV
−
50
100
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. This is the minimum time the user must wait between SPI commands.
11. Not tested in production
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NCV7708F
TCLKSU2
TCSBHT
CSB
50%
SCLK
50%
TCSBSU1
50%
TCSBSU2
50%
TCLKSU1
50%
TCLKH
50%
50%
TCLKL
CSB
50%
50%
50%
50%
SO
TSOCSBF
TSOCSBR
SI
50%
50%
TIHT
50%
50%
SCLK
TSOV
SO
50%
TISU
50%
Figure 3. SPI Timing Diagram
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8
50%
NCV7708F
SPI Communication
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(serial input) pin. The SI input signal is latched on
the falling edge of SCLK.
3. Current SO data is simultaneously shifted out on
every rising edge of SCLK starting with the LSB
(TW).
4. CSB goes high to transfer the clocked in
information to the data registers.
(Note: SO is tristate when CSB is high.)
5. The SI data will be accepted when a valid SPI
frame is detected. A valid SPI frame consists of
the above conditions and a complete set of
multiples of 16 bit words. Invalid frames are
ignored with previous input data intact.
Standard 16−bit communication has been implemented
for the communication of this IC to turn drivers on and off,
and to report faults. (Reference the SPI Communication
Frame Format Diagram). The LSB (Least Significant Bit) is
clocked in first.
For SPI communication, the device must first be enabled
(EN = high). The SPI inputs are TTL compatible and the SO
output high level is defined by the applied VCC. The
active-low CSB input has a pull−up resistor. SPI
communication is active when CSB is low. Providing a
pull-up resistor insures the communication bus is not active
should the communication link between the microcontroller
and NCV7708F become open. SCLK and SI have
pull−down resistors. This provides known states when the
SPI is not active.
Communication is implemented as follows:
CSB
LSB
SI
SRR
MSB
OUT
L1
OUT
H1
OUT
L2
OUT
H2
OUT
L3
OUT
H3
OUT
L4
OUT
H4
OUT
L5
OUT
H5
OUT
L6
OUT
H6
OCD
ULD
OVLO
OUT
L1
OUT
H1
OUT
L2
OUT
H2
OUT
L3
OUT
H3
OUT
L4
OUT
H4
OUT
L5
OUT
H5
OUT
L6
OUT
H6
OLD
ULD
PSF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
SO
TW
0
Figure 4. SPI Communication Frame Format
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9
NCV7708F
The table below defines the programming bits and
diagnostic bits. Fault information is sequentially clocked out
the SO pin of the NCV7708F as programming information
is clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the serial output pin (SO) to the input of the
sequential IC (SI).
Output Data
Input Data
Bit #
Bit Description
15
Overvoltage Lock Out Control
(OVLO)
14
13
12
Under Load Detection Shut
Down Control (ULD)
Overcurrent Detection Shut
Down Control (OCD)
OUTH6
Bit Status
0 = Disable
Bit #
Bit Description
15
Power Supply Fail Signal
(OVLO or UVLO = PSF)
0 = No Fault
14
Under Load Detect Signal
(ULD)
0 = No Fault
13
Over Load Detect Signal
(OLD)
0 = No Fault
12
OUTH6*
1 = Enable
0 = Disable
1 = Enable
0 = 200 msec
1 = 25 msec
0 = Off
OUTL6
0 = Off
11
OUTL6*
10
OUTH5*
OUTH5
0 = Off
9
OUTL5*
OUTL5
0 = Off
8
OUTH4*
OUTH4
0 = Off
OUTL4
0 = Off
7
OUTL4*
6
OUTH3*
OUTH3
0 = Off
5
OUTL3*
OUTL3
0 = Off
4
OUTH2*
OUTH2
0 = Off
3
OUTL2*
OUTL2
2
OUTH1*
0 = Off
OUTH1
1
OUTL1*
0 = Off
OUTL1
0
Thermal Warning (TW)
0 = Off
Status Register Reset (SRR)
0 = Off
0 = Off
0 = Off
0 = Off
1 = On
1 = On
0
0 = Off
1 = On
1 = On
1
0 = Off
1 = On
1 = On
2
0 = Off
1 = On
1 = On
3
0 = Off
1 = On
1 = On
4
0 = Off
1 = On
1 = On
5
0 = Off
1 = On
1 = On
6
0 = Off
1 = On
1 = On
7
0 = Off
1 = On
1 = On
8
1 = Fault
1 = On
1 = On
9
1 = Fault
1 = On
1 = On
10
1 = Fault
1 = On
1 = On
11
Bit Status
0 = No Reset
0 = Not in TW
1 = In TW
1 = Reset
*Output Bits [1:12] represent the state of the designated outputs.
Status Register Reset − SRR
present when SRR is sent, protection can be re−engaged and
shutdown can recur. The device can also be reset by toggling
the EN pin or by VCC power-on reset.
When asserted, all latched faults are cleared (TW, OLD,
ULD, and PSF).
Sending SRR = 1 clears status memory and reactivates
faulted output. The previous SI data pattern must be sent
with SRR to preserve device configuration and output states.
SRR takes effect at the rising edge of CSB. If a fault is still
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10
NCV7708F
CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
50%
10%
LS Turn OFF
TlsOffHsOn
90%
50%
10%
HS Turn ON
ThsTr
50%
ThsOn
CSB
LS Turn On
TlsTf
90%
50%
TlsOn
10%
HS Turn Off
ThsOffLsOn
90%
50%
10%
ThsTf
50%
CSB
ThsOff
Figure 5. Detailed Driver Timing
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11
NCV7708F
DETAILED OPERATING DESCRIPTION
General
All low−side drivers are powered by VRAIL via VCC.
All drivers are initialized in the off (high impedance)
condition. Power up sequencing of VCC, VS1, and VS2 is up
to the user. The voltage on VS1 and VS2 should be operated
at the same potential. If the VSx supply moves into either of
the VS under voltage or overvoltage regions (with (OVLO
= 1), the output drivers are switched to high Z, but command
and status data is preserved.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. Exceeding the under voltage lockout
threshold on VCC allows information to be input through the
SPI port for turn on control. Logic information remains
intact over the entire VS1 and VS2 voltage range.
The NCV7708F Double Hex Driver provides drive
capability for three independent H−Bridge configurations,
or 6 High Side configurations with 6 Low Side
configurations, or any combination of arrangements. Each
output drive is characterized for a 500 mA load and has a
typical 1.0 A surge capability (at 13.2 V). Strict adherence
to integrated circuit die temperature is necessary. Maximum
die temperature is 150°C. This may limit the number of
drivers enabled at one time. Output drive control and fault
reporting is handled via the SPI (Serial Peripheral Interface)
port.
Sleep Mode
An Enable function (EN = Low) provides a low quiescent
sleep current mode when the device is not being utilized. No
data is stored when the device is in sleep mode.
Current Limit
OUTx current is limited per the Current Limit electrical
parameter for each driver. The magnitude of the current has
a minimum specification of 2 A at VCC = 5 V and Vsx =
13.2 V. The output is protected for high power conditions
during Current Limit by thermal shutdown and the
Overcurrent Detection shutdown function. Overcurrent
Detection shutdown protects the device during current limit
because the Overcurrent threshold is below the Current
Limit threshold. The Overcurrent Detection Shutdown
Control Timer is initiated at the Overcurrent Shutdown
Threshold which starts before the Current Limit is reached.
Note: High currents will cause a rise in die temperature.
Devices will not be allowed to turn on if the die temperature
exceeds the thermal shutdown temperature.
Input Impedance
A pull down resistor is provided on the EN input to ensure
the device is off if the input signal is lost. Pull down resistors
are also provided on the SI and SCLK inputs. A pull up
resistor is provided for the CSB input for the same reason.
A loss of signal pulls the CSB input high to stop any spurious
signals into the SPI port.
Power Up/Down Control
An undervoltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2, and
VCC pins. Each analog power pin (VS1 or VS2) powers their
respective high−side output drivers and supporting charge
pump. VS1 powers OUTH1, OUTH2, and OUTH3. VS2
powers OUTH4, OUTH5, and OUTH6.
Overcurrent Shutdown (BIT13 = 1)
Effected outputs will turn off when the Overcurrent
Shutdown Threshold has been breached for the Overcurrent
Shutdown Delay Time. The respective OLD status bit will
be set to a “1” and the driver will latch off. The driver can
only be turned back on via the SPI port with a SPI command
that includes an SRR = 1.
Note: High currents will cause a rise in die temperature.
Devices will not be allowed to turn on if the die temperature
exceeds the thermal shutdown temperature.
OVERCURRENT DETECTION SHUT DOWN
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Load Detect (OLD) Status
OUTx Status
Current Limit
of all Drivers
0
0
0
Unchanged
3 A (typ.)
0
1
1 (Need SRR to reset)
OUTx Latches off after 200 ms (typ.)
(Need SRR to reset)
3 A (typ.)
1
0
0
Unchanged
3 A (typ.)
1
1
1 (Need SRR to reset)
OUTx Latches Off After 25 ms (typ.)
(Need SRR to reset)
3 A (typ.)
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12
NCV7708F
Overcurrent Detection Shut Down Control Timer
There are two protection mechanisms for output current,
overcurrent and current limit.
1. Current limit − Always active with a typical
threshold of 3 A.
2. Overcurrent Detection − Selectable shutdown time
via Bit 13 with a typical threshold of 1.45 A.
Figure 6 shows the typical performance of a part which
has exceeded the 1.45 A Overcurrent Detection threshold
and started the shutdown control timer. When Bit 13 = 1, the
shutdown time is 25 msec. When Bit 13 = 0, the shutdown
time is 200 msec.
(current limit)
Once an Overcurrent Shutdown Delay Time event has
been detected by the NCV7708F, the timer setting cannot be
interrupted by an attempted change via a SPI command of
Bit 13.
Input Bit 13
Overcurrent Shutdown Delay Time
0
200 msec
1
25 msec
3A
(overcurrent) 1.45 A
OUTx Current
Bit13 = 1
(current limit)
25 msec
3A
(overcurrent) 1.45 A
OUTx Current
Bit13 = 0
200 msec
Figure 6. Output Current Shutdown Control
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13
NCV7708F
Under Load Detection
The NCV7708F uses a global under load timer. An under
load condition starts the global under load delay timer. If
under load occurs in another channel after the global timer
has been started, the delay for any subsequent under load
will be the remainder of the initially started timer. The timer
runs continuously with any persistent under load condition.
The under load detect bit is reset by setting input data bit 0,
SRR = 1.
The under−load detection is accomplished by monitoring
the current from each output driver. A minimum load current
(this is the maximum detection threshold) is required when
the drivers are turned on. If the under−load circuit detection
threshold has been crossed for more than the under−load
delay time, the bit indicator (output bit #14) will be set to a
1. In addition, the offending driver will be turned off only if
input bit 14 (ULD) is set to 1 (true).
UNDER LOAD DETECTION SHUT DOWN
ULD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14 Under
Load Detect (ULD) Status
OUTx Status
0
0
0
0
Unchanged
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
Undervoltage Lockout (PSF)
Undervoltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins. When the Undervoltage Threshold
level has been breached on both or either one of the VSx
supply inputs, output bit 15 (PSF) will be set and all outputs
will turn off.
Turn on/off status is maintained in the logic circuitry.
When proper input voltage levels are re−established, the
programmed outputs will return to programmed operation.
The Power Supply Fail bit is reset by setting input data bit
0, SRR = 1.
UNDERVOLTAGE LOCK OUT (UVLO) SHUT DOWN
VSx UVLO
Condition
Output Data Bit 15 Power Supply Fail (PSF) Status
OUTx Status
0
0
Unchanged
1
1 (Need SRR to reset)
All Outputs Off (Remain off until VSx is out of UVLO)
Overvoltage Shutdown (PSF)
Overvoltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins. When the Overvoltage Threshold
voltage level has been breached on both or either one of the
VSx supply inputs, output bit 15 will be set and, if input bit
15 (OVLO) is set to 1, all drivers will turn off. Turn on/off
status is maintained in the logic circuitry. When proper input
voltage levels are re−established, the programmed outputs
will turn back on. Overvoltage shutdown can be disabled by
using the SPI input bit 15 (OVLO = 0). The Power Supply
Fail bit is reset by setting input data bit 0, SRR = 1.
OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input Bit 15
VSx OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
All Outputs Latch Off while in OVLO
Return to programmed state out of OVLO
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14
NCV7708F
Thermal Shutdown
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 7 displays how this is accomplished. Bringing
the CSB pin from a 1 to a 0 with SI = 0 immediately displays
the information on output data bit 0, thermal warning. As the
temperature of the NCV7708F changes from a condition
from below the thermal warning threshold to above the
thermal warning threshold, the state of the SO pin changes
and this level is available immediately when the CSB goes
to 0. A 0 on SO indicates there is no thermal warning, while
a 1 indicates the IC is above the thermal warning threshold.
This warning bit is reset by setting input data bit 0, SRR =
1.
Six independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two levels, one to give a Thermal Warning
(TW) and a higher one, Thermal Shutdown, which will shut
the drivers off. When the part reaches the temperature point
of Thermal Warning, the output data bit 0 (TW) will be set
to a 1, and the outputs will remain on. With one or more
sensors detecting the thermal shutdown level, all channels
will be turned off simultaneously. All outputs will return to
normal operation when the part thermally recovers
(Thermal toggling), because the thermal shutdown does not
change the channel selection. The output data bit 0, Thermal
Warning, will latch and remain set, even after cooling, and
is reset by using a software command to input bit 0 (SRR =
1). Since thermal warning precedes a thermal shutdown,
software polling of this bit will allow for load control and
possible prevention of thermal shutdown conditions.
CSB
CSB
SCLK
SCLK
TWH
SO
SO
Tristate Level
Tristate Level
NTW
Thermal Warning High
No Thermal Warning
Figure 7. Access to Temperature warning information shows the thermal information is available immediately
with activation of the CSB signal without having to toggle the SCLK line.
www.onsemi.com
15
NCV7708F
Applications Drawing
The applications drawing below displays the range with
which this part can drive a multitude of loads.
1. H−Bridge Driver configuration
2. Low Side Driver
3. High Side Driver
Reverse battery diode
VBAT
VSx
CIN
VSx
3
OUTHx
OUTHx
CEMC1
10 nF
(optional)
OUTLx
1
2
GND
GND
VSx
CEMC3
10 nF
(optional)
OUTLx
M
CEMC4
10 nF
(optional)
OUTHx
OUTLx
GND
CEMC2
10 nF
(optional)
Figure 8. Application Drawing
Any combination of H−Bridge, high−side, or low−side drivers can be designed in. This allows for flexibility in many
systems.
H−Bridge Driver Configuration
Overvoltage Clamping − Driving Inductive Loads
The NCV7708F has the flexibility of controlling each
driver independently. When the device is set up in an
H−Bridge configuration, the software design has to take care
of avoiding simultaneous activation of connected HS and LS
transistors. Resulting high shoot through currents could
cause irreversible damage to the device.
To avoid excessive voltages when driving inductive loads
in a single−side−mode (LS or HS switch, no freewheeling
path), the NCV7708F provides internal clamping diodes.
Thus any load type can be driven without the requirement of
external freewheeling diodes. Due to high power dissipation
during clamping, the maximum energy capability of the
driver transistor has to be considered.
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16
NCV7708F
TYPICAL OPERATING CHARACTERISTICS
−1.2
2.0
VCC SLEEP CURRENT (mA)
HIGH SIDE CURRENT (A)
1.8
−1.0
−0.8
−0.6
−0.4
−0.2
0
−1.0
−1.5
−2.0
1.2
1.0
0.8
0.6
0.4
0
−50 −30 −10
−2.5
VCC = 5.25 V
10
30
50
70
90
110 130 150
HIGH SIDE PIN VOLTAGE (V)
TJ, TEMPERATURE (°C)
Figure 9. High−Side Negative Clamp Voltage vs.
Reverse Current
Figure 10. VCC Sleep Supply Current vs.
Temperature
45
2.0
44
1.8
43
42
41
40
39
38
37
36
−50 −30 −10
Iout = 50 mA
10
30
50
70
90
VS1 + VS2 SLEEP CURRENT (mA)
LOW SIDE CLAMPING VOLTAGE (V)
−0.5
1.4
0.2
TA = 25°C
0
1.6
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
−50 −30 −10
110 130 150
10
30
50
70
90
110 130 150
TJ, TEMPERATURE (°C)
TJ, TEMPERATURE (°C)
Figure 11. Low−Side Clamping Voltage vs.
Temperature
Figure 12. VS1 + VS2 Sleep Current vs.
Temperature
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17
NCV7708F
Table 1. FAULT HANDLING
Driver Condition after
Parameters Within
Specified Limits
Output Register Clear
Requirement
Offending Driver is
latched off after
200 msec
Offending Driver is
latched off
Valid SPI frame with SRR
set to 1
Latched
Offending Driver is
latched off by
overcurrent timer after
25 msec
Offending Driver is
latched off
Valid SPI frame with SRR
set to 1
Under Load
(Input ULD Bit 14 = 0)
Latched
Unchanged
Unchanged
Valid SPI frame with SRR
set to 1
Under Load
(Input ULD Bit 14 = 1)
Latched
Offending Driver is
latched off after
350 msec
Offending Driver is
latched off
Valid SPI frame with SRR
set to 1 falls below
Power Supply Fail
(OVLO)
Latched
Output Driver on
Bit 15 = 0
Outputs return to their
previous programmed
state
PSF bit is cleared when
VSx falls below the
hysteresis voltage level
and SRR set to 1
Output Driver switched
to high Z
Bit 15 = 1
Outputs return to their
previous programmed
state
PSF bit is cleared when
VSx falls below the
hysteresis voltage level
and SRR set to 1
Fault Memory
Serial Output Bit
Driver Condition
During Fault
Current Limit
±3A
(Input OCD Bit 13 = 0)*
Latched
Over Load
± 1.45 A
(Input OCD Bit 13 = 1)*
Fault
Power Supply Fail
(UVLO)
Latched
Output Driver switched
to high Z
Return to programmed
state
Valid SPI frame with SRR
set to 1
Thermal
Warning
(TW)
Latched
Output Driver on
Drivers in Normal
Operation
Valid SPI frame with SRR
set to 1
Thermal Shutdown
No Thermal Shutdown
Bit
All Drivers turns off
Return to programmed
state
No Thermal Shutdown Bit
All specified currents and times refer to typical numbers.
*Current Limit performance is independent of Overcurrent (Bit13). The output will always limit to current limit independent of bit 13.
www.onsemi.com
18
160
160
140
140
120
120
100
100
80
qJA (°C/W)
qJA (°C/W)
NCV7708F
1 oz
60
2 oz
80
40
40
20
20
0
1 oz
60
2 oz
0
0
100 200
300 400
500
600 700 800 900 1000
0
100 200
300 400
500
600 700 800 900 1000
COPPER HEAT SPREADER AREA (sqmm)
COPPER HEAT SPREADER AREA (sqmm)
Figure 13. SOIC−28 qJA vs. Copper Spreader Area
Figure 14. SSOP24 Narrow Body Exposed Pad qJA
vs. Copper Spreader Area
100
90
50 sqmm
80
R(t) (°C/W)
70
100 sqmm
60
50
40
500 sqmm
30
20
10
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10
100
1000
TIME (s)
Figure 15. SOIC 28−Lead Single Pulse Heating Curve
100
R(t) (°C/W)
50% Duty Cycle
20%
10
10%
5%
2%
1
0.000001
1%
0.00001
Single Pulse
0.0001
0.001
0.01
0.1
1
TIME (s)
Figure 16. SOIC 28−Lead Thermal Duty Cycle Curve on 986 mm2 Spreader Test Board
www.onsemi.com
19
NCV7708F
180
50 sqmm
160
140
100 sqmm
R(t) (°C/W)
120
100
500 sqmm
80
60
40
20
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
100
1000
TIME (s)
Figure 17. SSOP24 Narrow Body Exposed Pad Single Pulse Heating Curve
100
50% Duty Cycle
R(t) (°C/W)
10
20%
10%
5%
2%
1
1%
0.1
0.01
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
TIME (s)
Figure 18. SSOP24 Lead Single Pulse Heating Curve
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20
10
NCV7708F
PACKAGE DIMENSIONS
SOIC−28 WB
CASE 751F−05
ISSUE H
−X−
D
28
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
H
E
0.25
M
Y
M
−Y−
1
14
PIN 1 IDENT
A
L
0.10
G
B
0.025
−T−
A1
SEATING
PLANE
C
M
M
T X
S
Y
S
SOLDERING FOOTPRINT*
8X
11.00
28X
1.30
1
28
28X
0.52
1.27
PITCH
14
15
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
21
DIM
A
A1
B
C
D
E
G
H
L
M
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0_
8_
NCV7708F
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
2X
0.20 C A-B
NOTE 4
D
NOTE 6
D
A
L1
13
24
2X
H
L2
0.20 C
E1
NOTE 5
GAUGE
PLANE
ÉÉ
ÉÉ
PIN 1
REFERENCE
E
L
DETAIL A
A1
C
NOTE 7
1
12
0.20 C
e
B
24X
NOTE 6
TOP VIEW
SEATING
PLANE
b
0.12
2X 12 TIPS
C A-B D
M
DETAIL A
A
A2
h
h
0.10 C
M
0.10 C
24X
0.15
SIDE VIEW
M
C A-B D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UNCONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
c
A1
C
END VIEW
SEATING
PLANE
NOTE 8
D2
0.15
M
C A-B D
RECOMMENDED
SOLDERING FOOTPRINT
E2
NOTE 8
5.63
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L1
L2
M
MILLIMETERS
MIN
MAX
--1.70
0.00
0.10
1.10
1.65
0.19
0.30
0.09
0.20
8.64 BSC
5.28
5.58
6.00 BSC
3.90 BSC
2.44
2.64
0.65 BSC
0.25
0.50
0.40
0.85
1.00 REF
0.25 BSC
0_
8_
BOTTOM VIEW
24X
1.15
2.84 6.40
1
24X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
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