Fairchild AN-4153 Designing asymmetric pwm half-bridge converter Datasheet

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AN-4153
Designing Asymmetric PWM Half-Bridge Converters with
a Current Doubler and Synchronous Rectifier using
FSFA-Series Fairchild Power Switches (FPSTM)
Introduction
In general, high-frequency operation allows the use of smallsized passive components in switch-mode power supplies
(SMPS), though it causes the switching losses to increase in
a hard-switching mode. To reduce switching losses at high
switching frequencies, many soft-switching techniques have
been developed, including load-resonant and zero-voltagetransition techniques.
Load-resonant techniques use a resonant feature of
capacitors and inductors during the entire switching period
to vary the switching frequency, depending on the input
voltage and load current. The change of the switching
frequency, i.e. pulse frequency modulation (PFM), makes it
difficult to design an SMPS including input filters. Since
there is no output inductor for filtering, the clamped voltage
across output-rectifying diodes allows designers to select
low-voltage-rating diodes. However, the absence of the
output inductor burdens the output capacitors when the load
current increases, making load-resonant techniques
unsuitable for applications with high output current and low
output voltage.
On the other hand, zero-voltage-transition techniques use a
resonant feature between parasitic components during turnon and/or turn-off transitions of the switching period. One of
the advantages of these techniques is to use the parasitic
components, such as the leakage inductance of the main
transformer and the output capacitances of the switches, so
there is no need to add more external components to achieve
soft switching. In addition, these techniques take pulse-width
modulation (PWM) up with fixed-switching frequency.
Therefore, these are easier to understand, analyze, and
design than load-resonant techniques.
Due to its simple configuration and zero-voltage switching
(ZVS) characteristic, an asymmetric PWM half-bridge
converter is one of the most popular topologies using the
zero-voltage-transition technique. In addition, the ripple
component of the output current due to an output inductor
becomes small enough to be handled by an appropriate
output capacitor. Being easy to analyze and design and
having an output inductor, it is generally used for
applications with high output current and low output voltage
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
(e.g. game console power supplies). To handle the large
output current, using a synchronous rectifier in the
secondary side is popular to obtain the conduction losses as
ohmic losses instead of diode losses. In addition, a current
doubler increases the utilization of the main transformer
when the output current is high.
Fairchild’s FSFA-series of green power switches (FPS™)
integrates a PWM controller and MOSFETs specifically
designed for asymmetric-controlled topologies with minimal
external components. Compared with discrete-PWMcontroller-and-MOSFETs solutions, FSFA-series switches
can reduce total cost, bill of materials (BOM) list, size, and
weight, while simultaneously increasing efficiency,
productivity, and system reliability.
This application note describes design considerations of an
asymmetric PWM half-bridge converter with current
doubler and synchronous rectifier employing FSFA-series
switches. It includes a step-by-step design procedure as well
as the general features and operational principles of the
proposed topology.
1. Operational Principles of a
Conventional Asymmetric PWM
Half-Bridge Converter
Figure 1 shows a conventional asymmetric PWM halfbridge converter with a center-tapped transformer. While the
switch S1 operates with a duty D, depending on the input
voltage and load current, the switch S2 operates with 1-D.
During DTS, Vin-VCb is applied on the primary side of the
transformer and the secondary diode D1 turns on. The
primary current ipri increases since the magnetizing current
im of the transformer (not illustrated) and the output inductor
current iLo increase together. During (1-D)TS, VCb is applied
on the transformer and D2 turns on. The capacitor Cb is not
only a voltage source during (1-D)TS but also a DC-blocking
capacitor to prevent transformer saturation. When the
volt·sec balance for the magnetizing inductance of the
transformer is applied, the following is obtained:
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AN-4153
APPLICATION NOTE
vCb
n:1:1
Cb
D1
iD1
iLo
vT1
S2
DTS
vGS
Co
Dloss2TS
Dloss1TS
LO
(1-D)TS
S1
S2
S1
Vo
t
Llk
Vin
ipri
ipri
S1
t
D2
Lm/(Lm+Llk)
*(Vin-VCb)
iD2
vT1
Figure 1. Conventional Asymmetric PWM HalfBridge Converter with a Center-Tapped Transformer
(Vin − VCb ) × D = VCb × (1 − D)
⇒ VCb = DVin
Lm/(Lm+Llk)
*(-VCb)
t
iD1
iD2
(1)
The volt·sec balance for the output inductor yields:
V ⎞
⎛
⎛ Vin − VCb
⎞
− VO ⎟ × D = ⎜VO − Cb ⎟ × (1 − D )
⎜
n
n ⎠
⎝
⎝
⎠
t0 t1
(2)
t
t4
and scaling down vT1 by n. In addition, the applied voltage
on the primary side of the transformer during powering
modes (t1~t2 and t3~t4) is slightly less than Vin–VCb or –VCb
due to the leakage inductance Llk as shown in Figure 3.
Therefore, the output voltage equation could be obtained as:
Combining Equations (1) and (2), the output voltage is
obtained as:
(3)
⎛ Lm
VO = ⎜⎜
⎝ Lm + Llk
As can be seen in Figure 2 (the gain curve according to the
duty cycle using Equation (3) ignoring turns ratio n), the
gain is proportional to the duty cycle up to 50% and
inversely proportional to it above 50%. Because of this
symmetry, the maximum duty cycle should be restricted up
to 50% to regulate the output voltage.
⎞⎛ 2 D(1 − D )Vin 4 I O Llk
⎟⎟⎜
− 2
⎜
n
n TS
⎠⎝
⎞
⎟ − VF
⎟
⎠
(4)
where IO is the output load current and VF is the forward
voltage drop of the secondary side-rectifying diodes.
To design the transformer, the magnetizing current must be
known. Assume that the magnetizing inductance and the
output inductance are high enough for the current ripple on
them to be ignored and the leakage inductance is low
enough for the duty loss parts to be neglected. Then the
current waveforms are simplified as shown in Figure 4. To
meet the current·sec balance for Cb, the positive part of the
primary current ipri is equivalent to the negative part such
that the magnetizing current is obtained as:
The loss parts of the duty cycle by the leakage inductance
are not considered in Equation (3). Figure 3 shows the key
waveforms of the conventional asymmetric PWM halfbridge converter illustrated in Figure 1. Since both
secondary rectifying diodes conduct, the voltage across the
primary side of the transformer becomes zero during Dloss1TS
and Dloss2TS. As a result, the output voltage is not as high as
in Equation (3), which is obtained by averaging, rectifying,
Figure 2. Normalized Gain Curve
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
t3
Figure 3. Key Waveforms of the Conventional
Asymmetric PWM Half-Bridge Converter
where n is the turns ratio of the transformer.
⎛ 2 D(1 − D) ⎞
VO = ⎜
⎟ × Vin
n
⎝
⎠
t2
Figure 4. Simplified Current Waveforms in the
Primary Side
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AN-4153
I ⎞
I ⎞
⎛
⎛
⎜ I m + O ⎟ × D = ⎜ − I m + O ⎟ × (1 − D)
n
n ⎠
⎝
⎠
⎝
I
⇒ I m = (1 − 2 D) O
n
APPLICATION NOTE
2.1. Operational Principles
Figure 7 shows the mode analysis for the asymmetric PWM
half-bridge converter with the current doubler and
corresponding key waveforms. Assume ZVS is achieved
sufficiently with very short duration. The ZVS modes can be
ignored in the mode analysis. The ZVS operation is
discussed in detail in the next section. Other assumptions
are:
(5)
where Im is the DC component of im. As can be seen in
Equation (5), Im could be zero when the duty cycle is 50%.
Generally im has a DC offset, so the core saturation has to be
taken into account when the transformer is designed.
(1) The DC-blocking capacitor Cb is large enough to
neglect the voltage ripple on it, and
2. Operational Principles of an
Asymmetric PWM Half-Bridge
Converter with Current Doubler and
Synchronous Rectifier
(2) All elements in the circuit are ideal.
For low-output-voltage and high-output-current applications,
the current doubler is widely used. Figure 5 illustrates the
asymmetric PWM half-bridge converter with the current
doubler on the secondary side. The secondary winding is a
single-ended configuration, while the output inductors are
divided into two smaller inductors. To increase the total
efficiency, a synchronous rectifier (SR) comprised of
MOSFETs with low Rds(on) is used. The current doubler has
several advantages compared to the conventional centertapped configuration. First, the DC component of the
magnetizing current is lower than or equal to that of the
center-tapped configuration, which makes it possible to use
the smaller core for the transformer. The amount of the
magnetizing current is the same as that of the center-tapped
configuration when each output inductor carries half the
load current. The amount of the magnetizing current is
reduced when the output inductors carry the load current
unevenly. Second, the root-mean-square (rms) value of the
secondary winding current is smaller than that of the centertapped configuration, since almost half of the load current
flows through each output inductor. As a result, the low
current density for the secondary winding could be used
with the same core and the same gauge of wire. Third, the
winding itself is easier than the center-tapped configuration.
This is notable especially for multi-output applications
because of the limitation of the pin number of the bobbin of
the transformer. Fourth, the gate signals for SR are obtained
easily and effectively from the output inductors, as shown in
Figure 6(b). An appropriate gate voltage (e.g., between 10 V
and 20 V) could be easily obtained from the output
inductors due to an enough number of turns, while the
secondary side number of turns of the transformer is only a
few. Additionally, the separated output inductors reduce the
burden of the cost of the bigger core. These advantages
make the current doubler one of the most popular topologies
for high-output-current applications.
Figure 5. Asymmetric PWM Half-Bridge Converter
with the Current Doubler
Figure 6. Methods for Producing the Gate Driver
Signal Using; (a) the Transformer; (b) the Output
Inductor
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
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AN-4153
APPLICATION NOTE
Let’s start with Mode 2, a powering mode. When S1 turns
on, Vin-VCb is applied on the primary side of the transformer.
The magnetizing current im increases with the slope of (VinVCb)/Lm. The slope of the current of LO1 is determined by
subtracting the output voltage from (Vin-VCb)/n because SR2
turns off. On the other hand, the current of LO2 decreases
with the slope of –VO/LO2, which is free-wheeling through
SR1. While two output inductors share the load current, SR1
carries the whole load current. The secondary winding of the
transformer handles only iLO1 so that iLO1/n is the reflected
current to the primary side of the transformer and it is
superimposed on the magnetizing current, which constitutes
the primary current ipri. In fact, vT2 is slightly lower than the
value illustrated in Figure 7 due to leakage inductance (see
Chapter 1.) It is ignored in this section to simplify analysis.
body diode of SR2 turns on since its reverse-biased voltage
is eliminated. Subsequently, both SRs turn on together
during this mode. The body diode of S2 turns on after the S2
output capacitance is wholly discharged and that of S1 is
entirely charged. Since both SRs turn on, iLO1 and iLO2 are
free-wheeling with the slope of –VO/LO1 and –VO/LO2,
respectively, and vT1 and vT2 are zero, VCb is applied only on
the leakage inductance, causing the primary current’s
polarity to change rapidly. When S2 turns on after the S2
body diode conducts, the S2 ZVS condition is achieved. The
duration of this mode is obtained as:
Dloss 2 =
LO1
n:1
SR2
S2
Vin
DTS
Vo
VGS
SR1
Dloss2TS
Dloss1TS
Co
Llk
S1
(6)
Mode 4, another powering mode, starts with the end of
commutation between SRs. The applied voltage on the
primary side of the transformer is –VCb so that the
magnetizing current decreases with the slope of –VCb/Lm and
When S1 turns off, Mode 3 begins. As the output capacitance
of S2 is discharged, vT1 decreases. It becomes zero when the
output capacitance voltage of S2 equals VCb. At this time, the
Cb
IO
Llk
×
n DVin × TS
(1-D)TS
S1
S2
S1
t
LO2
(a) Mode 1 (t0~t1)
Cb
LO1
n:1
im
(Vin-VCb)/Lm
ipri
-VCb/Lm
t
SR2
S2
Co
Llk
Vin
(Vin-VCb)/n
Vo
vT2
SR1
S1
t
-VCb/n
LO2
(b) Mode 2 (t1~t2)
Cb
LO1
n:1
-VO/LO1
iLo2
SR2
S2
-VO/LO2
Co
Llk
Vin
Vo
iLo1
((Vin-VCb)/n-VO)/
LO1
SR1
S1
(VCb/n-VO)/LO2
t
LO2
iSR1
(c) Mode 3 (t2~t3)
Cb
diLo1+diLo2
LO1
n:1
iSR2
diLo1+diLo2
SR2
S2
Co
Llk
Vin
Vo
S1
t0 t1
SR1
t2
t3
t4
t
(e) Key waveforms
LO2
(d) Mode 4 (t3~t4)
Figure 7. Mode Analysis and Waveforms for Asymmetric PWM Half-Bridge Converter with the Current Doubler
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
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AN-4153
APPLICATION NOTE
Therefore, not only the energy in the leakage inductance, but
also the energy of the load current, helps S1 be discharged
from Vin to Vin-VCb. After vDS1 is reduced more than Vin-VCb,
the dotted terminal of the transformer changes its polarity,
which allows the body diode of SR1 to turn on. Therefore,
the magnetizing inductance is short-circuited so that the
switches are charged and discharged by the energy in the
leakage inductance only from ta. Finally, vDS1 is fully
discharged at tb, so the primary current flows through the
body diode of S1, as can be seen in Figure 8(c). After tc, the
primary current flows through both the channel and the body
diode since the gate signal of S1 is applied. Mode 2 begins
with the end of the commutation between SRs from t1.
the slope of iLO2 is (VCb/n-VO)/LO2. The other inductor
current is free-wheeling through SR2. As can be seen in
Figure 7, the large ripple on each output inductor is
cancelled because of the out-of-phase. Therefore, two
smaller inductors can be used in the current doubler
configurations compared with the center-tapped or bridge
rectifying configurations.
When S2 turns off, Mode 1 starts as another regenerating
mode. The operating principle of Mode 1 is almost the same
as Mode 3, except for a ZVS condition. In Mode 1, vT1
becomes zero at the instant when the output capacitance
voltage of S1 is equivalent to Vin-VCb. Before this instant, the
load current on the output inductor LO2 is reflected to the
primary side of the transformer and helps to meet the ZVS
condition of the switches. The energy stored in the leakage
inductance only has to discharge and charge the output
capacitance of the switches after this instant. Therefore, the
ZVS condition for S1 is harder than S2 since Vin-VCb is higher
than VCb in general. In all other respects, Mode 1 can be
analyzed in the same way as Mode 3. The duration of Mode
1 is obtained as:
Dloss1 =
IO
Llk
×
n (1 − D)Vin × TS
For the ZVS operation of S1 there are three conditions in
Figure 8, as follows:
(1) The energy in the leakage inductance should be
sufficient to discharge S1 from Vin-VCb to zero and
charge S2 from VCb to Vin.
(2) The instant tb must be earlier than when the primary
current changes its polarity. Otherwise, the drain
voltages of S1 and S2 are again charged and discharged,
respectively.
(7)
(3) The gate signal of S1 must be applied before the
primary current changes its polarity.
The detailed output voltage is calculated with Equations (6)
and (7) as:
VO =
Lm
Lm + Llk
⎛ D (1 − D)Vin I O Llk
⎜
− 2
⎜
n
n TS
⎝
⎞
⎟ − VSR
⎟
⎠
Figure 9 shows the detailed modes in Mode 3. While the
detailed mode analysis is similar to the case of Figure 8,
three conditions for the ZVS operation of S2 are different
from those of Figure 8:
(8)
where VSR is the voltage across the MOSFET as an SR
during powering modes. It is similar to Equation (4) except
for the turns ratio, which is half that of the conventional
converter.
(1') Since the polarity of the transformer terminals changes
when vDS2 reaches VCb, the portion of discharging S2 by
the load current, t2~td, is much larger than t0~ta in
Figure 8. Therefore, the remaining portion of
discharging S2 by the energy in the leakage inductance
only is shortened; the ZVS of S2 is easier to achieve
compared with the ZVS of S1. Therefore, the energy in
the leakage inductance should be sufficient to discharge
S2 from VCb to zero and charge S1 from Vin-VCb to Vin.
By modifying Equation (5), the DC and ripple components
of im are obtained as:
I m = (1 − D )
I
I LO 2
− D LO1
n
n
Δim = ( DTS − Dloss1TS ) ×
(1 − D)Vin
Lm + Llk
(9)
(2') The commutation between SRs begins with the change
of polarity of the transformer terminals so that it takes
longer from te to the instant when the currents in SRs
are equal. In addition, the commutation slope is more
sluggish than the case in Figure 8, since the applied
voltage on the leakage inductance is reduced to VCb
from Vin-VCb.
(10)
where ILO1 and ILO2 are the DC components of the output
inductor currents.
2.2. ZVS Conditions
(3') The gate signal of S2 must be applied before the
primary current changes its polarity if Condition (3) is
satisfied due to the same dead time and the reason
mentioned in (2’).
In the previous section, the duration for ZVS operation was
omitted to simplify mode analysis. More detailed analysis
for ZVS operation is given in this section to discover an
exact ZVS condition for each switch. Figure 8 shows the
detailed modes for Mode 1.
With respect to both energy ((1) and (1’)) and timing ((2 &
3) and (2’ & 3’)), the ZVS condition of S1 is more difficult
to achieve than that of S2. Therefore, the ZVS condition
should be considered with S1 only. In general, the condition
for timing is easily satisfied if the condition for energy is
From t0, the primary current starts to charge and discharge
the output capacitance of the switches. Before the drain
voltage of S1, vDS1 reaches to Vin-VCb, the dotted terminal of
the transformer is negative so that SR1 is still reverse-biased.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
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AN-4153
APPLICATION NOTE
An easy way to achieve ZVS for both switches even at light
load conditions is to increase Llk. However, the increased Llk
increases duty loss parts by reducing the slope of the
primary current in Modes 1 and 3. This results in the
increase of conduction loss for the reduced effective duty
cycle. Therefore, it is not recommended as a method to
increase Llk for ZVS at very light load. According to
Equation (9), as the load current decreases, the DC
component of the magnetizing current decreases as well. If
the DC component of im is less than half the ripple
component of im, the ZVS operation is performed by the
magnetizing inductance with the leakage inductance. In
Equation (11), ignoring the second term in the denominator,
satisfied. Therefore, the required leakage inductance for the
ZVS of both switches at special load condition can be
calculated as:
Llk >
2COSS [(1 − D)Vin ]2
⎧⎪ D (1 − D)Vin × TS I O, tar
−
⎨
2n
⎪⎩ 2( Lm + Llk )
(11)
⎛
Lm
⎜⎜1 −
L
m + Llk
⎝
⎞ DI O, tar ⎫⎪
⎟⎟ +
⎬
n ⎪⎭
⎠
2
where COSS is the output capacitance of the switch and IO,tar
is the target load condition where a designer wants the
system to operate in ZVS condition with the leakage
inductance.
Cb
LO1
n:1
SR2
S2
Co
Llk
Vin
Vo
SR1
S1
Dloss1TS
LO2
(a) Mode 1_1 (t0~ta)
Cb
LO1
n:1
(1-D)TS
DTS
S2
S1
t
vDS1
SR2
S2
Co
Vin-VCb
Vo
VCb
vDS2
Llk
Vin
SR1
S1
iSR2
iSR1
t
LO2
(b) Mode 1_2 (ta~tb)
Cb
LO1
n:1
t
SR2
S2
Co
Llk
Vin
Vo
(Vin-VCb)/Llk
SR1
S1
t
ipri
LO2
(c) Mode 1_3 (tb~tc)
Cb
t0 ta
tb tc
t1
LO1
n:1
(e) Key waveforms
SR2
S2
Co
Llk
Vin
Vo
SR1
S1
LO2
(d) Mode 1_4 (tc~t1)
Figure 8. Detailed Mode Analysis During Mode 1
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
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APPLICATION NOTE
rearrangement for Lm yields:
Lm + Llk <
2.3. Synchronous Rectifier
D(1 − D)Vin × TS
⎧⎪ 2COSS
⎫⎪
DI
2×⎨
(1 − D)Vin − O, tar ⎬
n ⎪⎭
⎪⎩ Llk
It is more profitable that the conduction losses on the
secondary rectifying stage are composed of ohmic losses
instead of diode losses when the output current is high.
Since most of load current flow through the channel,
conduction losses can be reduced dramatically if
synchronous MOSFETs with very low Rds(on) (less than
several mΩ) turn on and off appropriately. In buck-derived
topologies such as forward, half-bridge, and full-bridge
converters, the gate signal for SR is easily obtained from the
(12)
To obtain appropriate Lm and Llk using Equations (11) and
(12), iterations are necessary. An example of this is given in
the next section.
Cb
LO1
n:1
SR2
S2
Co
Llk
Vin
Vo
SR1
S1
Dloss2TS
LO2
DTS
(a) Mode 3_1 (t2~td)
Cb
S1
LO1
n:1
(1-D)TS
S2
t
vDS2
SR2
S2
Co
Vin-VCb
Vo
VCb
vDS1
Llk
Vin
SR1
S1
iSR1
iSR2
t
LO2
(b) Mode 3_2 (td~te)
Cb
LO1
n:1
t
SR2
S2
ipri
Co
Llk
Vin
-VCb/Llk
Vo
SR1
S1
t
LO2
(c) Mode 3_3 (te~tf)
Cb
t2
td te tf
t3
LO1
n:1
(e) Key waveforms
SR2
S2
Co
Llk
Vin
Vo
SR1
S1
LO2
(d) Mode 3_4 (tf~t3)
Figure 9. Detailed Mode Analysis During Mode 3
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
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APPLICATION NOTE
main transformer (as shown in Figure 6(a)). Unlike flyback
or LLC converters, there is no need to add any other special
functions, except for the driving circuit. Ease of construction
of the SR driver is another reason to use the half-bridge
topology for high-output-load-current applications.
3. Design Procedure and Example
In this chapter, a design procedure is shown using the design
reference illustrated in Figure 11. The target system for this
example is a game console power-supply unit with 12 V of
output voltage and 30 A of output load current. To handle
the large output-load current, the current doubler with the
synchronous rectifier discussed in the previous chapter is
used. Since the input comes from a power factor correction
(PFC) circuit, the input-voltage range is not wide.
Moreover, when using a current doubler, it is more efficient
to get the gate signal from the output inductors than from the
main transformer (as shown in Figure 6(b)). Figure 10
illustrates the SR gate-signal waveforms from the main
transformer and the output inductors. It is difficult to tune up
the turns ratio na and nb (where na=ns/n1 and nb=ns/n2) to
make the sufficient gate voltage (as shown in Figure 10(a)).
This is because both positive and negative parts are
dependent not only on the turns ratios na and nb but also on
VCb. Additionally, the power loss by the negative part of the
gate signal is determined by the turns ratio, VCb, and Vin. On
the other hand, the power loss by the negative part of the
gate signal does not depend on the load condition (as shown
in Figure 10(b), where nc=n3/n1 and nd=n4/n2). In addition,
during the duty loss part, Dloss1TS and Dloss2TS, the gate
signals change their polarity to a negative value so that the
SRs turn off rapidly and definitely. This helps to reduce the
turn-off loss of the synchronous MOSFETs.
Dloss1TS
[STEP 1] System Specifications
The first step in designing is to define the system
specifications. Generally, a PFC circuit is used for mediumor high-power applications such as LCD/PDP TV systems,
game console power supplies, and beam projectors to meet
international harmonic regulations. Thus, the input voltage
range for the main power stage (i.e. the output voltage of
PFC stage) is almost fixed (e.g., 370~410 Vdc). However,
the input voltage range may be widened to meet special
requirements.
In this chapter, the target specifications are:
▪ Nominal input voltage: 390 Vdc
▪ Input voltage range: 370~410 Vdc
▪ Output voltage: 12 V
▪ Output current: 30 A
▪ Switching frequency: 100 kHz
Dloss2TS
(Vin-VCb)/n
vT2
-VCb/n
t
[STEP 2] Turns Ratio and Duty Cycle
(Vin-VCb)/n/na
The output voltage equation (Equation 8) is used to
determine turns ratio n. However, the output voltage
equation contains the leakage and magnetizing inductance,
which are not yet determined. Therefore, a designer should
make assumptions for the following:
vgate_SR1
-VCb/n/na
vgate_SR2
t
VCb/n/nb
t
▪
▪
▪
-(Vin-VCb)/n/nb
t0 t1
t2
t3
t4
(a)
Dloss1TS
vgate_SR1
▪
Same shape as vLO1 except for nc
Dloss2TS
According to Equation (8), the turns ratio is obtained as:
((Vin-VCb)/nVO)/nc
-VO/nc
t
Dn (1 − Dn )Vin , n + ( Dn (1 − Dn )Vin, n ) 2 − 4(VO + VSR )
Same shape as vLO2 except for nd
vgate_SR2
n=
(VCb/n-VO)/nd
-VO/nd
t0 t1
VSR considering Rds(on) of used MOSFETs as an SR;
α, the ratio between Lm and Lm+Llk;
The leakage inductance that will be changed later by
iterations of Equations (11) and (12);
The nominal duty cycle at the nominal input voltage.
α
t
t2
t3
2(VO + VSR )
where Vin,n and Dn are the nominal input voltage and the
nominal duty cycle at Vin,n, respectively.
t4
(b)
For turns ratio n, the duty cycle at an input voltage and a
load current is calculated as:
Figure 10. Gate Signals for Synchronous Rectifier; (a)
Transformer Coupled; (b) Output Inductor Coupled
⎛ n(VO + VSR ) I O Llk
1 − 1 − 4⎜⎜
+
αVin
nVinTS
⎝
D=
2
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
I O Llk
αTS (13)
⎞
⎟⎟
⎠
(14)
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8
AN-4153
APPLICATION NOTE
C102
Dvcc
Vcc
Cvcc
#7
FUSE1
R107
#9
C107
#2
VFB
Cfb
R102
L202
Csn1
Cout2
N4
Rdr1
Vo = 12V/30A
Rdr2
Qdr2
Rsn2
Cout1
Csn2
L201
Q102
#10
#4
CS
Qdr1
Ns
Chvcc
Control IC
U2-2
Clink
Np
H-Vcc
#3
RT
Vin
PFC output
Rsn1
Q101
#1 VDL
L-Vcc
R105
Ddr1
N1
Rvcc
VCTR
N2
Ddr2
N3
U1
FSFA2100
#5 SG
#6
C103
PG
R101
Figure 11. Reference Design Schematic
Design Example
For the example, the following values are assumed:
▪
▪
▪
D@ 30%
VSR = 0.3V
α is 0.95
The initial leakage inductance is 20 µH. This may be
increased after checking the ZVS condition. Taking the
core size for 360W into account, if Llk is less than this
value, the productivity is not good.
The nominal duty cycle at 390 Vdc is 0.4.
▪
Since COSS of the FSFA2100 MOSFETs is 150 pF, the
required leakage inductance is obtained with D@30%=0.305
as:
n=
2COSS [(1 − D )Vin ]
2
Llk >
Using these values, the turns ratio is obtained by Equation
(13) as:
0.4 ⋅ 0.6 ⋅ 390 + (0.4 ⋅ 0.6 ⋅ 390) 2 − 4(12 + 0.3)
⎛ 6.5 ⋅ (12 + 0.3)
⎞
9 ⋅ 20 μ
1 − 1 − 4⎜⎜
+
⎟⎟
μ
0
.
95
⋅
410
6
.
5
⋅
410
⋅
10
⎝
⎠
=
2
= 0.305.
⎧ D (1 − D )Vin × TS I O ,tar ⎛
Lm ⎞ DI O ,tar ⎫
−
⎨
⎜⎜1 − L + L ⎟⎟ + n ⎬
L
L
n
2
(
)
2
+
m
lk
m
lk ⎠
⎝
⎭
⎩
2
2 ⋅150 p ⋅ [(1 − 0.305) ⋅ 410]
2
=
30 ⋅ 20μ
0.95 ⋅ 10μ
⎧ 0.305 ⋅ (1 − 0.305) ⋅ 410 × 10 μ
⎞ 0.305 ⋅ 9 ⎫
9 ⎛
400 μ
−
⎨
⎜⎜1 − 400 μ + 20μ ⎟⎟ + 6.5 ⎬
+
×
2
(
400
μ
20
μ
)
2
6
.
5
⎝
⎠
⎩
⎭
= 12.0 μH .
2(12 + 0.3)
0.95
= 6.52
2
The required leakage inductance is 12.0 µH, which is too
small to control in a mass production. If the obtained value
is larger than the assumed value, the obtained value is used,
and the SMPS designer must repeat Step 2 to check if the
turns ratio is still valid. However, in this design example, the
designer chooses the initial value for productivity, and there
is no iteration needed.
yielding a turns ratio is 6.5. The nominal duty cycle at the
nominal input voltage is recalculated by Equation (14) as:
⎛ 6.5 ⋅ (12 + 0.3)
30 ⋅ 20 μ ⎞
+
1 − 1 − 4⎜⎜
⎟
6.5 ⋅ 390 ⋅ 10 μ ⎟⎠
⎝ 0.95 ⋅ 390
Dn =
= 0.397
2
[STEP 3] Magnetizing and Leakage Inductance
Using the turns ratio obtained in Step 2, the ZVS condition
could be checked with Equations (11) and (12).
Design Example
This example is designed to achieve the ZVS operation from
full- to 30%-load condition using the leakage inductance and
the magnetizing inductance. The duty cycle at 30% load
condition and the maximum input voltage is obtained by
Equation (14) as:
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
Figure 12. Primary Current Waveform
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9
AN-4153
APPLICATION NOTE
addition, it is better to choose a wire with multi-strands of
thinner wire, such as Litz wire, to minimize the skin effect.
The magnetizing inductance can be determined using
Equation (12) as:
D(1 − D)Vin × TS
Lm + Llk <
When the output inductor current ripple is ignored, Figure
12 shows the primary-current waveform. The rms value of
this waveform is given as:
⎧ 2COSS
⎫
DI
2× ⎨
(1 − D)Vin − O,tar ⎬
n ⎭
⎩ Llk
0.305 ⋅ (1 − 0.305) ⋅ 410 ⋅10μ
=
⎧ 2 ⋅150 p
0.305 ⋅ 9 ⎫
2× ⎨
(1 − 0.305) ⋅ 410 −
⎬
6.5 ⎭
⎩ 20μ
= 638μH .
( I P12 + I P1I P 2 + I P 2 2 )
( I 2 + I P3 I P 4 + I P 4 2 )
D + P3
(1 − D)
3
3
iP rms =
Therefore, Lm is selected as 600 µH.
I P1 =
I LO1
Δi
+ Im − m
2
n
(20)
I P2 =
I LO1
Δi
+ Im + m
2
n
(21)
[STEP 4] Transformer
Using Equations (9) and (10), the peak magnetizing current
is obtained as:
I
Δi
I
I m + m = (1 − D) LO 2 − D LO1
2
n
n
(1 − D)Vin
+ ( DTS − Dloss1TS ) ×
2( Lm + Llk )
(15)
IO
2n
Lmim max
Ae Bmax
I LO 2
Δi
+ Im − m
2
n
(23)
im max =
IO
30
=
= 2.31A.
2 n 2 ⋅ 6 .5
The given core is EER4042 (Ae=158 mm2). The minimum
turns number for the transformer primary side is calculated
as:
(17)
NP
min
Lmim
600 μ ⋅ 2.31
=
= 38.14
Ae Bmax 158μ ⋅ 0.23
max
=
When NP is selected as 39, the secondary turns number is
obtained as 6.
Use Equations (19)-(23) to get the rms value of the
transformer primary side current. Assume each output
inductor carries the output load current evenly at the
nominal condition (Dn=0.397).
(18)
where NP is larger than NPmin in Equation (17).
The diameter of the wire is selected based on the current
density, whose range is generally 4~10 A/mm2. It is
recommended to select the current density as low as possible
to reduce conduction losses on the wire. However, try to
reduce the winding layers at the same time. The more
winding layers, the more circulating current caused by the
proximity effect. Sometimes trying to reduce conduction
losses by increasing the wire diameter makes conduction
losses increase by increasing the circulating current. In
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
I P4 = −
When the duty cycle is zero, the maximum im is obtained as:
(16)
The number of turns for the transformer secondary side is
obtained as:
NP
n
(22)
Design Example
where Ae is the effective cross-sectional area of the used
core in mm2, and Bmax is the maximum flux density in Tesla.
Bmax = 0.2~0.25 T is recommended if there is no reference
data.
NS =
I LO 2
Δi
+ Im + m
2
n
For the secondary-side winding, half the load current is the
rms value when it is assumed that each output inductor
carries the load current evenly and the ripple on the output
inductor is small enough to be ignored.
The minimum number of turns for the transformer primary
side is given as:
N P min =
I P3 = −
where Im and Δim are defined in Equations (9) and (10).
The maximum value of the peak magnetizing current occurs
when each output inductor carries half the load current for
the worst case and the duty cycle is zero during startup or
transient instant. Therefore, the maximum im is:
im max =
(19)
I P1 =
15
1.357
+ 0.475 −
= 2.10 A
6 .5
2
I P2 =
15
1.357
+ 0.475 +
= 3.46 A
6.5
2
I P3 = −
15
1.357
+ 0.475 +
= −1.15 A
2
6.5
I P4 = −
15
1.357
+ 0.475 −
= −2.51A
2
6 .5
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10
AN-4153
APPLICATION NOTE
Therefore, the rms value of the transformer primary side
current is obtained by Equation (19) as:
i P rms =
fS =
( 2.12 + 2.1 ⋅ 3.46 + 3.46 2 )
0.397
3
For the design example, the frequency setting resistor R105 is
selected as 27 kΩ for 100 kHz operation.
[STEP 7] DC-Blocking Capacitance
The rms value of the transformer secondary side current is
half the load current, so iSrms=15 A.
It has been assumed that the DC-blocking capacitor is large
enough to neglect the voltage ripple on it. However, too
large a DC-blocking capacitor leads to slow dynamic
response. Therefore, it is recommended to make the voltage
ripple on the DC-blocking capacitor around 10% of the
input voltage. The voltage ripple on the DC-blocking
capacitor is obtained as:
Since the diameter of the wire becomes too thin, it is not
easy to wind 39 turns for the primary side of the transformer
in two layers. Choose the biggest wire that can be wound 13
turns in one layer of the bobbin for EER4042. Due to
consideration of the skin effect, Litz wire of 100 strands
with AWG38 (American wire gauge) is selected as the
primary wire. In this case, the current density is around 2.9
A/mm2. For the secondary side, 250-strand Litz wire with
AWG36 is chosen where the current density is around 4.7
A/mm2.
ΔvCb
[STEP 5] Output Inductance
(V + VSR )(1 − D + Dloss1 )TS
= O
(24)
LO1
(VO + VSR )( D + Dloss 2 )TS
⎛ Dloss1TS × I P1 Dloss 2TS × I P 2 ⎞
+
⎜
⎟
1
2
2
⎟
C102 ≅
×⎜
2ΔvC102 ⎜ ( D − Dloss1 )TS × ( I P1 + I P 2 ) ⎟
⎜+
⎟
2
⎝
⎠
⎛ 0.039 × 10μ × 2.1 0.06 × 10μ × 3.47 ⎞
+
⎜
⎟
1
2
2
⎜
⎟
=
×
2 × 30 ⎜ (0.397 − 0.039) × 10μ × (2.1 + 3.47) ⎟
⎜+
⎟
2
⎝
⎠
= 190nF
(25)
LO 2
Design Example
In the design example, the ripple on each output inductor is
selected to be less than 20% of the rated output load current.
The inductances are calculated as:
Therefore, 220 nF is selected as the DC-blocking capacitor.
(V + VSR )(1 − D + Dloss1 )TS
= O
[STEP 8] Sensing Resistor
ΔiLO1
=
L202 =
=
(12 + 0.3)(1 − 0.397 + 0.039) × 10 μ
= 13.2μH
6
The pulse-by-pulse current limit of the FSFA-series switches
can be adjusted by changing R101 in Figure 11. It is
determined by the peak of the primary current obtained
using Equation (21) when the input voltage is maximized.
Due to the ripple current of the magnetizing inductance, the
maximum peak of the primary current happens when the
input voltage is maximized.
(VO + VSR )( D + Dloss 2 )TS
ΔiLO 2
(27)
When the voltage ripple on the capacitor is 30 V, the DCblocking capacitance is calculated using Equation (27) as:
In general, the current ripple on the output inductor is set to
10-20% of the rated output load current.
L201
⎛ Dloss1TS × I P1 Dloss 2TS × I P 2 ⎞
+
⎜
⎟
1 ⎜
2
2
⎟
≅
×
2Cb ⎜ ( D − Dloss1 )TS × ( I P1 + I P 2 ) ⎟
⎜+
⎟
2
⎝
⎠
Design Example
The output inductor current ripple is given as:
ΔiLO 2 =
(26)
Design Example
((−1.15) 2 + ( −1.15)(−2.51) + ( −2.51) 2 )
(1 − 0.397)
3
= 2.29 A.
+
ΔiLO1
27 kΩ
× 100 [kHz]
R105
.
(12 + 0.3)(0.397 + 0.060) × 10μ
= 9.4 μH
6
Design Example
To increase productivity, both output inductors are selected
as the same value, 15µH.
Continuing with the example, calculate the duty cycle at the
maximum input voltage and full-load conditions using
Equation (14).
[STEP 6] Operating frequency
In Figure 11, the operating frequency fS is obtained by using
the following equation when FSFA-series is used.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
www.fairchildsemi.com
11
AN-4153
APPLICATION NOTE
D@ 410V ,100%
⎛ n(VO + VSR ) I O Llk
+
1 − 1 − 4⎜⎜
nVinTS
⎝ αVin
=
2
An N-channel power MOSFET with 8mΩ of Rds(on) and
100V of the voltage rating, HUF75652G3, is selected for
both SRs with consideration of the voltage ringing and
overshoot.
⎞
⎟⎟
⎠
⎛
⎞
⎜ 6.5 ⋅ (12 + 0.3)
30 × 20 μ ⎟
+
1 − 1 − 4⎜
⎟
⎜ 600 μ 620 μ × 410 6.5 × 410 × 10 μ ⎟
⎝
⎠
=
2
= 0.338.
The voltages across the output inductors during powering
modes are:
VL 201min =
− VO
n
(1 − 0.458) ⋅ 370
=
− 12 = 19
6 .5
Then, the peak of the primary current is obtained combining
Equations (7), (9), (10), and (21) as:
I P2
(1 − D@ 370V ,100% ) ⋅ 370
Δi
I
= LO1 + I m + m
2
n
I LO1
I
I
=
+ (1 − D) LO 2 − D LO1
n
n
n
1⎛
I O Llk ⎞ (1 − D)Vin
⎟×
+ ⎜⎜ DTS −
2⎝
n(1 − D)Vin ⎟⎠ Lm + Llk
VL 201max =
(1 − 0) ⋅ 410
410
− VO =
− 12 = 51
n
6.5
VL 202 min =
0 × Vin
− VO = −12
n
VL 202 max =
15
15
15
=
+ (1 − 0.338)
− 0.338 ⋅
6.5
6.5
6.5
⎞ (1 − 0.338) ⋅ 410
1⎛
30 × 20 μ
⎟×
+ ⎜⎜ 0.338 × 10μ −
6.5 ⋅ (1 − 0.338) ⋅ 410 ⎟⎠
600μ + 20 μ
2⎝
D@ 370V ,100% × 370
n
− VO =
0.458 × 370
− 12 = 14
6.5
To protect the SRs, the gate signal has to be restricted ±20
V. The turns ratios between the output inductors and the
windings for the gate drivers are:
N3
=3
N1
= 3.72 A
Since the internal threshold voltage for the pulse-by-pulse
current limit is -0.58 V, 0.1 Ω is selected as the sensing
resistor, R101.
N4
=1
N2
[STEP 9] Synchronous Rectifier
[STEP 10] External Soft Start
The voltage stresses on the SRs are calculated as:
At startup, the duty cycle starts increasing slowly to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased to smoothly establish
the required output voltage. For the FSFA-series, the softstart time is internally implemented for 15ms when the
operating frequency is set to 100 kHz. In addition, to help
the soft-start operation, a capacitor and a resistor are
connected on the RT pin externally, as shown in Figure 11.
Before the power supply is powered on, the capacitor C107
remains fully discharged. After power-on, C107 becomes
charged gradually by the current through the RT pin, which
determines the operating frequency. The current through the
RT pin is inversely proportional to the total impedance of the
connected resistors. The total impedance during startup is
lower than that of the normal operation because R107 is
added on R105 in parallel, which means the operating
frequency decreases continuously from higher to nominal.
Eventually, C107 is fully charged to the RT pin voltage and
the operating frequency is determined by R105 only.
VSR1 =
DVin
n
(28)
VSR 2 =
(1 − D)Vin
n
(29)
For windings to drive the gate of the SRs, during powering
modes the voltages across the output inductors are:
VLO1 =
(1 − D)Vin
− VO
n
(30)
VLO 2 =
DVin
− VO
n
(31)
Design Example
Considering the worst case for each SR, the voltage stresses
on them are:
VQ101 =
DVin 0.5 × 410
=
= 32
n
6 .5
VQ102 =
(1 − D)Vin (1 − 0) × 410
=
= 64
n
6 .5
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
During C107 charging time, the operating frequency is higher
than during normal operation. In asymmetric PWM halfbridge converters, a switching period contains powering and
commutation periods. The energy cannot be transferred to
the output side during the commutation period. Since the DC
www.fairchildsemi.com
12
AN-4153
APPLICATION NOTE
link voltage applied to the VDL pin and the leakage
inductance of the main transformer are fixed, the powering
period over the switching period is shorter in high switching
frequencies. As C107 is charged, the switching frequency
decreases so that the powering period over the switching
period increases. It is helpful to start SMPS with the internal
soft-start time together.
4. Design Summary
Figures 13 and 14 show the full schematic of the reference
design and its transformer configuration. Table 1 shows the
detailed wire information of the transformer. The electrical
features of the transformer are described in Table 2.
Design Example
In the design example, 2.2 µF and 12 kΩ are selected as C107
and R107, respectively.
Figure 13. Full Schematic with Components Values of the Reference Design
1
16
2
15
3
14
4
13
NP
NS
5
12
6
11
7
10
3 mm
3 mm
8
1
27
28
29
30
31
32
33
34
35
36
37
38
39
26
25
24
23
22
21
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
5
4
9
6
9
8
3
2
1
16
Figure 14. Transformer Construction of the Reference Design
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
www.fairchildsemi.com
13
AN-4153
APPLICATION NOTE
Table 1. Transformer Winding Specifications
Pin
No.
Winding
(start → end)
Wire
Turns
Winding Method
39 T
Solenoid
6T
Solenoid
Insulation Tape (25 um) 1T
Litz wire (AWG38×100 strands) (1)
1Æ8
NP
2
Insulation Tape (25 um) 1T
NS
1
16 Æ 9
Litz wire (AWG36×250 strands)
NOTE:
1. Insulation tape (25 µm, 1T each) should be inserted between the layers.
Table 2. Transformer Electrical Characteristics
Pin
Spec.
Remark
Magnetizing Inductance (Lm)
1－8
600 µH (typical)
(600 µH ± 5%)
Leakage Inductance (Llk)
1－8
20 µH ± 10%
100 kHz, 1 V
All other pins open
100 kHz, 1 V
All other pins shorted
illustrated in Figure 6(a). As can be seen in Figure 17, since
the winding voltage decreases to the negative at the turn-off
transition in the upper waveforms, the SRs are turned off
more rapidly and definitely than in the transformer coupling
case. In Figure 17, the smaller negative parts in the inductor
coupling case are shown compared to the transformer
coupling case. The smaller negative parts allow the power
losses on the gate driver circuit for SRs to be reduced.
5. Experimental Results
Figures 15 and 16 show the experimental waveforms of the
converter designed in the previous chapter at the nominal
input and the full-load condition. The gate signal of S1, the
primary- and secondary-side voltages across the main
transformer, and the primary current are shown in Figure 15.
These waveforms are consistent with the theoretical
analysis, including the ZVS operation. The output inductor
currents and the SRs’ currents are shown in Figure 16. The
output inductor currents are unbalanced due to the duty
cycle and the parasitic components, which means the
averaged magnetizing current is smaller than that of the
center-tapped configuration.[1]
The ZVS operations at various load conditions are shown in
Figure 18. The drain voltage and the gate signal of the lower
side switch are displayed. As designed in the previous
chapter, the converter shows ZVS operation downs to 30%
load condition.
The efficiency of the converter is shown in Figure 19. The
measured efficiencies are 93.7%, 94.6%, and 93.1% at 20%,
50%, and 100% of the rated load condition, respectively. It
shows a marginal performance so that the 85 PLUS program
can be achieved with well-designed PFC and DC-DC stages.
Figure 17 shows the winding voltages for the gate driver
circuits of SRs at the full-load condition. The upper
waveforms are for the inductor coupling illustrated in Figure
6(b), while the lower ones are for the transformer coupling
Figure 16. Waveforms for the Secondary Side
Figure 15. Experimental Waveforms
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
www.fairchildsemi.com
14
AN-4153
APPLICATION NOTE
96
Efficiency [%]
95
93.7%
94
94.6%
93
93.1%
92
91
90
89
88
10
20
30
40
50
60
70
80
90
100
Load [%]
Figure 19. Measured Efficiency of the Designed Converter
6. References
[1] Hong Mao, Songquan Deng, Yangyang wen, and Issa
Batarseh, “Unified Steady-State Model and DC Analysis of
Half-Bridge DC-DC Converters with Current Doubler
Rectifier,” APEC '04. Nineteenth Annual IEEE, Vol. 2,
2004, pp. 786-791.
Figure 17. Gate Signals for SR; Upper Waveforms
Use Output Inductors; Lower Waveforms Use the
Transformer
[2] Yu-Chieh Hung, Fu-San Shyu, Chih Jung Lin, and YenShin Lai, “Design and Implementation of Symmetrical HalfBridge DC-DC Converter”, The Fifth International
Conference on PEDS 2003. Vol. 1, Nov. 2003 pp. 338-342.
vgs_S1 (20V/div.)
[3] Panov, Y. and Jovanovic, M.M., “Design and
Performance Evaluation of Low-Voltage / High-Current
DC/DC On-board Modules,” IEEE Transactions on Power
Electronics, Vol. 16, Issue 1, Jan. 2001 pp. 26-33.
vds_S1 (200V/div.)
(a)
ZVS fail begins
vgs_S1 (20V/div.)
vds_S1 (200V/div.)
(b)
Figure 18. ZVS Verification; (a) at 40% Load; (b)
at 30% Load
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
www.fairchildsemi.com
15
AN-4153
APPLICATION NOTE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 12/9/08
2.
A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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