FEATURES FUNCTIONAL BLOCK DIAGRAM Reflective, 50 Ω design Low insertion loss: 0.6 dB typical to 2.0 GHz High isolation: 50 dB typical to 2.0 GHz High power handling RF input power, continuous wave (CW) at TCASE = 85°C 43 dBm maximum operating 46.5 dBm absolute maximum rating High linearity 0.1 dB compression (P0.1dB): 46 dBm typical Input third-order intercept (IP3): 68 dBm typical to 2 GHz ESD ratings Human body model (HBM): 2 kV, Class 2 Charged device model (CDM): 1.25 kV Single positive supply: VDD = 5 V Positive control, TTL-compatible: VCTL = 0 V or VDD 24-lead, 4 mm × 4 mm LFCSP package (16 mm2) VCTL ADRF5130 RF1 RF2 RFC 14081-001 Data Sheet High Power, 44 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 3.5 GHz ADRF5130 Figure 1. APPLICATIONS Cellular/4G infrastructure Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement GENERAL DESCRIPTION The ADRF5130 is a high power, reflective, 0.7 GHz to 3.5 GHz, silicon, single-pole, double-throw (SPDT) switch in a leadless, surface-mount package. The switch is ideal for high power and cellular infrastructure applications, like long-term evolution (LTE) base stations. The ADRF5130 has high power handling of 43 dBm (maximum), a low insertion loss of 0.6 dB, input third-order intercept of 68 dBm (typical), and 0.1 dB compression (P0.1dB) Rev. A of 46 dBm. On-chip circuitry operates at a single, positive supply voltage of 5 V and typical supply current of 1.06 mA, making the ADRF5130 an ideal alternative to pin diode-based switches. The device comes in a RoHS compliant, compact, 24-lead, 4 mm × 4 mm LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5130* Product Page Quick Links Last Content Update: 01/26/2017 Comparable Parts Design Resources View a parametric search of comparable parts • ADRF5130 Evaluation Board • • • • Documentation Discussions Data Sheet • ADRF5130: High Power, 44 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 3.5 GHz Data Sheet View all ADRF5130 EngineerZone Discussions Evaluation Kits Tools and Simulations ADRF5130 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Sample and Buy Visit the product page to see pricing options • ADRF5130 S-parameters Technical Support Reference Materials Submit a technical question or find your regional support number Press • Analog Devices’ Silicon Switch Reduces Size and Power Consumption in Cellular Radio RF Front Ends *This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. 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ADRF5130 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Insertion Loss, Isolation, Return Loss, and IP3 ........................6 General Description ......................................................................... 1 Theory of Operation .........................................................................7 Revision History ............................................................................... 2 Applications Information .................................................................8 Specifications..................................................................................... 3 Evaluation Board ...........................................................................8 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 10 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 10 Pin Configuration and Function Descriptions ............................. 5 REVISION HISTORY 1/2017—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 10 7/2016—Revision 0: Initial Version Rev. A | Page 2 of 10 Data Sheet ADRF5130 SPECIFICATIONS VDD = 5 V, VCTL = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Symbol ISOLATION RFC to RF1 or RF2 (Worst Case) RF1 to RF2 (Worst Case) RETURN LOSS RFC RFC to RF1 or RF2 SWITCHING SPEED Time Rise and Fall On and Off RADIO FREQUENCY (RF) SETTLING TIME INPUT POWER 0.1 dB Compression INPUT THIRD-ORDER INTERCEPT RECOMMENDED OPERATING CONDITIONS Voltage Range Bias Control Maximum RF Input Power TCASE = 105°C TCASE = 85°C TCASE = 25°C Case Temperature Range DIGITAL INPUT CONTROL VOLTAGE Low Range High Range SUPPLY CURRENT tRISE, tFALL tON, tOFF P0.1dB IP3 Test Conditions/Comments Min 0.7 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 0.6 0.7 Unit GHz dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 50 46 51 41 dB dB dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 23 17 21 17 dB dB dB dB 90% to 10% of RF output 50% VCTL to 10% to 90% of RF output 50% VCTL to 0.1 dB margin of final RF output 155 750 1.8 ns ns µs 46 dBm 68 65 dBm dBm Two-tone input power = 25 dBm/tone 0.7 GHz to 2 GHz 2 GHz to 3.5 GHz 0.7 GHz to 3.5 GHz VDD VCTL Typ 4.5 0 5.4 VDD V V −40 41 43 38 44 44.5 +105 dBm dBm dBm dBm dBm °C 0 1.3 0.8 5.0 V V mA Continuous wave Continuous wave 8 dB peak to average ratio (PAR) LTE, average 8 dB PAR LTE, single event (<10 sec), average Continuous wave TCASE Max 3.5 VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C at <1 µA typical VIL VIH IDD VDD = 5 V Rev. A | Page 3 of 10 1.06 ADRF5130 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Bias Voltage Range (VDD) Control Voltage Range (VCTL) RF Input Power,1 Continuous Wave Channel Temperature Storage Temperature Range Operating Temperature Range Peak Reflow Temperature (MSL3)2 Thermal Resistance (Channel to Package Bottom) Electrostatic Discharge (ESD) Sensitivity HBM CDM 1 2 Rating −0.3 V to +5.5 V −0.3 V to +5.5 V 46.5 dBm 135°C −65°C to +150°C −40°C to +105°C 260°C 17°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 2 kV (Class 2) 1.25 kV For the recommended operating conditions, see Table 1. See the Ordering Guide section. Rev. A | Page 4 of 10 Data Sheet ADRF5130 19 GND 20 GND 21 VCTL 22 VDD 23 GND 24 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 18 GND GND 2 17 GND ADRF5130 16 RF2 TOP VIEW (Not to Scale) GND 4 15 GND GND 12 RFC 10 GND 11 GND 9 13 GND GND 8 14 GND GND 6 GND 7 GND 5 PACKAGE BASE NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 14081-002 RF1 3 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 4 to 9, 11 to 15, 17 to 20, 23, 24 Mnemonic GND 3 RF1 10 RFC 16 RF2 21 VCTL 22 VDD EPAD Description Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 3 for the GND interface schematic. RF Output Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Input Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Output Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 4 and the recommended digital input control voltage range in Table 1. Supply Voltage. See Figure 4 for the VDD interface schematic. Exposed Pad. Exposed pad must be connected to RF/dc ground. Table 4. Truth Table Signal Path State Control Input (VCTL) State Low High RFC to RF1 Off On RFC to RF2 On Off INTERFACE SCHEMATICS VCTL 14081-003 GND 14081-004 VDD Figure 4. Control Interface Schematic Figure 3. GND Interface Schematic Rev. A | Page 5 of 10 ADRF5130 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –0.5 –0.5 –1.0 –1.5 –2.0 –1.0 –1.5 +105°C +85°C +25°C –40°C –2.0 RF1 RF2 0 1 2 3 4 5 FREQUENCY (GHz) –2.5 14081-005 –2.5 0 3 4 5 Figure 8. Insertion Loss vs. Frequency over Temperature at VDD = 5 V 0 RF1 RF2 –10 RF1 ON RF2 ON –10 –20 –20 –30 ISOLATION (dB) –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 0 1 2 3 4 5 FREQUENCY (GHz) –80 14081-006 –90 0 1 2 3 4 5 FREQUENCY (GHz) Figure 6. Isolation Between RFC to RF1 or RF2 vs. Frequency at VDD = 5 V 14081-009 ISOLATION (dB) 2 FREQUENCY (GHz) Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V 0 1 14081-008 INSERTION LOSS (dB) INSERTION LOSS (dB) INSERTION LOSS, ISOLATION, RETURN LOSS, AND IP3 Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V, Switch Mode On 74 0 RFC RF1 RF2 –5 72 –15 70 IP3 (dBm) –20 –25 68 66 –30 –35 +105°C +85°C +25°C –40°C 64 –45 0 1 2 3 4 5 FREQUENCY (GHz) 14081-007 –40 Figure 7. Return Loss vs. Frequency at VDD = 5 V (RFC, RF1, and RF2) 62 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (GHz) Figure 10. IP3 vs. Frequency over Temperature, VDD = 5 V Rev. A | Page 6 of 10 4.0 14081-010 RETURN LOSS (dB) –10 Data Sheet ADRF5130 THEORY OF OPERATION The ADRF5130 requires a single-supply voltage applied to the VDD pin. Bypass capacitors are recommended on the supply line to minimize RF coupling. A digital control voltage applied to the VCTL pin controls the ADRF5130. A small bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The ADRF5130 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RFx pins are dc-coupled, and dc blocking capacitors are required on the RF lines. The design is bidirectional; the input and outputs are interchangeable. The ideal power-up sequence of the ADRF5130 is as follows: 1. 2. 3. 4. Connect to GND. Power up VDD. Power up the digital control input. Powering the digital control input before the VDD supply can inadvertently forward-bias and damage the ESD protection structures. Power up the RF input. Depending on the logic level applied to the VCTL pin, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path is provided from the input to the output, while the other RF output port (for example, RF2) is set to off mode, by which the output is isolated from the input. Table 5. Switch Operation Mode Switch Mode Digital Control Input (VCTL) 0 1 RFC to RF1 Off mode: the RF1 port is isolated from the RFC port and is internally terminated to a 50 Ω load to absorb the applied RF signals. On mode: a low insertion loss path from the RFC port to the RF1 port. Rev. A | Page 7 of 10 RFC to RF2 On mode: a low insertion loss path from the RFC port to the RF2 port. Off mode: the RF2 port is isolated from the RFC port and is internally terminated to a 50 Ω load to absorb the applied RF signals. ADRF5130 Data Sheet APPLICATIONS INFORMATION Generate the evaluation PCB used in the application circuit shown in Figure 11 with proper RF circuit design techniques. Signal lines at the RF port must have a 50 Ω impedance, and the package ground leads and backside ground slug must connect directly to the ground plane, as shown in Figure 14. G = 13mil W = 18mil 2oz Cu (2.7mil) 2oz Cu (2.7mil) 2oz Cu (2.7mil) RO4350 = 10mil T = 2.7mil H = 10mil 1oz Cu (1.3mil) R1 VCTL VDD C6 C5 C7 C4 GND 19 14 6 13 GND GND C3 RF2 C12 TO C15 12 GND GND GND GND GND RF2 TOTAL THICKNESS = 62mil 15 5 11 4 GND FR4 1oz Cu (1.3mil) FR4 1oz Cu (1.3mil) C18 TO C21 14081-011 C2 RFC FR4 1oz Cu (1.3mil) Figure 11. Application Circuit FR4 EVALUATION BOARD 1oz Cu (1.3mil) The ADRF5130 evaluation board has eight metal layers and dielectrics between each layer (see Figure 12). The top and the bottom metal layers have copper thickness of 2 oz (2.7 mil), whereas the metal layers in between them have 1 oz copper (1.3 mil) thickness. The top dielectric material is 10 mil Rogers RO4350, which exhibits a very low thermal coefficient, offering control over thermal rise of the board. The dielectrics between other metal layers are FR-4. The overall board thickness achieved is 62 mil. FR4 2oz Cu (2.7mil) 14081-013 20 GND VCTL 22 16 7 GND 17 3 10 GND 18 RFC GND 1oz Cu (1.3mil) 2 8 RF1 1 9 C8 TO C11 GND GND C1 21 GND 24 RF1 GND GND GND 23 VDD FR4 Figure 12. Evaluation Board Cross-Sectional View 1.500 0.050 14081-014 The top copper layer has all RF and dc traces, whereas the other seven layers provide good ground and help to handle the thermal rise on the evaluation board caused by the high power of the ADRF5130. In addition, for proper thermal grounding, many via holes are provided around the transmission lines and under the exposed pad of the package. RF transmission lines on the ADRF5130 evaluation board are coplanar wave guide design with an 18 mil width and a ground spacing of 13 mil. For controlling the thermal rise of the ADRF5130 evaluation board at high temperatures and power levels, it is recommended to use a heat sink and a mini dc fan. 1.500 Figure 13 shows the top view of the ADRF5130 evaluation board. 0.050 Figure 13. Evaluation Board Top View Rev. A | Page 8 of 10 Data Sheet ADRF5130 respectively. The connectors used are 2.9 mm end launch SMA connectors. Unpopulated capacitor positions are available on all RF traces to provide extra matching. A through transmission line (THRU CAL) is available on the ADRF5130 evaluation board that can measure board loss on the printed circuit board (PCB). Figure 14 shows the ADRF5130 evaluation board with all components populated. The VDD supply port connects to TP1. The VDD supply trace has three bypass capacitors 100 pF, 1 µF, and 1 nF. The TP2 test point connects to the control voltage port (VCTL). The control trace has a 100 pF bypass capacitor and 0 Ω resistor. The ground reference connects to GND. A 100 pF dc blocking capacitor is used on all RF traces that connect the RF1, RF2, and RFC ports to the J1, J2, and J3 connectors, Table 6 shows the bill of materials for the ADRF5130 evaluation board. The evaluation board shown in Figure 14 is available from Analog Devices, Inc., upon request. J1 GND VDD TP3 RFC C2 C4 C5 C6 4321 J2 TP1 THRU CAL RF1 C1 U1 R1 C7 RF2 1234 4321 600-01532-00-2 TP2 C3 VCTL 14081-012 J3 Figure 14. ADRF5130-EVALZ Evaluation Board Table 6. Bill of Materials for the ADRF5130-EVALZ Evaluation Board Reference Designator J1 to J3 C1 to C4, C7 C5 C6 C8 to C15, C18 to C21 R1 TP1, TP2, TP3 U1 PCB 1 Description PCB mount SMA connectors 100 pF capacitors, 0402 package 1 nF capacitor, 0402 package 1 µF capacitor, 0402 package Do not insert (DNI) 0 Ω resistor, 0402 package Surface-mount test points ADRF5130 SPDT switch 600-01532-00-2 1 evaluation PCB; circuit board material: Rogers RO4350 or Arlon 25FR Reference this evaluation board number when ordering the complete evaluation board. Rev. A | Page 9 of 10 ADRF5130 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 18 0.50 BSC 2.85 2.70 SQ 2.55 EXPOSED PAD 13 0.50 0.40 0.30 TOP VIEW PKG-004926/PKG-004866 0.90 0.85 0.80 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 05-25-2016-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 15. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.85 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5130BCPZ ADRF5130BCPZ-R7 ADRF5130-EVALZ 1 2 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C MSL Rating2 MSL3 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS-Compliant Part. See the Absolute Maximum Ratings section. ©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14081-0-1/17(A) Rev. A | Page 10 of 10 Package Option CP-24-16 CP-24-16