LTC2755 Quad Current Output 12-/14-/16-Bit SoftSpan DACs with Parallel I/O FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Program or Pin-Strap Six Output Ranges Unipolar: 0V to 5V, 0V to 10V Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V Maximum 16-Bit INL Error: ±1 LSB over Temperature Low 1μA (Maximum) Supply Current Guaranteed Monotonic over Temperature Low Glitch Impulse 1nV•s 2.7V to 5.5V Single Supply Operation 2μs Settling Time to ±1 LSB Parallel Interface with Readback of All Registers Asynchronous CLR Pin Clears DAC Outputs to 0V in Any Output Range Power-On Reset to 0V 64-Pin 9mm × 9mm QFN Package The LTC®2755 is a family of quad 12-, 14-, and 16-bit multiplying parallel-input, current-output DACs. These DACs operate from a single 2.7V to 5.5V supply and are all guaranteed monotonic over temperature. The LTC2755A-16 provides 16-bit performance (±1LSB INL and DNL) over temperature without any adjustments. These SoftSpan™ DACs offer six output ranges—two unipolar and four bipolar—that can be programmed through the parallel interface, or pinstrapped for operation in a single range. The LTC2755 DACs use a bidirectional input/output parallel interface that allows readback of any internal register, including the DAC output span settings. A power-on reset circuit resets the DAC outputs to 0V when power is initially applied. A logic low on the CLR pin asynchronously clears the DACs to 0V in any output range. APPLICATIONS ■ ■ ■ ■ The parts are specified over commercial and industrial temperature ranges. High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Acquisition Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7034735, 7256721. TYPICAL APPLICATION SoftSpan Parallel IOUT DAC Selector Guide Quad 16-Bit VOUT DAC with Software-Selectable Ranges VREF1 5V + – ROFSA RIN1 RCOM1 Part Number REFA REFB RVOSB IOUT1A DAC B DAC A VDD I/O PORT DATA I/O LTC2755-16 IOUT1C IOUT1D IOUT2D DAC C DAC D IOUT2C RVOSC RVOSD GND LTC2755 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 5V 0.1μF 0.4 – + VOUTC 0.2 0.0 –0.2 –0.4 –0.6 25°C 90°C –45°C –0.8 MSPAN ROFSD REFD REFC VREF2 5V + – – + QUAD LTC2753 LTC2755-16 Integral Nonlinearity (INL) VOUTB RFBC I/O PORT RFBD VOUTD + – RFBB RFBA SPAN I/O IOUT1B INL (LSB) VOUTA IOUT2B IOUT2A DUAL LTC2751 ROFSB RVOSA + – SINGLE RCOM2 RIN2 ROFSC 2755 TA01 –1.0 0 16384 32768 CODE 49152 65535 2755 TA01b 2755f 1 LTC2755 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Operating Temperature Range LTC2755C..................................................... 0°C to 70°C LTC2755I .................................................. –40°C to 85°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 150°C IOUT1X, IOUT2X, RCOMX to GND................................±0.3V RVOSX, RFBX, ROFSX, RINX, REFX to GND..................±15V VDD to GND .................................................. –0.3V to 7V Digital Inputs and Digital I/O to GND ..........................–0.3V to VDD+0.3V (max 7V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 S2 1 IOUT2A 2 GND 3 D11 4 D10 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 11 D3 12 GND 13 IOUT2D 14 VDD 15 A2 16 65 RIN1 RCOM1 REFA ROFSA RFBA IOUT1A RVOSA RVOSB IOUT1B RFBB ROFSB REFB S1 WR UPD READ RIN1 RCOM1 REFA ROFSA RFBA IOUT1A RVOSA RVOSB IOUT1B RFBB ROFSB REFB S1 WR UPD READ RIN1 RCOM1 REFA ROFSA RFBA IOUT1A RVOSA RVOSB IOUT1B RFBB ROFSB REFB S1 WR UPD READ PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D/S S0 IOUT2B GND NC NC NC NC NC NC D0 D1 D2 GND IOUT2C MSPAN S2 1 IOUT2A 2 GND 3 D13 4 D12 5 D11 6 D10 7 D9 8 D8 9 D7 10 D6 11 D5 12 GND 13 IOUT2D 14 VDD 15 A2 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 65 D/S S2 1 S0 IOUT2A 2 IOUT2B GND 3 GND D15 4 NC D14 5 NC D13 6 NC D12 7 NC D11 8 D0 D10 9 D1 D9 10 D2 D8 11 D3 D7 12 D4 GND 13 GND IOUT2D 14 IOUT2C VDD 15 MSPAN A2 16 65 A1 A0 GND CLR REFD ROFSD RFBD IOUT1D RVOSD RVOSC IOUT1C RFBC ROFSC REFC RCOM2 RIN2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A1 A0 GND CLR REFD ROFSD RFBD IOUT1D RVOSD RVOSC IOUT1C RFBC ROFSC REFC RCOM2 RIN2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D/S S0 IOUT2B GND NC NC D0 D1 D2 D3 D4 D5 D6 GND IOUT2C MSPAN A1 A0 GND CLR REFD ROFSD RFBD IOUT1D RVOSD RVOSC IOUT1C RFBC ROFSC REFC RCOM2 RIN2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LTC2755-12 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN LTC2755-14 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN LTC2755-16 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 28°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 28°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 28°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2755CUP-12#PBF LTC2755CUP-12#TRPBF LTC2755UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2755IUP-12#PBF LTC2755IUP-12#TRPBF LTC2755UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2755CUP-14#PBF LTC2755CUP-14#TRPBF LTC2755UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2755IUP-14#PBF LTC2755IUP-14#TRPBF LTC2755UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2755BCUP-16#PBF LTC2755BCUP-16#TRPBF LTC2755UP-16 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2755BIUP-16#PBF LTC2755BIUP-16#TRPBF LTC2755UP-16 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2755ACUP-16#PBF LTC2755ACUP-16#TRPBF LTC2755UP-16 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2755AIUP-16#PBF LTC2755AIUP-16#TRPBF LTC2755UP-16 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2755f 2 LTC2755 ELECTRICAL CHARACTERISTICS VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTC2755-12 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2755-14 MAX MIN TYP LTC2755B-16 MAX MIN TYP MAX LTC2755A-16 MIN TYP MAX UNITS Static Performance Resolution ● 12 12 14 16 16 Bits Monotonicity ● DNL Differential Nonlinearity ● ±1 ±1 ±1 ±0.2 ±1 LSB INL Integral Nonlinearity ● ±1 ±1 ±2 ±0.4 ±1 LSB GE Gain Error All Output Ranges ±5 ±20 ±2 ±12 LSB GETC Gain Error Temperature Coefficient ΔGain/ΔTemp BZE Bipolar Zero Error All Bipolar Ranges BZSTC Bipolar Zero Temperature Coefficient PSR Power Supply Rejection VDD = 5V, ±10% VDD = 3V, ±10% ● ● ILKG IOUT1 Leakage Current TA = 25°C TMIN to TMAX ● CIOUT1 Output Capacitance Full-Scale Zero Scale ● 14 ±0.5 ±2 ±0.6 ● 16 ±1 ±0.6 ±0.2 ±1 ±0.5 ±0.5 ±0.05 ±2 ±5 ±3 75 45 ±0.6 ±12 ±2 ±5 75 45 ±8 ±0.5 ±0.4 ±1 ±0.05 ppm/°C ±1 ±0.5 ±0.1 ±0.25 ±0.05 Bits ±0.6 ±0.5 ±0.025 ±0.06 16 ppm/°C ±0.03 ±0.2 ±0.1 ±0.5 ±2 ±5 ±0.05 75 45 LSB LSB/V LSB/V ±2 ±5 nA nA 75 45 pF pF VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP R1, R2, R3, R4 Reference Inverting Resistors (Note 4) RREF DAC Input Resistance RFB Feedback Resistor MAX UNITS ● 16 20 kΩ ● 8 10 kΩ (Note 3) ● 8 10 kΩ (Note 3) ● 16 20 kΩ ● 800 1000 kΩ Resistances (Note 3) ROFS Bipolar Offset Resistor RVOS Offset Adjust Resistor Dynamic Performance THD Output Settling Time 0V to 10V Range, 10V Step. To ±0.0015% FS (Note 5) 2 μs Glitch Impulse (Note 6) 1 nV•s Digital-to-Analog Glitch Impulse (Note 7) 1 nV•s Reference Multiplying BW 0V to 5V Range, VREF = 3VRMS, code = Full Scale, –3dB BW 2 MHz Multiplying Feedthrough Error 0V to 5V Range, VREF = ±10V, 10kHz Sine Wave 0.5 mV Analog Crosstalk (Note 8) –109 dB Total Harmonic Distortion (Note 9) Multiplying –110 Output Noise Voltage Density (Note 10) at IOUT1 13 dB ⎯ ⎯z nV/√H 2755f 3 LTC2755 ELECTRICAL CHARACTERISTICS VDD = 5V, VREF = 5V unless otherwise specified. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply ● VDD Supply Voltage IDD Supply Current, VDD Digital Inputs = 0V or VDD ● 2.7 VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V ● ● VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.5V ● ● 0.8 0.6 V V IIN Digital Input Current VIN = GND to VDD ● ±1 μA CIN Digital Input Capacitance VIN = 0V (Note 11) ● 6 pF VOH IOH = 200μA 2.7V ≤ VDD ≤ 5.5V ● VOL IOL = 200μA 2.7V ≤ VDD ≤ 5.5V ● 0.4 V 0.5 5.5 V 1 μA Digital Inputs 2.4 2 V V Digital Outputs TIMING CHARACTERISTICS VDD – 0.4 V The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 4.5V to 5.5V Write and Update Timing t1 I/O Valid to WR Rising Edge Set-Up ● 7 ns t2 I/O Valid to WR Rising Edge Hold ● 7 ns t3 WR Pulse Width Low ● 15 ns t4 UPD Pulse Width High ● 15 ns t5 UPD Falling Edge to WR Falling Edge No Data Shoot-Through ● 0 ns t6 WR Rising Edge to UPD Rising Edge (Note 11) ● 0 ns t7 D/S Valid to WR Falling Edge Set-Up Time ● 7 ns t8 WR Rising Edge to D/S Valid Hold Time ● 7 ns t9 A2-A0 Valid to WR Falling Edge Setup Time ● 5 ns t10 WR Rising Edge to A2-A0 Valid Hold Time ● 0 ns t11 A2-A0 Valid to UPD Rising Edge Setup Time ● 9 ns t12 UPD Falling Edge to A2-A0 Valid Hold Time ● 7 ns Readback Timing t13 WR Rising Edge to READ Rising Edge ● 7 ns t14 READ Falling Edge to WR Falling Edge (Note 11) ● 20 ns t15 READ Rising Edge to I/O Propagation Delay CL = 10pF ● t26 A2-A0 Valid to READ Rising Edge Setup Time t27 READ Falling to A2-A0 Valid Hold Time (Note 11) 40 ns ● 20 ns ● 0 ns 2755f 4 LTC2755 TIMING CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS t17 UPD Valid to I/O Propagation Delay CL = 10pF ● MIN TYP MAX t18 D/S Valid to READ Rising Edge (Note 11) ● 7 ns t19 READ Rising Edge to UPD Rising Edge No Update ● 0 ns t20 UPD Falling Edge to READ Falling Edge No Update ● 0 ns 26 UNITS ns t22 READ Falling Edge to UPD Rising Edge (Note 11) ● 7 ns t23 I/O Bus Hi-Z to READ Rising Edge (Note 11) ● 0 ns t24 READ Falling Edge to I/O Bus Active (Note 11) ● 20 ns ● 15 ns CLR Timing t25 CLR Pulse Width Low VDD = 2.7V to 3.3V Write and Update Timing t1 I/O Valid to WR Rising Edge Set-Up ● 15 ns t2 I/O Valid to WR Rising Edge Hold ● 15 ns t3 WR Pulse Width Low ● 30 ns t4 UPD Pulse Width High ● 30 ns t5 UPD Falling Edge to WR Falling Edge No Data Shoot-Through ● 0 ns t6 WR Rising Edge to UPD Rising Edge (Note 11) ● 0 ns t7 D/S Valid to WR Falling Edge Set-Up Time ● 7 ns t8 WR Rising Edge to D/S Valid Hold Time ● 7 ns t9 A2-A0 Valid to WR Falling Edge Setup Time ● 7 ns t10 WR Rising Edge to A2-A0 Valid Hold Time ● 0 ns t11 A2-A0 Valid to UPD Rising Edge Setup Time ● 15 ns t12 UPD Falling Edge to A2-A0 Valid Hold Time ● 15 ns ● 10 ns 35 ns Readback Timing t13 WR Rising Edge to Read Rising Edge t14 Read Falling Edge to WR Falling Edge (Note 11) ● t15 Read Rising Edge to I/O Propagation Delay CL = 10pF ● t26 A2-A0 Valid to READ Rising Edge Setup Time ● 35 0 55 ns ns t27 READ Falling to A2-A0 Valid Hold Time (Note 11) ● t17 UPD Valid to I/O Propagation Delay CL = 10pF ● t18 D/S Valid to Read Rising Edge (Note 11) ● 12 ns t19 Read Rising Edge to UPD Rising Edge No Update ● 0 ns t20 UPD Falling Edge to Read Falling Edge No Update ● 0 ns ns 45 ns 2755f 5 LTC2755 TIMING CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.3V t22 READ Falling Edge to UPD Rising Edge (Note 11) ● 10 ns t23 I/O Bus Hi-Z to Read Rising Edge (Note 11) ● 0 ns t24 Read Falling Edge to I/O Bus Active (Note 11) ● 35 ns ● 20 ns CLR Timing CLR Pulse Width Low t25 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Because of the proprietary SoftSpan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the IOUT1X and IOUT2X pins are held at ground. Note 4: R1 measured from RIN1 to RCOM1; R2 measured from REFA to RCOM1; R3 measured from RIN2 to RCOM2; R4 measured from REFC to RCOM2. Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time of 1.7μs can be achieved by optimizing the time constant on an individual basis. See Application Note 74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time. Note 6: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1469; CFB = 27pF. Note 7. Full-scale transition; REF = 0V. Note 8. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA, expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Crosstalk between other DAC channels is similar or better. Note 9. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1469. Note 10. Calculation from Vn = √4⎯ ⎯k⎯T⎯R⎯B, where k = 1.38E-23 J/°K (Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale. Note 11. Guaranteed by design, not subject to test. TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2755-16 Integral Nonlinearity (INL) 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.2 0.2 0.0 –0.2 INL (LSB) 0.4 DNL (LSB) INL (LSB) INL vs Temperature Differential Nonlinearity (DNL) 1.0 1.0 0.0 –0.2 0.0 –0.4 –0.4 –0.6 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 –1.0 –40 16384 32768 CODE 49152 65535 2755 G01 0 16384 32768 CODE 49152 65535 2755 G02 –INL –0.2 –0.4 0 +INL –20 20 40 0 60 TEMPERATURE (°C) 80 2755 G04 2755f 6 LTC2755 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2755-16 DNL vs Temperature VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 8 16 4 8 VDD = 5V 12 VREF = 5V ±10V RANGE VDD = 5V 6 VREF = 5V ±10V RANGE +DNL 0.0 –DNL –0.2 0.5ppm/°C (TYP) 2 0 0.6ppm/°C (TYP) 4 GE (LSB) 0.2 BZE (LSB) 0.4 0 –2 –4 –4 –8 –6 –12 –0.4 –0.6 –0.8 20 40 0 60 TEMPERATURE (°C) –8 –40 80 –20 –16 –40 80 20 40 0 60 TEMPERATURE (°C) 2755 G05 20 40 0 60 TEMPERATURE (°C) –20 80 2755 G07 2755 G06 INL vs VREF DNL vs VREF 1.0 1.0 0.6 0.6 VDD = 5V 0.8 ±5V RANGE VDD = 5V 0.8 ±5V RANGE 0.4 0.4 0.0 –INL –INL –0.2 INL (LSB) +INL +INL 0.2 0.2 0.0 +DNL +DNL –DNL –DNL –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –10 –8 –6 –1.0 –10 –8 –6 4 2 0 2 VREF (V) 4 6 8 10 2755 G08 1.0 0 0.8 0.6 –20 0.4 +INL 0.2 0.0 4 2 0 2 VREF (V) –INL –0.2 –0.4 –0.6 –40 –60 –80 –100 3 3.5 6 8 10 2755 G09 ALL BITS ON D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 UNIPOLAR 5V OUTPUT RANGE LT1469 OUTPUT AMPLIFIER CFEEDBACK = 8.2pF –0.8 –1.0 2.5 4 Multiplying Frequency Response vs Digital Code INL vs VDD ATTENUATION (dB) –20 INL (LSB) –1.0 –40 INL (LSB) DNL (LSB) Gain Error vs Temperature Bipolar Zero vs Temperature 1.0 4 4.5 5 5.5 VDD (V) 2755 G09b –120 100 ALL BITS OFF 1k 10k 100k FREQUENCY (Hz) 1M 10M 2755 G10a 2755f 7 LTC2755 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2755-14 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) 1.0 0.0 –0.2 0.0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 4096 0 8192 CODE 4096 0 16383 12288 8192 CODE 16383 12288 2755 G12 2755 G11 LTC2755-12 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.0 –0.2 0.0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 1024 0 2048 CODE –1.0 4095 3072 0 1024 2755 G13 LTC2755-12, LTC2755-14, LTC2755-16 Supply Current vs Logic Input Voltage 2048 CODE Supply Current vs Update Frequency 10 2 1.75 VDD = 5V 10 5 1 1.5 SUPPLY CURRENT (mA) LOGIC THRESHOLD (V) 15 4095 2755 G14 Logic Threshold vs Supply Voltage 20 SUPPLY CURRENT (mA) 3072 RISING 1.25 FALLING 1 0.1 0.01 VDD = 5V VDD = 3V 0.001 0.75 VDD = 3V 0.5 0 0 2 3 4 1 DIGITAL INPUT VOLTAGE (V) 5 0.0001 2.5 3 3.5 4 4.5 5 5.5 VDD (V) 2755 G21 2755 G17 10 100 1k 10k 100k UPDATE FREQUENCY (Hz) 1M 2755 G19a 2755f 8 LTC2755 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2755-12, LTC2755-14, LTC2755-16 Settling 0V to 10V Midscale Glitch UPD 5V/DIV UPD 5V/DIV UNIPOLAR 5V OUTPUT RANGE LT1469 OUTPUT AMPLIFIER VOUT 2mV/DIV 1nV • s TYP C FEEDBACK = 27pF GATED SETTLING WAVEFORM 250μV/DIV VDD = 5V, VREF = 5V 500ns/DIV 2755 G20 RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. 500ns/DIV USING LT1469 AMP CFEEDBACK = 12pF 0V TO 10V STEP 2755 G10 PIN FUNCTIONS S2 (Pin 1): Span I/O Bit 2. Pins S0, S1 and S2 are used to program and to read back the output ranges of the DACs. IOUT2A (Pin 2): DAC A Current Output Complement. Tie IOUT2A to ground. GND (Pin 3): Shield Ground, provides necessary shielding for IOUT2A. Tie to ground. D3-D11 (Pins 4-12): LTC2755-12 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D11 is the MSB. D5-D13 (Pins 4-12): LTC2755-14 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D13 is the MSB. D7-D15 (Pins 4-12): LTC2755-16 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D15 is the MSB. GND (Pin 13): Shield Ground, provides necessary shielding for IOUT2D. Tie to ground. IOUT2D (Pin 14): DAC D Current Output Complement. Tie IOUT2D to ground. VDD (Pin 15): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V. Requires a 0.1μF bypass capacitor to GND. A2 (Pin 16): DAC Address Bit 2. See Table 3. A1 (Pin 17): DAC Address Bit 1. See Table 3. A0 (Pin 18): DAC Address Bit 0. See Table 3. GND (Pin 19): Ground. Tie to ground. CLR (Pin 20): Asynchronous Clear. When CLR is taken to a logic low, the data registers are reset to the zero-volt code (VOUT = 0V) for the present output range. REFD (Pin 21): Reference Input for DAC D. The impedance looking into this pin is 10k to ground. For normal operation tie this pin to the negative reference voltage at the output of reference inverting amplifier A2 (see Typical Applications). Typically –5V; accepts up to ±15V. ROFSD (Pin 22): Bipolar Offset Network for DAC D. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RIN2 (Pin 32). The impedance looking into this pin is 20k to ground. RFBD (Pin 23): DAC D Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC D (see Typical Applications). The DAC output current from IOUT1D flows through the feedback resistor to the RFBD pin. The impedance looking into this pin is 10k to ground. IOUT1D (Pin 24): DAC D Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC D (see Typical Applications). 2755f 9 LTC2755 PIN FUNCTIONS RVOSD (Pin 25): DAC D Offset Adjust. Nominal input range is ±5V. The impedance looking into this pin is 1M to ground. If not used, tie RVOSD to ground. RVOSC (Pin 26): DAC C Offset Adjust. Nominal input range is ±5V. The impedance looking into this pin is 1M to ground. If not used, tie RVOSC to ground. IOUT1C (Pin 27): DAC C Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC C (see Typical Applications). RFBC (Pin 28): DAC C Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC C (see Typical Applications). The DAC output current from IOUT1C flows through the feedback resistor to the RFBC pin. The impedance looking into this pin is 10k to ground. ROFSC (Pin 29): Bipolar Offset Network for DAC C. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RIN2 (Pin 32). The impedance looking into this pin is 20k to ground. output range. When configured for single-span operation, the output range is set via hardware pin strapping. The span I/O port’s input, and DAC, registers are transparent and do not respond to write or update commands. To configure the part for single-span use, tie MSPAN directly to VDD. If MSPAN is instead connected to GND (SoftSpan configuration), the output ranges are set and verified by using write, update and read operations. See Manual Span Configuration in the Operation section. MSPAN must be connected either directly to GND (SoftSpan configuration) or VDD, Pin 15 (single-span configuration). IOUT2C (Pin 34): DAC C Current Output Complement. Tie IOUT2C to ground. GND (Pin 35): Shield Ground, provides necessary shielding for IOUT2C. Tie to ground. D0-D2 (Pins 36-38): LTC2755-12 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. D0-D4 (Pins 36-40): LTC2755-14 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. REFC (Pin 30): Reference Input for DAC C, and connection for internal reference inverting resistor R4. The 20k resistor R4 is connected internally from RCOM2 to REFC. For normal operation tie this pin to the output of reference inverting amplifier A2 (see Typical Applications). Typically –5V; accepts up to ±15V. The impedance looking into this pin is 10k to ground (RIN2 and RCOM2 floating). D0-D6 (Pins 36-42): LTC2755-16 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. RCOM2 (Pin 31): Center Tap Point for the Reference Amplifier A2 Inverting Resistors. The 20k reference inverting resistors R3 and R4 are connected internally from RIN2 to RCOM2 and from RCOM2 to REFC, respectively (see Block Diagram). For normal operation tie RCOM2 to the negative input of external reference inverting amplifier A2 (see Typical Applications). GND (Pin 45): Shield Ground, provides necessary shielding for IOUT2B. Tie to ground. RIN2 (Pin 32): Input Resistor R3 for Reference Inverting Amplifier A2. The 20k resistor R3 is connected internally from RIN2 to RCOM2. For normal operation tie RIN2 to the external reference voltage VREF2 (see Typical Applications). Typically 5V; accepts up to ±15V. MSPAN (Pin 33): Manual Span Control Pin. MSPAN is used to configure the LTC2755 for operation in a single, fixed NC (Pins 39-44): LTC2755-12 Only. No Internal Connection. NC (Pins 41-44): LTC2755-14 Only. No Internal Connection. NC (Pins 43-44): LTC2755-16 Only. No Internal Connection. IOUT2B (Pin 46): DAC B Current Output Complement. Tie IOUT2B to ground. S0 (Pin 47): Span I/O Bit 0. Pins S0, S1 and S2 are used to program and to read back the output ranges of the DACs. D/S (Pin 48): Data/Span Select. This pin is used to select the data I/O port or the span I/O port (D0 to D15 or S0 to S2, respectively), along with their respective dedicated registers, for write and read operations. Update operations ignore D/S, since all updates affect both data and span registers. See Table 1. For single-span operation, tie D/S to ground. 2755f 10 LTC2755 PIN FUNCTIONS READ (Pin 49): Read Pin. When READ is asserted high, the data I/O (D0-D15) or span I/O (S0-S2) port outputs the contents of the selected register (see Table 1). For singlespan operation, readback of the span I/O pins is disabled, since they must be tied directly to GND and/or VDD. UPD (Pin 50): Update and Buffer Select Pin. When UPD is asserted high with READ held low, the contents of the addressed DAC’s input registers (both data and span) are copied into their respective DAC registers. The output of the DAC is updated, reflecting the new DAC register values. When READ is held high (during a read operation), the update function is disabled and the UPD pin functions as a buffer selector—logic low to read back the input register, high to read back the DAC register. See Readback in the Operation section. WR (Pin 51): Active Low Write Pin. A Write operation copies the data present on the data or span I/O pins (D0-D15 or S0-S2, respectively) into the associated input register. When READ is high, the Write function is disabled. S1 (Pin 52): Span I/O Bit 1. Pins S0, S1 and S2 are used to program and to read back the output ranges of the DACs. REFB (Pin 53): Reference Input for DAC B. The impedance looking into this pin is 10k to ground. For normal operation tie this pin to the negative reference voltage at the output of reference inverting amplifier A1 (see Typical Applications). Typically –5V; accepts up to ±15V. ROFSB (Pin 54): Bipolar Offset Network for DAC B. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RIN1 (Pin 64). The impedance looking into this pin is 20k to ground. RFBB (Pin 55): DAC B Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC B (see Typical Applications). The DAC output current from IOUT1B flows through the feedback resistor to the RFBB pin. The impedance looking into this pin is 10k to ground. IOUT1B (Pin 56): DAC B Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC B (see Typical Applications). RVOSB (Pin 57): DAC B Offset Adjust. Nominal input range is ±5V. The impedance looking into this pin is 1M to ground. If not used, tie RVOSB to ground. RVOSA (Pin 58): DAC A Offset Adjust. Nominal input range is ±5V. The impedance looking into this pin is 1M to ground. If not used, tie RVOSA to ground. IOUT1A (Pin 59): DAC A Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC A (see Typical Applications). RFBA (Pin 60): DAC A Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC A (see Typical Applications). The DAC output current from IOUT1A flows through the feedback resistor to the RFBA pin. The impedance looking into this pin is 10k to ground. ROFSA (Pin 61): Bipolar Offset Network for DAC A. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RIN1 (Pin 64). The impedance looking into this pin is 20k to ground. REFA (Pin 62): Reference Input for DAC A, and connection for internal reference inverting resistor R2. The 20k resistor R2 is connected internally from RCOM1 to REFA. For normal operation tie this pin to the output of reference inverting amplifier A1 (see Typical Applications). Typically –5V; accepts up to ±15V. The impedance looking into this pin is 10k to ground (RIN1 and RCOM1 floating). RCOM1 (Pin 63): Center Tap Point for Reference Amplifier A1 Inverting Resistors. The 20k reference inverting resistors R1 and R2 are connected internally from RIN1 to RCOM1 and from RCOM1 to REFA, respectively (see Block Diagram). For normal operation tie RCOM1 to the negative input of external reference inverting amplifier A1 (see Typical Applications). RIN1 (Pin 64): Input Resistor R1 for Reference Inverting Amplifier A1. The 20k resistor R1 is connected internally from RIN1 to RCOM1. For normal operation tie RIN1 to the external reference voltage VREF1 (see Typical Applications). Typically 5V; accepts up to ±15V. Exposed Pad (Pin 65): Ground. The Exposed Pad must be soldered to the PCB. 2755f 11 LTC2755 BLOCK DIAGRAM 15 VDD 64 RIN1 LTC2755-16 63 RCOM1 62 REFA R1 DATA I /O 4-12, 36-42 16 SPAN I /O 1, 52, 47 3 I/O PORT R2 61 ROFSA 60 RFBA DATA INPUT REGISTER 16 SPAN INPUT REGISTER 3 DATA DAC REGISTER 16 SPAN DAC REGISTER 3 I/O PORT DAC A 16-BIT WITH SPAN SELECT 59 IOUT1A 2 IOUT2A 58 RVOSA 53 REFB 54 ROFSB 55 RFBB DATA INPUT REGISTER 16 SPAN INPUT REGISTER 3 DATA DAC REGISTER 16 SPAN DAC REGISTER 3 A2 16 DAC ADDRESS A1 17 A0 18 DAC B 16-BIT WITH SPAN SELECT 56 IOUT1B 46 IOUT2B 57 R VOSB 32 RIN2 31 RCOM2 30 REFC R3 R4 29 ROFSC 28 RFBC DATA INPUT REGISTER 16 SPAN INPUT REGISTER 3 DATA DAC REGISTER 16 SPAN DAC REGISTER 3 DAC C 16-BIT WITH SPAN SELECT 27 IOUT1C 34 IOUT2C 26 RVOSC 21 REFD 22 ROFSD 23 RFBD DATA INPUT REGISTER 16 SPAN INPUT REGISTER 3 DATA DAC REGISTER 16 SPAN DAC REGISTER 3 DAC D 16-BIT WITH SPAN SELECT 24 IOUT1D 14 IOUT2D 25 RVOSD POWER-ON RESET CONTROL LOGIC 3, 13, 19, 35, 45, 65 49 51 50 READ WR UPD 48 20 D/S CLR 33 2755 BD MSPAN GND 2755f 12 LTC2755 TIMING DIAGRAMS Write, Update and Clear Timing t3 t1 t2 WR DATA/SPAN I/O INPUT VALID t5 t4 t6 UPD t7 t8 D/S VALID t9 t10 ADDRESS A2 - A0 t11 t12 VALID VALID t25 CLR 2753 TD01 Readback Timing READ WR t14 t13 t23 t24 DATA/SPAN I/O INPUT t15 DATA/SPAN I/O OUTPUT VALID t26 VALID t17 t27 VALID ADDRESS A2-A0 t20 t19 t22 UPD t18 D/S VALID 2753 TD02 2755f 13 LTC2755 OPERATION Output Ranges The LTC2755 is a quad current-output, parallel-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility, or hardwired through pin-strapping for greatest ease of use. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. When a reference voltage of 2V is used, the ranges become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to 3V. The output ranges are linearly scaled for references other than 2V and 5V. Digital Section The LTC2755 has 4 internal registers for each DAC, a total of 16 registers (see Block Diagram). Each DAC channel has two sets of double-buffered registers—one set for the data, and one set for the span (output range) of the DAC. The double-buffered feature provides the capability to simultaneously update the span and code, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs. Each set of double-buffered registers comprises an input register and a DAC register. The input registers are holding buffers—when data is loaded into an input register via a write operation, the DAC outputs are not affected. Loading the span input register is accomplished similarly, holding the D/S pin high and pulsing the WR pin low. The span and data register structures are the same except for the number of parallel bits—the span registers have 3 bits, while the data registers have 12, 14 or 16 bits. To make both registers transparent for flowthrough mode, tie WR low and UPD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the UPD pin. The interface also allows the use of the input and DAC registers in a master-slave, or edge-triggered, configuration. This mode of operation occurs when WR and UPD are tied together and driven by a single clock signal. The data bits are loaded into the input register on the falling edge of the clock and then loaded into the DAC register on the rising edge. It is possible to control both data and span on one 16-bit wide data bus by allowing span pins S2 to S0 to share bus lines with the data LSBs (D2 to D0). No write or read operation includes both span and data, so there cannot be a conflict. The asynchronous clear pin resets all DACs to 0V in any output range. CLR resets all data registers, while leaving the span registers undisturbed. VDD The contents of a DAC register, on the other hand, directly control the DAC output voltage or output range. The contents of the DAC registers are changed by copying the contents of an input register into its associated DAC register via an update operation. LTC2755-16 DAC A – + ±10V DAC B – + ±10V DAC C – + ±10V DAC D – + ±10V MSPAN S2 S1 S0 D/S Write and Update Operations The data input register of the addressed DAC is loaded directly from a 16-bit microprocessor bus by holding the D/S pin low and pulsing the WR pin low (write operation). The DAC register is loaded by pulsing the UPD pin high (update operation), which copies the data held in the input register into the DAC register. Note that updates always include both data and span; but the DAC register values will not change unless the associated input register values have previously been changed via a write operation. VDD DATA I/O 16 WR UPD READ A2 A1 A0 2755 F01 DAC ADDRESS Figure 1. Using MSPAN to Configure the LTC2755 for Single-Span Operation (±10V Range). 2755f 14 LTC2755 OPERATION These devices also have a power-on reset that initializes all DACs to VOUT = 0V in any output range. The DACs power up in the 0V-5V range if the part is in SoftSpan configuration; for manual span (see Manual Span Configuration below), the DACs power up in the manually-chosen range at the appropriate code. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2755 for single-span operation, tie the MSPAN pin to VDD and the D/S pin to GND. The desired output range is then specified by the span I/O pins (S0, S1 and S2) as usual, but the pins are programmed by tying directly to GND or VDD (see Figure 1 and Table 2). In this configuration, all DAC channels will initialize to the chosen output range at power-up, with VOUT = 0V. When configured for manual span operation, span pin readback is disabled. Readback The contents of any one of the 16 interface registers can be read back from the I/O ports. the D/S pin. The selected I/O port’s pins become logic outputs during readback, while the unselected I/O port’s pins remain high-impedance inputs. With the DAC channel and I/O port selected, assert READ high and select the desired input or DAC register using the UPD pin. Note that UPD is a two function pin—the update function is only available when READ is low. When READ is high, the update function is disabled and the UPD pin instead selects the input or DAC register for readback. Table 1 shows the readback functions for the LTC2755. Table 1. Write, Update and Read Functions READ D/S WR UPD SPAN I/O DATA I/O 0 0 0 0 - Write to Input Register 0 0 0 1 - Write/Update (Transparent) 0 0 1 0 - - 0 0 1 1 Update DAC Register Update DAC Register 0 1 0 0 Write to Input Register - 0 1 0 1 Write/Update (Transparent) - 0 1 1 0 - - 0 1 1 1 Update DAC register Update DAC Register 1 0 X 0 - Read Input Register 1 0 X 1 - Read DAC Register 1 1 X 0 Read Input Register - 1 1 X 1 Read DAC Register - The I/O pins are grouped into two ports: data and span. The data I/O port comprises pins D0-D11, D0-D13 or D0-D15 (LTC2755-12, LTC2755-14 or LTC2755-16, respectively). The span I/O port comprises pins S0, S1 and S2 for all parts. X = Don’t Care Each DAC channel has a set of data registers that are controlled and read back from the data I/O port; and a set of span registers that are controlled and read back from the span I/O port. The register structure is shown in the Block Diagram. The most common readback task is to check the contents of an input register after writing to it, before updating the new data to the DAC register. To do this, hold UPD low and assert READ high. The contents of the selected port’s input register are output to its I/O pins. A readback operation is initiated by asserting READ to logic high after selecting the desired DAC channel and I/O port. The I/O pins, which are high-impedance digital inputs when READ is low, selectively change to low-impedance logic outputs during readback. To read back the contents of a DAC register, hold UPD low and assert READ high, then bring UPD high to select the DAC register. The contents of the selected DAC register are output by the selected port’s I/O pins. Note: if no update is desired after the readback operation, UPD must be returned low before bringing READ low; otherwise the UPD pin will revert to its primary function and update the DAC. Select the DAC channel with address pins A0, A1 and A2, and select the I/O port (data or span) to be read back with 2755f 15 LTC2755 OPERATION System Offset Adjustment Many systems require compensation for overall system offset. The RVOSX offset adjustment pins are provided for this purpose. For noise immunity and ease of adjustment, the control voltage is attenuated to the DAC output: VOS = –0.01 • V(RVOSX) [0V to 5V, ±2.5V spans] VOS = –0.02 • V(RVOSX) [0V to 10V, ±5V, –2.5V to 7.5V spans] VOS = –0.04 • V(RVOSX) [±10V span] The nominal input range of this pin is ±5V; other reference voltages of up to ±15V may be used if needed. The RVOSX pins have an input impedance of 1MΩ. To preserve the settling performance of the LTC2755, drive this pin with a Thevenin-equivalent impedance of 10k or less. Short any unused RVOSX system offset adjustment pins to GND. Table 2. Span Codes S2 S1 S0 SPAN 0 0 0 Unipolar 0V to 5V 0 0 1 Unipolar 0V to 10V 0 1 0 Bipolar –5V to 5V 0 1 1 Bipolar –10V to 10V 1 0 0 Bipolar –2.5V to 2.5V 1 0 1 Bipolar –2.5V to 7.5V Codes not shown are reserved and should not be used. Table 3. Address Codes A2 A1 A0 DAC CHANNEL 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 1 1 ALL DACs* Codes not shown are reserved and should not be used. *If readback is taken using the ALL DACs address, the LTC2755 defaults to DAC A. 2755f 16 LTC2755 OPERATION—EXAMPLES 1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at 0V, will stay there. The 16-Bit DAC code is shown in hex for compactness. WR SPAN I/O INPUT 010 DATA I/O INPUT 8000H UPD UPDATE (±5V RANGE, VOUT = 0V) D/S READ = LOW VOUTX 0V (0000H IN 0V TO 5V RANGE) 0V (8000H IN ±5V RANGE) 2755 TD03 2. Load ±10V range with the output at 5V, changing to –5V. WR SPAN I/O INPUT 011 DATA I/O INPUT C000H 4000H UPD UPDATE (–5V) UPDATE (5V) D/S READ = LOW +5V VOUTX OV –5V 2755 TD04 3. Write and update midscale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input and DAC registers before updating. WR DATA I/O INPUT 8000H DATA I/O HI-Z OUTPUT HI-Z 8000H INPUT REGISTER UPD 0000H DAC REGISTER UPDATE (2.5V) D/S READ +2.5V VOUTX OV 2755 TD05 2755f 17 LTC2755 APPLICATIONS INFORMATION Op Amp Selection programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 4 and 5 can also be used to determine the effects of op amp parameters on the LTC2755-14 and the LTC2755-12. However, the results obtained from Tables 4 and 5 are in 16-bit LSBs. Divide these results by 4 (LTC2755-14) and 16 (LTC2755-12) to obtain the correct LSB sizing. Because of the extremely high accuracy of the 16-bit LTC2755-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the LTC2755’s accuracy when Table 6 contains a partial list of LTC precision op amps recommended for use with the LTC2755. The easy-to-use design equations simplify the selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 6 and insert the specified op amp parameters in Table 5. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Table 4. Variables for Each Output Range that Adjust the Equations in Table 5 OUTPUT RANGE A1 A2 A3 A4 A5 5V 1.1 2 1 1 10V 2.2 3 0.5 1.5 ±5V 2 2 1 1 1.5 ±10V 4 4 0.83 1 2.5 ±2.5V 1 1 1.4 1 1 –2.5V to 7.5V 1.9 3 0.7 0.5 1.5 Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp. OP AMP DNL (LSB) INL (LSB) UNIPOLAR OFFSET (LSB) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) VOS2 (mV) 0 0 0 IB2 (mV) 0 0 0 AVOL2 (V/V) 0 0 0 5V 5V 5V VOS1 • 0.82 • V A3 • VOS1 • 13.2 • V VOS1 • 3.2 • V REF REF REF 5V 5V 5V IB1 (nA) IB1 • 0.0003 • V IB1 • 0.00008 • V IB1 • 0.13 • V REF REF REF 16.5k 1.5k AVOL1 (V/V) A1 • A A2 • A 0 VOL1 VOL1 VOS1 (mV) BIPOLAR ZERO ERROR (LSB) ( ) ( ) 5V A3 • VOS1 • 19.8 • V REF 5V IB1 • 0.13 • V REF 0 ( (V5V ) ) 5V A4 • (I • 0.13 • ( V )) A4 • ( 66k ) A A4 • VOS2 • 13.1 • B2 REF REF VOL2 UNIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.26 • VREF 131k AVOL2 ( ) ( ) ( ) ( ) ( ) ( ) BIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.26 • VREF 131k AVOL2 ( ) ( ) ( ) ( ) ( ) ( ) Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2755 with Relevant Specifications AMPLIFIER SPECIFICATIONS IB nA A VOL V/mV VOLTAGE NOISE ⎯ ⎯z nV/√H CURRENT NOISE ⎯ ⎯z pA/√H SLEW RATE V/μs GAIN BANDWIDTH PRODUCT MHz tSETTLING with LTC2755 μs POWER DISSIPATION mW AMPLIFIER VOS μV LT1001 25 2 800 10 0.12 0.25 0.8 120 46 LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp LT1468 75 10 5000 5 0.6 22 90 2 117 LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp 2755f 18 LTC2755 APPLICATIONS INFORMATION Op amp offset will contribute mostly to output offset and gain error, and has minimal effect on INL and DNL. For example, for the LTC2755-16 with a 5V reference in 5V unipolar mode, a 250μV op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error; but only 0.8LSB of INL degradation and 0.2LSB of DNL degradation. While not directly addressed by the simple equations in Tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers into the VOS and IB equations from Table 5 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time, offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2755 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2755 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s apparent INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Table 7. Partial List of LTC Precision References Recommended for Use with the LTC2755 with Relevant Specifications INITIAL TOLERANCE TEMPERATURE DRIFT 0.1Hz to 10Hz NOISE LT1019A-5, LT1019A-10 ±0.05% 5ppm/°C 12μVP-P LT1236A-5, LT1236A-10 ±0.05% 5ppm/°C 3μVP-P LT1460A-5, LT1460A-10 ±0.075% 10ppm/°C 20μVP-P LT1790A-2.5 ±0.05% 10ppm/°C 12μVP-P REFERENCE 2755f 19 LTC2755 APPLICATIONS INFORMATION Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. IOUT2X must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than 1Ω, a force/sense amplifier configuration should be used to drive this pin (see Figure 2). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC2755-16. Layout Figures 3, 4, 5, and 6 show the layout for the LTC2755 evaluation board, DC1112. This shows how to route the digital signals around the device without interfering with the reference and output op amps. Complete demo board documentation is available in the DC1112 quick start guide. ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE 2,14, 34, 46 + 2 3 200Ω 200Ω 1000pF LT1468 6 IOUT2 3 LT1001 1 3 2 + ZETEX BAT54S – 6 1 2 – IOUT2 ZETEX* BAT54S 2 3 *SCHOTTKY BARRIER DIODE VREF 5V LTC2755-16 60 RFBA ROFSA 61 RIN1 64 + 1 15pF 3 1/2 LT1469 2 – 150pF RCOM1 63 59 IOUT1A 2 – 2 IOUT2A 3 + DAC A 1/2 LT1469 1 VOUTA 58 RVOSA REFA 62 DAC B – + DAC C – + DAC D – + 2755 F02 Figure 2. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier. 2755f 20 LTC2755 APPLICATIONS INFORMATION 2755 F03 Figure 3. LTC2755 Evaluation Board DC1112. Layer 1, Top Layer. 2755 F04 Figure 4. LTC2755 Evaluation Board DC1112. Layer 2, GND Plane. 2755f 21 LTC2755 TYPICAL APPLICATIONS 2755 F05 Figure 5. LTC2755 Evaluation Board DC1112. Layer 3, Power Traces. 2755 F06 Figure 6. LTC2755 Evaluation Board DC1112. Layer 4, Bottom Layer. 2755f 22 LTC2755 PACKAGE DESCRIPTION UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705 Rev C) 0.70 ±0.05 7.15 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) 7.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.15 ± 0.10 7.50 REF (4-SIDES) 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2755f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2755 TYPICAL APPLICATION Digitally Controlled Offset Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply V+ 2 IN C20 10μF VREF U6 OUT 6 LT1236S TRIM 5 GND AMPLIFIER A1 C13 10μF 4 2 3 V+ 9 10 U4 LT1991 15 64 VDD RIN1 450k 50k 1 + V– C22 .001μF 53 54 55 62 61 60 REFB ROFSB RFBB REFA ROFSA RFBA 63 RCOM1 IOUT1A M9 6 – 2 5 +LT1469 56 2 – 46 3 +LT1469 IC1B 4pF – 450k M1 + 450k 1 P1 150k 2 450k P3 50k 3 REF 5 P9 DATA I/O 4pF VEE 4 V– 5V 16 VCC 6 VREF U2 LTC2600 SPI INTERFACE 7 8 9 10 11 C1 30pF 59 150k M3 OUT 6 VREF V+ IC1A LT1469 4 7 VCC 8 8 – CS/LD SCK SDI SDO CLR GND 1 DACA DACB DACC DACD DACE DACF DACG DACH 2 3 4 5 12 13 14 15 • • • 4 5 6 7 8 9 10 11 12 36 37 38 39 40 41 42 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPAN I/O 1 S2 52 S1 47 S0 DAC ADDRESS 16 A2 17 A1 18 A0 IOUT2A VOUTA RVOSA 58 IOUT1B V+ 8 C2 30pF IC2A IOUT2B RVOSB 57 U1 IOUT1C 1 C1 30pF 27 6 – 34 5 +LT1469 IC2B IOUT2C 7 8 V+ 24 2 – 14 3 +LT1469 IC3A IOUT2D RVOSD 25 49 TO ADDITIONAL OFFSET ADJUST CIRCUITS 50 51 20 VOUTC C1 30pF RVOSC 26 IOUT1D VOUTB V– 4 LTC2755-16 D/S READ UPD WR CLR MSPAN 48 7 4 1 VOUTD V– GND RIN2 RCOM2 REFC ROFSC RFBC REFD ROFSD RFBD 33 19 32 31 30 29 28 21 22 23 CONTROL AMPLIFIER A2 2755 TA03 C21 001 6 – 5 +LT1469 IC3B 7 REF2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1027 Precision Reference 1ppm/°C Maximum Drift LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise LT1468 16-Bit Accurate Op-Amp 90MHz GBW, 22V/μs Slew Rate LT1469 Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/μs Slew Rate LTC1588/LTC1589/ LTC1592 Serial 12-/14-/16-Bit IOUT Single DAC Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package LTC1591/LTC1597 Parallel 14-/16-Bit IOUT Single DAC Integrated 4-Quadrant Resistors LTC2704 Serial 12-/14-/16-Bit VOUT Quad DACs Software-Selectable (SoftSpan) Ranges, Integrated Amplifiers, ±1LSB INL LTC2751 Parallel 12-/14-/16-Bit IOUT SoftSpan Single DAC ±1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 5mm × 7mm QFN-38 Package LTC2753 Parallel 12-/14-16-Bit IOUT SoftSpan Dual DACs ±1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 7mm × 7mm QFN-48 Package 2755f 24 Linear Technology Corporation LT 0308 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008