PD – 95290 IRF7807PbF IRF7807APbF HEXFET® Chip-Set for DC-DC Converters • • • • • N Channel Application Specific MOSFETs Ideal for Mobile DC-DC Converters Low Conduction Losses Low Switching Losses Lead-Free Description These new devices employ advanced HEXFET Power MOSFET technology to achieve an unprecedented balance of on-resistance and gate charge. The reduced conduction and switching losses make them ideal for high efficiency DC-DC Converters that power the latest generation of mobile microprocessors. A pair of IRF7807 devices provides the best cost/ performance solution for system voltages, such as 3.3V and 5V. A D 1 8 S 2 7 D S 3 6 D G 4 5 D S SO-8 T o p V ie w Device Features IRF7807 IRF7807A Vds 30V 30V Rds(on) 25mΩ 25mΩ Qg 17nC 17nC Qsw 5.2nC Qoss 16.8nC 16.8nC Absolute Maximum Ratings Parameter Symbol Drain-Source Voltage Gate-Source Voltage 25°C Current (VGS ≥ 4.5V) 70°C Pulsed Drain Current ID IDM 25°C ±12 8.3 6.6 6.6 66 66 2.5 PD W TJ, TSTG –55 to 150 °C IS 2.5 2.5 Pulsed source Current ISM 66 66 www.irf.com A 1.6 Continuous Source Current (Body Diode) Thermal Resistance Parameter Maximum Junction-to-Ambient Units V 8.3 70°C Junction & Storage Temperature Range IRF7807A 30 VGS Continuous Drain or Source Power Dissipation IRF7807 VDS RθJA Max. 50 A Units °C/W 1 09/22/04 IRF7807/APbF Electrical Characteristics Parameter IRF7807 Min Typ Max IRF7807A Min Typ Max Units Drain-to-Source Breakdown Voltage* V(BR)DSS Static Drain-Source on Resistance* RDS(on) Gate Threshold Voltage* VGS(th) Drain-Source Leakage Current* IDSS Gate-Source Leakage Current* IGSS Total Gate Charge* Qg 12 Pre-Vth Gate-Source Charge Q gs1 2.1 2.1 Post-Vth Gate-Source Charge Q gs2 0.76 0.76 Gate to Drain Charge Qgd 2.9 2.9 Switch Charge* (Qgs2 + Qgd) QSW 3.66 5.2 3.66 Output Charge* Q oss 14 16.8 14 30 – – 17 25 1.0 30 – – V VGS = 0V, ID = 250µA 17 25 mΩ VGS = 4.5V, ID = 7A V VDS = VGS, ID = 250µA µA VDS = 24V, VGS = 0 1.0 30 30 150 150 ±100 ±100 17 Conditions 12 VDS = 24V, VGS = 0, Tj = 100°C nA 17 VGS = ±12V VGS = 5V, ID = 7A VDS = 16V, ID = 7A nC 16.8 VDS = 16V, VGS = 0 Ω Gate Resistance Rg 1.2 1.2 Turn-on Delay Time td(on) 12 12 Rise Time tr 17 17 Turn-off Delay Time td (off) 25 25 Rg = 2Ω Fall Time tf 6 6 VGS = 4.5V Resistive Load VDD = 16V ns ID = 7A Source-Drain Rating & Characteristics Parameter Min Typ Max Min Typ Max Units Diode Forward Voltage* VSD Reverse Recovery Charge Qrr 80 80 Reverse Recovery Charge (with Parallel Schotkky) Notes: Qrr(s) 50 50 * 2 1.2 1.2 Conditions V IS = 7A, VGS = 0V nC di/dt = 700A/µs VDS = 16V, VGS = 0V, IS = 7A di/dt = 700A/µs (with 10BQ040) VDS = 16V, VGS = 0V, IS = 7A Repetitive rating; pulse width limited by max. junction temperature. Pulse width ≤ 300 µs; duty cycle ≤ 2%. When mounted on 1 inch square copper board, t < 10 sec. Typ = measured - Q oss Devices are 100% tested to these parameters. www.irf.com IRF7807/APbF Power MOSFET Selection for DC/DC Converters 4 Drain Current Control FET This can be expanded and approximated by; VGTH t0 2 Drain Voltage Figure 1: Typical MOSFET switching waveform Ploss = (Irms 2 × Rds(on ) ) Synchronous FET Qgs2 ⎞ ⎛ f⎟ + ⎜ I × × Vin × ig ⎠ ⎝ ⎞ f⎟ ⎠ + (Qg × Vg × f ) ⎛Q + oss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 1. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached (t1) and the time the drain current rises to Idmax (t2) at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure 2 shows how Qoss is formed by the parallel combination of the voltage dependant (non-linear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. www.irf.com t3 t1 QGD Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛ Qgd +⎜I × × Vin × ig ⎝ Gate Voltage t2 QGS1 Power losses in the control switch Q1 are given by; 1 QGS2 Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) + (Qg × Vg × f ) ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ *dissipated primarily in Q1. 3 IRF7807/APbF For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Spice model for IRF7807 can be downloaded in machine readable format at www.irf.com. Figure 2: Qoss Characteristic Typical Mobile PC Application The performance of these new devices has been tested in circuit and correlates well with performance predictions generated by the system models. An advantage of this new technology platform is that the MOSFETs it produces are suitable for both control FET and synchronous FET applications. This has been demonstrated with the 3.3V and 5V converters. (Fig 3 and Fig 4). In these applications the same MOSFET IRF7807 was used for both the control FET (Q1) and the synchronous FET (Q2). This provides a highly effective cost/performance solution. 3.3V Supply : Q1=Q2=IRF7807 5V Supply : Q1=Q2=IRF7807 93 95 92 94 90 Efficiency (%) Efficiency (%) 91 89 88 87 Vin = 10V 86 91 90 Vin = 14V Vin = 24V Vin=24V 84 89 1 1.5 2 2.5 3 3.5 Load Current (A) Figure 3 4 92 Vin = 10V Vin = 14V 85 93 4 4.5 5 1 1.5 2 2.5 3 3.5 Load Current (A) 4 4.5 5 Figure 4 www.irf.com IRF7807/APbF Typical Characteristics IRF7807 IRF7807A Figure 5. Normalized On-Resistance vs. Temperature Figure 6. Normalized On-Resistance vs. Temperature Figure 7. Typical Gate Charge vs. Gate-to-Source Voltage Figure 8. Typical Gate Charge vs. Gate-to-Source Voltage Figure 9. Typical Rds(on) vs. Gate-to-Source Voltage Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage www.irf.com 5 IRF7807/APbF IRF7807 IRF7807A 10 ISD , Reverse Drain Current (A) ISD , Reverse Drain Current (A) 10 TJ = 150 ° C 1 TJ = 25 ° C V GS = 0 V 0.1 0.4 0.5 0.6 0.7 0.8 TJ = 150 ° C 1 TJ = 25 ° C V GS = 0 V 0.1 0.4 0.9 0.5 0.6 0.7 0.8 0.9 VSD ,Source-to-Drain Voltage (V) VSD ,Source-to-Drain Voltage (V) Figure 11. Typical Source-Drain Diode Forward Voltage Figure 12. Typical Source-Drain Diode Forward Voltage Thermal Response (Z thJA ) 100 D = 0.50 10 0.20 0.10 0.05 1 0.02 0.01 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 0.1 0.001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.01 0.1 1 10 100 1000 t1 , Rectangular Pulse Duration (sec) Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 6 www.irf.com IRF7807/APbF SO-8 Package Outline Dimensions are shown in millimeters (inches) D 5 A 8 7 6 6X 2 3 MIN .0532 .0688 1.35 1.75 A1 .0040 0.25 .0098 0.10 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BASIC 1.27 BASIC e1 .025 BASIC 0.635 BASIC A 4 e e1 H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° K x 45° A C y 0.10 [.004] 8X b 0.25 [.010] MAX .013 H 0.25 [.010] 1 MAX b 5 6 MILLIMETERS MIN A E INCHE S DIM B A1 8X L 8X c 7 C A B F OOTPRINT NOT ES : 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. 8X 0.72 [.028] 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 6.46 [.255] 7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBST RAT E. 3X 1.27 [.050] 8X 1.78 [.070] SO-8 Part Marking EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) INT ERNAT IONAL RECT IFIER LOGO XXXX F7101 DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = AS S EMBLY S IT E CODE LOT CODE PART NUMBER www.irf.com 7 IRF7807/APbF SO-8 Tape and Reel Dimensions are shown in millimeters (inches) TERMINAL NUMBER 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. 14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/04 8 www.irf.com