FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input
Integrated Synchronous Buck Regulator
Features
Single-Supply Operation with 4 A Output Current
Wide Input Range with Dual Supply: 3.0 V to 24 V
Wide Output Voltage Range: 0.8 V to 80% VIN
Over 94% Peak Efficiency
1% Reference Accuracy Over Temperature
Fully Synchronous Operation with Integrated
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
Single Supply Device for VIN > 6.5 V – 24 V
Synchronizable to External Clock with
Master/Slave Provisions
Power-Good Signal
5x6mm, 25-Pin, 3-Pad MLP Package
Programmable Frequency Operation (200600 KHz)
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Starts on Pre-Bias Outputs
Integrated Bootstrap Diode
Programmable Over-Current Protection
Under-Voltage, Over-Voltage, and ThermalShutdown Protections
Applications
Servers & Telecom
Graphics Cards & Displays
Computing Systems
Set-Top Boxes & Game Consoles
Point-of-Load Regulation
Description
The FAN21SV04 TinyBuck™ is a highly efficient,
small-footprint,
programmable-frequency,
4 A,
integrated synchronous buck regulator.
FAN21SV04 contains both synchronous MOSFETs
and a controller/driver with optimized interconnects in
one package, which enables designers to solve highcurrent requirements in a small area with minimal
external components, thereby reducing cost. Onboard internal 5 V regulator enables single-supply
operation for input voltages >6.5 V.
The FAN21SV04 can be configured to drive multiple
slave devices OR synchronize to an external system
clock. In slave mode, FAN21SV04 may be set up to be
free-running in the absence of a master clock signal.
External compensation, programmable switching
frequency, and current-limit features allow for design
optimization and flexibility. High-frequency operation
allows for all-ceramic solutions.
Fairchild’s advanced BiCMOS power process,
combined with low-RDS(ON) internal MOSFETs and a
thermally efficient MLP package, provide the ability
to dissipate high power in a small package.
Integration helps minimize critical inductances,
making layout simpler and more efficient compared
to discrete solutions.
Output over-voltage, under-voltage, over-current, and
thermal-shutdown protections help protect the device
from damage during fault conditions. FAN21SV04
prevents pre-biased output discharge during startup in
point-of-load applications.
Related Resources
TinyCalc™ Calculator Design Tool
AN-8022 — TinyCalc™ Calculator User Guide
Ordering Information
Operating
Temperature Range
Package
Packing
Method
FAN21SV04MPX
-10°C to 85°C
Molded Leadless Package (MLP) 5x6 mm
Tape and Reel
FAN21SV04EMPX
-40°C to 85°C
Molded Leadless Package (MLP) 5x6 mm
Tape and Reel
Part Number
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
November 2012
IN
VIN
CHF
CIN
Boot
Diode
5V_Reg
BOOT
C4
Reg
Q1
R5
CBOOT
VIN_Reg
PWM
+
DRIVER
RRAMP
Enable
L
Q2
RAMP
Power
Good
OUT
SW
C5
COUT
PGND
POWER
MOSFETS
EN
RILIM
CLK
ILIM
RT
R1
FB
RT
R3
AGND
COMP
C3
C1
RBIAS
C2
R2
Figure 1. Typical Application as Master at VIN=6.5 V to 24 V
Block Diagram
VIN_Reg
Reg
5V
BOOT
5V_Reg
IILIM
Boot
Diode
Current Limit
Comparator
VIN
ILIM
Int ref
COMP
Error
Amplifier
FB
CBOOT
R
PWM
Comparator
Q
S
Gate
Drive
Circuit
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Typical Application Diagram
VOUT
SW
L
SS
VREF
COUT
CLK
OSC
EN
RAMP
GEN
Summing
Amplifier
Current
Sense
AGND
PGND
RAMP
Figure 2. Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
2
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
Name
Description
P1, 6-12
SW
Switching Node. Junction of high-side and low-side MOSFETs.
P2, 3-5
VIN
Power Conversion Input Voltage. Connect to the main input power source.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V_Reg when
SW is LOW.
2
VIN_Reg
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5 V with 10 Ω resistor and a 1 µF bypass capacitor at the pin (see Figure 10).
13
PGOOD
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled
(see Figure 31).
14
EN
15
5V_Reg
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R
capacitor.
16
AGND
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the internal default setting.
18
RT
Switching Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the
switching frequency and configures the CLK pin as an output (master). Tying this pin to
5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running switching frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
24
CLK
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
25
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Pin Configuration
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
Max.
Units
28
V
6
V
35
V
-0.5
6.0
V
-0.5
24.0
-5
30
-0.3
6.0
VIN, VIN_Reg to AGND AGND=PGND
5V_Reg to AGND
AGND=PGND
BOOT to PGND
BOOT to SW
SW to PGND
Continuous
Transient (t < 20 ns, f < 600 KHz)
All other pins
ESD
Human Body Model,
JESD22-A114
Charged Device Model,
JESD22-C101
Electrostatic Discharge
Protection Level
V
V
1.5
kV
2.5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
fSW
VIN,
VIN_Reg
Parameter
Conditions
Switching Frequency
Supply Voltage for Power and Bias
TA
Ambient Temperature
TJ
Junction Temperature
Min.
Typ.
200
500
Max
Units
600
KHz
VIN to PGND
3.0
24.0
VIN_Reg to AGND
6.5
24.0
FAN21SV04MPX
-10
+85
FAN21SV04EMPX
-40
+85
V
°C
+125
°C
Max.
Units
+150
°C
+300
°C
Thermal Information
Symbol
TSTG
TL
θJC
Parameter
Min.
Storage Temperature
Typ.
-65
Lead Soldering Temperature, 30 Seconds
Thermal Resistance: Junction-to-Case
P1 (Q2)
4
P2 (Q1)
7
P3
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
°C/W
4
(1)
θJ-PCB
Thermal Resistance: Junction-to-Mounting Surface
PD
Total Power Dissipation in the package, TA=25°C(1)
35
°C/W
2.8
W
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 38. Actual results
are dependent upon mounting method and surface related to the design.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
4
Recommended operating conditions and using the circuit shown in Figure 1, with VIN, VIN_Reg=12 V, unless
otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
30
mA
Power Supplies
Operating Current
(VIN+VIN_Reg)
VIN=12 V, 5V_Reg Open, CLK Open,
fSW =500 KHz, No Load
22
VIN_Reg Operating Current
EN=High, 5 V_Reg Open, CLK Open,
fSW =500 KHz
11
VIN_Reg Quiescent Current
EN=High, FB=0.9 V
4
VIN_Reg Standby Current
EN=0, VIN=12 V
5V_Reg Output Voltage
Internal VCC Regulator, No Load,
6.5 V<VIN_Reg<24 V
5V_Reg Max. Current Load
VIN_Reg=12 V
VIN_Reg UVLO Threshold
Rising VIN, VIN=VIN_Reg
Falling VIN, VIN=VIN_Reg
Reference
Reference Voltage measured
at FB (See Figure 4 for
Temperature Coefficient)
Oscillator
Frequency
Frequency in Slave Mode
Compared to Master Mode
Minimum On Time
Duty Cycle
4.7
Gain Bandwidth Product
Output Voltage Swing (VCOMP)
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
5.3
V
5
mA
5.6
6.3
5
V
V
806
FAN21SV04EMPX, TA=25°C
795
800
805
RT=50 kΩ to GND (Master Mode)
255
300
345
RT=24 kΩ to GND (Master Mode)
540
600
660
RT=24 kΩ to 50 kΩ to 5 V_Reg
(Slave Mode)
-15
40
80
Master (RT to GND)
Master, VCLK=0.4 V
Master, VCLK=2 V
Slave: VCLK > 2 V
Slave: VCLK=1 V
Slave
70
0.25
-2.5
50
-230
1.73
5V_Reg=5 V, VCOMP=2.2 V
5V_Reg=5 V, VCOMP=1.2 V
VFB=0.8 V, TA=25°C
KHz
%
65
85
ns
%
V
100
150
ns
85
100
0.35
-2.0
-200
1.83
-170
1.93
ns
mA
mA
ns
µA
V
2.5
ms
3.1
ms
80
85
dB
12
15
Frequency=500 KHz
VIN_Reg > 6.5 V
mV
+15
0.5
(2)
(2)
5.0
800
VIN=6.5 V, fSW =600 KHz
Fault Enable/SSOK (T1.0)
Error Amplifier
DC Gain (2)
mA
mA
794
VIN=16 V, 1.8 VOUT, RT=30 kΩ,
RRAMP=200 kΩ
Minimum Off Time
Synchronization
CLK Output Pulse Width
CLK Output Sink Current
CLK Output Source Current
CLK Input Pulse Width
CLK Input Source Current
CLK Input Threshold, Rising
Soft-Start
VOUT to Regulation (T0.8)
5
1
FAN21SV04MPX, TA=25°C
(2)
Ramp Amplitude,
Peak–to-Peak(2)
mA
0.4
1.5
0.8
-850
2.2
1.2
-650
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Electrical Characteristics
MHz
4.0
2.5
1.5
-450
V
mA
mA
nA
Note:
2. Specifications guaranteed by design and characterization; not production tested.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
5
Recommended operating conditions using the circuit shown in Figure 1 with VIN, VIN_Reg=12 V, unless otherwise
noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
EN Threshold, Rising
1.35
2.00
EN Hysteresis
250
mV
800
KΩ
1
µA
Control Functions
EN Pull-Up Resistance
VIN_Reg >6.5 V
EN Discharge Current
Auto-Restart Mode, VIN_Reg>6.5 V
FB OK Drive Resistance
PGOOD Low Threshold
800
1000
(3)
-14.0
-11.0
-8.0
FB > VREF, 2 Consecutive Clock Cycles(3)
+7.0
+10.0
+13.5
FB < VREF, 2 Consecutive Clock Cycles
PGOOD Low Voltage
IOUT < 2 mA
PGOOD Leakage Current
VPGOOD=5 V
V
KΩ
%VREF
0.4
V
0.2
1.0
µA
Protection and Shutdown
Current Limit
RILIM open, fSW =500 KHz, VOUT=1.8 V,
RRAMP=200 kΩ, 16 Consecutive Clock
Cycles(3)
5.5
6.5
7.5
A
ILIM Current
VIN_Reg > 6.5 V, TA=25°C
-11
-10
-9
µA
Over-Temperature Shutdown
Over-Temperature Hysteresis
+155
Internal Temperature
°C
+30
°C
Over-Voltage Threshold
2 Consecutive Clock Cycles(3)
110
115
120
%VOUT
Under-Voltage Shutdown
16 Consecutive Clock Cycles(3)
68
73
78
%VOUT
Fault-Discharge Threshold
Measured at FB pin
250
mV
Fault-Discharge Hysteresis
Measured at FB pin (VFB ~500 mV)
250
mV
Note:
3. Delay times are not tested in production. Guaranteed by design.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Electrical Characteristics (Continued)
www.fairchildsemi.com
6
1.010
1.20
1.005
1.10
I FB
V FB
VIN=12V, VCC=5V, TA=25°C, unless otherwise specified.
1.000
0.995
1.00
0.90
0.990
0.80
-50
0
50
100
150
-50
0
Temperature (oC)
50
100
150
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature, Figure 5. Reference Bias Current (IFB) vs. Temperature,
Normalized
Normalized
1.02
1200
1.01
Frequency
Frequency (KHz)
1500
900
600
600KHz
1.00
300KHz
0.99
300
0.98
0
0
20
40
60
80
100
120
-50
140
0
RT (KΩ)
100
150
o
Temperature ( C)
Figure 6. Frequency vs. RT (Master)
Figure 7.
Frequency vs. Temperature, Normalized
1.04
1.60
1.40
1.02
1.20
I ILIM
RDS
50
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Typical Characteristics
1.00
1.00
Q1 ~0.32 %/oC
0.80
0.98
Q2 ~0.35 %/oC
0.96
0.60
-50
0
50
100
150
-50
50
100
150
Temperature ( C)
Temperature ( C)
Figure 8. RDS vs. Temperature, Normalized
(5 V_Reg=VGS=5 V)
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
0
o
o
Figure 9.
ILIM Current (IILIM) vs. Temperature,
Normalized
www.fairchildsemi.com
7
FAN21SV04
Figure 10. Single-Supply Application Circuit: 1.8 VOUT, 500 KHz, Master, 8 V – 20 V Input
FAN21SV04
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Application Circuit
Figure 11. Single -Supply Application Circuit: 1.2 VOUT, 500 KHz, Master 8 V – 20 V Input
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
8
Typical operating characteristics using the Figure 10 circuit; VIN=12 V, VCC=5 V, TA=25°C, unless otherwise specified.
95
3.3V Eff 8-20V 500kHz
95
1.8V_Eff 8-20V_500kHz
90
Efficiency(%)
Efficiency(%)
90
85
80
8V
85
8Vin
12Vin
80
16Vin
12V
75
20Vin
75
16V
20V
70
70
0
0.5
Figure 12.
1
1.5
2
Load(A)
2.5
3
3.5
0
4
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Figure 13. 3.3 VOUT Efficiency, 500 KHz(4)
1.8 VOUT Efficiency Over VIN vs. Load
95
1.8V_Eff 8-20V_300kHz
3.3V_Eff 8-20V_300kHz
95
90
85
Efficiency(%)
Efficiency(%)
90
8V
80
12V
85
8V
80
12V
16V
75
16V
75
20V
20V
70
70
0
0.5
1
1.5
2
Load(A)
2.5
3
3.5
0
4
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Figure 14. 1.8 VOUT Efficiency, 300 KHz(4)
Figure 15. 3.3 VOUT Efficiency, 300 KHz(4)
95
1.2V_Eff 8-20V_500kHz
95
90
5V_Eff 8-20V_300kHz
Efficiency(%)
Efficiency (%)
90
85
80
85
8Vin
80
12Vin
8V
75
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Typical Performance Characteristics
16Vin
12V
75
20Vin
16V
20V
70
70
0
0.5
1
1.5
2
Load (A)
2.5
3
3.5
4
0
0.5
1
1.5
2
Load(A)
2.5
3
3.5
4
Figure 17. 5 VOUT Efficiency, 300 KHz(4)
Figure 16. 1.2 VOUT Efficiency, 500 KHz (Figure 11)
Note:
4. Circuit values for this configuration change in Figure 10.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
9
Typical operating characteristics using the Figure 10 circuit; VIN=12 V, VCC=5 V, TA=25°C, unless otherwise specified.
0.10
0.15
Line Regulation
Load Regulation
0.08
0.05
0.1
% Change in output voltage as
compared at 0 Amps
% Change in output voltage as
compared to set value at 6.5V
No load
0.5A Load
0.03
0.00
-0.03
-0.05
12V
0.05
16V
0
-0.05
-0.1
-0.08
-0.15
-0.10
0
5
Figure 18.
10
15
Input Voltage (V)
20
0
25
1
1.5
2
2.5
3
3.5
4
Load(A)
1.8 VOUT Line Regulation
Figure 19. 1.8 VOUT Load Regulation
70
70
Peak Case Tempr over Mosfet Location
@Room Tempr - 3.3V Output, 500kHz
60
60
50
Temperature (Deg C)
Temperature (Deg C)
0.5
40
30
12V_HS
12V_LS
20
Peak Case Tempr over Mosfet Location
@Room Tempr - 5V Output, 300kHz
50
40
30
20
12V_HS
10
12V_LS
24V_HS
24V_LS
10
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
Load(A)
Load(A)
Figure 20. Peak MOSFET Temperatures 3.3 V Output,
12 V and 24 V Input (500KHz)(5)
2.5
3
3.5
4
Figure 21. Peak Case Temperature Over MOSFET
Locations 5 V Output (300 KHz)
95
Recommended FAN21SV04 Safe Operating Area curves for 70 Deg
Temperature rise VIN = 20V, Natural Convection.
1.8V_Eff 12V Input
6
90
Load Current (Amps)
5
Efficiency(%)
85
300kHz
400kHz
80
500kHz
600kHz
75
4
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
3
2
300KHz
500KHz
1
600Khz
0
70
0
0.5
1
1.5
2
Load(A)
2.5
3
3.5
0
4
2
4
6
8
10
12
14
Output Voltage (Volts)
Figure 23. Typical Output Operating Area Based on
Thermal Limitations
Figure 22. 1.8 VOUT Efficiency Over fSW
Note:
5. Circuit values for this configuration change in Figure 10.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
10
Typical operating characteristics using the Figure 10 circuit. VIN=12 V unless otherwise specified.
VOUT, 1V/div
VOUT, 100mv/div
EN, 1V/div
CLK, 5V/div
IOUT, 2A/div
PGOOD, 5V/div
Figure 24. CLK and VOUT at Startup
Figure 25. Transient Response, 2-4 A Load
VOUT, 1V/div
EN, 2V/div
SW, 10V/div
SW, 10V/div
Figure 26. Startup on Pre-Bias
Figure 27. Restart on Fault
CLK, 5V/div
VOUT, 1V/div
SW, 5V/div
CLK, 5V/div
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
EN, 5V/div
PGOOD, 5V/div
Figure 29.
Figure 28. Shutdown, 1 A Load
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
Slave (500 KHz Free-Run to 600 KHz
Synchronization)
www.fairchildsemi.com
11
PWM Generation
Internal Regulator
Refer to Figure 2 for the PWM control mechanism.
FAN21SV04 uses the summing-mode method of control
to generate the PWM pulses. An amplified currentsense signal is summed with an internally generated
ramp and the combined signal is compared with the
output of the error amplifier to generate the pulse width
to drive the high-side MOSFET. Sensed current from the
previous cycle is used to modulate the output of the
summing block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. RRAMP resistor helps set the charging current for
the internal ramp and provides input voltage feedforward function. The controller facilitates external
compensation for enhanced flexibility.
FAN21SV04 facilitates single-supply operation for input
voltages >6.5 V. At startup, the output of the internal
regulator tracks the input voltage and comes into
regulation (5 V) when VIN_Reg exceeds the UVLO
threshold. The EN pin is released at the same time. The
output voltage of the internal regulator (5 V_Reg) is set
to 5 V. The internal regulator supplies power to all the
control circuits including the drivers.
For applications with VIN<6.5 V, FAN21SV04 can be used
if VIN_Reg is provided with a separate low-power source
>6.5 V. VIN_Reg supply should come up after VIN during
dual-supply operation. The VIN_Reg pin should always be
decoupled with at least a 10 Ω resistor and a 1 µF
ceramic capacitor (see Figure 10, Figure 11).
Since 5 V_Reg is used to drive the internal MOSFET
gates, high peak currents are present on the 5 V_Reg
pin. Connect a >2.2 µf X5R or X7R decoupling capacitor
between the 5 V_Reg pin and AGND. For VIN>20 V
operation, use a 3.3 Ω resistor in series with the boot
capacitor to reduce noise into the regulator.
Initialization
Once VIN_Reg voltage exceeds the UVLO threshold
and EN is HIGH, the IC checks for a shorted FB pin
before releasing the internal soft-start ramp (SS).
If the parallel combination of R1 and RBIAS is ≤ 1 kΩ, the
internal SS ramp is not released and the regulator does
not start.
In addition to supplying power for the control circuits
internally, 5 V_Reg output can be used as a reference
voltage for other applications requiring low noise
reference voltage. 5 V_Reg is capable of sourcing up to
5 mA of output current.
Enable
FAN21SV04 has an internal pull-up to the enable (EN)
pin so that the IC is enabled once VIN_Reg exceeds the
UVLO threshold. Connecting a small capacitor across
EN and AGND delays the rate of voltage rise on the EN
pin. The EN pin also serves for the restart whenever a
fault occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after 5 V_Reg is established. For
applications where such sequencing is required,
FAN21SV04 can be enabled (after the VCC comes up)
with external control, as shown in Figure 30.
When EN is pulled LOW externally, 5 V_Reg output is
still present, but the IC is in standby mode with no
switching.
Soft-Start
FAN21SV04 uses an internal digital soft-start circuit to
slowly ramp up the output voltage and limit inrush
current during startup. When 5 V_Reg is in regulation
and EN is HIGH, the circuit releases SS and enables the
PWM regulator. Soft-start time is a function of the
switching frequency (number of clock cycles).
If auto-restart is not desired, tie the EN pin HIGH with a
logic gate to keep the 1 µA current sink from discharging
EN to 1.1 V. Figure 32 shows one method to pull up EN
to VCC for a latch configuration.
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), only the over-current-protection circuit is
active during soft-start and all other output protections
are inhibited.
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Circuit Operation
In dual-supply operation mode, it is necessary to apply
VIN before VIN_Reg reaches its UVLO threshold to
avoid skipping the soft-start cycle.
VIN_Reg UVLO or toggling the EN pin discharges the
SS and resets the IC.
Figure 30.
Enabling with External Control
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
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12
Auto-Restart
After a fault, the EN pin is discharged with 1 µA current
pull-down to a 1.1 V threshold before the internal 800 kΩ
pull-up is restored. A new soft-start cycle begins when
EN charges above 1.35 V.
Depending on the external circuit, the FAN21SV04 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
Table 1.
Fault / Restart Configurations
EN Pin
Controller / Restart State
Pull to GND
Connected to
5V_Reg with
100KΩ
Open
OFF (Disabled)
Cap to GND
Figure 31. Typical Soft-Start Timing Diagram
No Restart – Latched OFF
Immediate Restart After Fault
New Soft-Start Cycle After EN is
HIGH (Auto Restart Mode)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin HIGH with a
logic gate to keep the 1 µA current sink from discharging
EN to 1.1 V. Figure 32 shows one method to pull up EN
to VCC for a latch configuration.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76 V). This enables the regulator to startup
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and undervoltage conditions.
Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This protection is not active until
the internal SS ramp reaches 1.0 V during soft-start.
Figure 32.
Enable Control with Latch Option
Power Good (PGOOD) Signal
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin.
The thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0) (see Figure 31).
Over-Voltage Protection
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV/UV fault conditions are not allowed to set the
fault latch during soft-start. They are active only after
T1.0 (see Figure 31).
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
13
transient response use a higher ripple-current setting
while regulator designs that require higher efficiency
keep ripple current on the low side and operate at a
lower switching frequency. The inductor value is
calculated by the following formula:
5 V_Reg Output
The 5 V_Reg pin is the output of the internal regulator
that supplies all power to the control circuit. It is
important to keep this pin decoupled to AGND with a
>2.2 µf X5R or X7R decoupling capacitor. In addition,
for operation with VIN>20 V, add a 3.3 Ω resistor in
series with the boot capacitor to reduce the switching
noise into the regulator.
L=
The output voltage of the regulator can be set from
0.8 V to ~80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1). For output voltages >3.3 V,
output current rating may need to be de-rated depending
on the ambient temperature, power dissipated in the
package, and the PCB layout (refer to Thermal
Information table on page 4, Figure 20, Figure 21, and
Figure 23).
Setting the Ramp Resistor Value
RRAMP resistor plays a critical role by providing charging
current to the internal ramp capacitor and also serving
as a means to provide input voltage feedforward.
RRAMP is calculated by the following formula:
R RAMP(KΩ ) =
The internal reference is set to 0.8 V with 650 nA
sourced from the FB pin to ensure that the regulator
does not start if the pin is left open.
−2
(4)
For wide input operation, first calculate RRAMP for the
minimum and maximum input voltage conditions and
use larger of the two values calculated.
(1)
In all applications, current through the RRAMP pin must
be greater than 10 µA from the equation below for
proper operation:
Connect RBIAS between FB and AGND.
If R1 is open (see Figure 1), the output voltage is not
regulated and a latched fault occurs after the SS is
complete (T1.0).
VIN − 1.8
≥ 10 μA
RRAMP + 2
If the parallel combination of R1 and RBIAS is ≤ 1 KΩ, the
internal SS ramp is not released and the regulator does
not start.
(5)
If the calculated RRAMP values in Equation (4) result in a
current less than 10 µA, use the RRAMP value that
satisfies Equation (5). In applications with large Input
ripple voltage, the RRAMP resistor should be adequately
decoupled from the input voltage to minimize ripple on
the ramp pin.
Setting the Switching Frequency
Switching frequency is determined by a resistor, RT,
connected between the RT pin and AGND (Master
Mode) or 5 V_Reg (Slave Mode):
Setting the Current Limit
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the lowside MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 33 shows a simplified schematic of the overcurrent system.
where RT is expressed in kΩ:
(106 / f ) − 135
65
( VIN − 1.8 ) • VOUT
(30.5 − 4.5 • IOUT ) • VIN • f • 10 − 6
where frequency (f) is expressed in KHz.
The external resistor divider is calculated using:
RT (KΩ ) =
(3)
where f is the switching frequency.
Setting the Output Voltage
V
− 0 .8 V
0 .8 V
= OUT
+ 650nA
R BIAS
R1
VOUT
)
VIN
ΔIL • f
VOUT • (1 -
(2)
where frequency (f) is expressed in KHz.
In Slave Mode, the switching frequency is about 10%
slower for the same RT. The regulator does not start if
RT is open in Master Mode.
Calculating the Inductor Value
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Application Information
Typically the inductor value is chosen based on ripple
current (ΔIL), which is chosen between 10 to 35% of the
maximum DC load. Regulator designs that require fast
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
14
VERR
+
_
complete Type-3 compensation network.
compensation eliminates R3 and C3.
PWM
COMP
Type-2
PWM
VCC
VILIM
+
_
MAX
ILIMIT
10µA
+
_
ILIM
ADJUST
ILIMIT
ILIMTRIP
RILIM
Figure 34. Compensation Network
Figure 33. Current-Limit System Schematic
Since the FAN21SV04 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
VRILIM = 10µA*RILIM
(6)
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which can make it difficult
to compensate the loop. For low-input-voltage-range
designs (3 V to 8 V), RRAMP and the compensation
component values are different as compared to designs
with VIN between 8 V and 24 V.
To calculate RILIM:
RILIM = VRILIM/ 10µA
(7)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
RILIM = (VBOT + VRMPEAK)/ 10µA
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW *0.03*RRAMP)}/10µA
Master / Slave Configuration
(8)
When first enabled, the IC determines if it is configured
as a master or slave for synchronization, depending on
how RT is connected.
(9)
Table 2.
where:
Master / Slave Configuration
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
RT to:
Master / Slave
VRMPEAK = D*(VIN – 1.8)/(fSW *0.03*RRAMP);
GND
Master
ILOAD = the desired maximum load current;
5V_Reg
RDSON = the nominal RDSON of the low-side MOSFET;
Output
Input
Slaves free-run in the absence of an external clock
signal input when RT is connected to 5 V_Reg, allowing
regulation to be maintained. It is not recommended to
leave RT open when running in Slave Mode to avoid
noise pick up on the clock pin.
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
D = VOUT/VIN duty cycle;
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum
synchronizing
clock
frequency
is
recommended to be below 600 KHz.
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in kΩ.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
Synchronization
The synchronization method employed by the
FAN21SV04 also provides the following features for
maximum flexibility.
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
Loop Compensation
The control loop is compensated using a feedback
network around the error amplifier. Figure 34 shows a
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
Slave, free-running
CLK Pin
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
RAMP
Synchronization to an external system clock
Multiple FAN21SV04s can be synchronized to a
single master or system clock
www.fairchildsemi.com
15
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with two-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
The FAN21SV04 master outputs an 85 ns-wide clock
(CLK) signal, delayed 180o from its leading PWM edge.
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40 ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8 V threshold and a 200 µA
current source pull-up.
SW
In Master Mode, the clock signals go out after powergood signal asserts HIGH. Likewise, in Slave Mode,
synchronization to an external clock signal occurs after
the power-good signal goes HIGH. Until then, the
converter operates in free-run mode.
VIN
PGND
PGND
VOUT
Figure 38. Recommended PCB Layout
Figure 35. Synchronization Timing Diagram
Figure 36. Slave-CLK-Input Block Diagram
One or more slaves can be connected directly to a
master or system clock to achieve a 180o phase shift.
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Figure 37. Slaves with 180o Phase Shift
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180o.
The FAN21SV04 is not intended for use in single-output,
multi-phase regulator applications.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
16
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
OPTIONAL LEAD DESIGN
(LEADS# 1, 24 & 25 ONLY)
SCALE: 1.5X
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV3
BOTTOM VIEW
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
Physical Dimensions
Figure 39. 5x6 mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
17
FAN21SV04 — TinyBuck™ 4 A, 24 V Single-Input Integrated Synchronous Buck Regulator
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.3
www.fairchildsemi.com
18