2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241 FEATURES 225 ps Propagation Delay through the Switch 4.5 Switch Connection between Ports Data Rate 1.5 Gbps 2.5 V/3.3 V Supply Operation Selectable Level Shifting/Translation Level Translation 3.3 V to 2.5 V 3.3 V to 1.8 V 2.5 V to 1.8 V Small Signal Bandwidth 770 MHz Tiny 6-Lead SC70 Package and 6-Lead SOT-66 Package FUNCTIONAL BLOCK DIAGRAM A B BE APPLICATIONS 3.3 V to 1.8 V Voltage Translation 3.3 V to 2.5 V Voltage Translation 2.5 V to 1.8 V Voltage Translation Bus Switching Bus Isolation Hot Swap Hot Plug Analog Switch Applications GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3241 is a 2.5 V or 3.3 V, single digital switch. It is designed on a low voltage CMOS process, which provides low power dissipation yet gives high switching speed and very low on resistance. This allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. 1. 2. 3. 4. 5. 3.3 V or 2.5 V supply operation. Extremely low propagation delay through switch. 4.5 Ω switches connect inputs to outputs. Level/voltage translation. Tiny SC70 package and SOT-66 package. The switch is enabled by means of the bus enable (BE) input signal. This digital switch allows a bidirectional signal to be switched when ON. In the OFF condition, signal levels up to the supplies are blocked. This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, a level translating select pin (SEL) is included. When SEL is low, VCC is reduced internally, allowing for level translation between 3.3 V inputs and 1.8 V outputs. This makes the device suited to applications requiring level translation between different supplies, such as converter to DSP/microcontroller interfacing. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. ADG3241–SPECIFICATIONS1 Parameter Symbol DC ELECTRICAL CHARACTERISTICS Input High Voltage VINH VINH Input Low Voltage VINL VINL Input Leakage Current II OFF State Leakage Current IOZ ON State Leakage Current Maximum Pass Voltage VP CAPACITANCE3 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance (VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.) Conditions Min VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V 2.0 1.7 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VA/VB = VCC = SEL = 3.3 V, IO = –5 µA VA/VB = VCC = SEL = 2.5 V, IO = –5 µA VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA CA OFF CB OFF CA, CB ON CIN f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ CL = 50 pF, VCC = SEL = 3 V VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = VCC VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 3.0 V to 3.6 V; SEL = 0 V VCC = 2.3 V to 2.7 V; SEL = VCC VCC = 2.3 V to 2.7 V; SEL = VCC VCC = SEL = 3.3 V; VA/VB = 2 V VCC = SEL = 3.3 V; VA/VB = 2 V DIGITAL SWITCH On Resistance RON VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA POWER REQUIREMENTS VCC Quiescent Power Supply Current ICC Digital Inputs = 0 V or VCC; SEL = VCC Digital Inputs = 0 V or VCC; SEL = 0 V VCC = 3.6 V, BE = 3.0 V; SEL = VCC SWITCHING CHARACTERISTICS3 Propagation Delay A to B or B to A, tPD4 Bus Enable Time BE to A or B5 Bus Disable Time BE to A or B5 Bus Enable Time BE to A or B5 Bus Disable Time BE to A or B5 Bus Enable Time BE to A or B5 Bus Disable Time BE to A or B5 Maximum Data Rate Channel Jitter Increase in ICC per Input6 2.2 1.5 1.5 B Version Typ2 Max ± 0.01 ± 0.01 ± 0.01 2.5 1.8 1.8 3.5 3.5 7 4 1 1 1 1 1 1 3.2 3 3 2.5 3 2.5 1.5 45 4.5 12 5 9 5 12 2.3 ⌬ICC 0.8 0.7 ±1 ±1 ±1 2.7 2.1 2.1 0.01 0.1 0.15 Unit V V V V µA µA µA V V V pF pF pF pF 0.225 4.6 4 4 3.8 4 3.4 ns ns ns ns ns ns ns Gbps ps p-p 8 28 9 18 8 Ω Ω Ω Ω Ω Ω 3.6 1 0.2 8 V µA mA µA NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Typical values are at 25°C, unless otherwise stated. 3 Guaranteed by design, not subject to production test. 4 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5 See Timing Measurement Information section. 6 This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition. Specifications subject to change without notice. –2– REV. A ADG3241 ABSOLUTE MAXIMUM RATINGS* Table I. Truth Table (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C SC70 Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 332°C/W SOT-66 Package JA Thermal Impedance . . . . . . . . . 191°C/W (4-Layer Board) Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C BE SEL* Function L L H L H X A = B, 3.3 V to 1.8 V Level Shifting A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting Disconnect *SEL = 0 V only when V DD = 3.3 V ± 10%. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3241 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– ADG3241 PIN CONFIGURATION 6-Lead SC70 BE 1 2 6 ADG3241 Table II. Pin Function Descriptions SEL 5 VCC TOP VIEW A 3 (Not to Scale) 4 B GND 6-Lead SOT-66 VCC 1 SEL 2 6 ADG3241 BE Pin No. SC70 SOT-66 Mnemonic Description 1 2 3 4 5 6 BE GND A B VCC SEL Bus Enable (Active Low) Ground Reference Port A, Input or Output Port B, Input or Output Positive Power Supply Voltage Level Translation Select 6 4 3 5 1 2 5 B TOP VIEW A 3 (Not to Scale) 4 GND ORDERING GUIDE Model Temperature Range Package Description Package Branding ADG3241BKS-REEL ADG3241BKS-REEL7 ADG3241BKS-500RL7 ADG3241BRY-REEL7 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Thin Shrink Small Outline Transistor Package (SC70) Thin Shrink Small Outline Transistor Package (SC70) Thin Shrink Small Outline Transistor Package (SC70) Small Outline Transistor Package (SOT-66) KS-6 KS-6 KS-6 RY-6-1 SKA SKA SKA 00 TERMINOLOGY VCC GND VINH VINL II IOZ IOL VP RON CX OFF CX ON CIN ICC ⌬ICC tPLH, tPHL tPZH, tPZL tPHZ, tPLZ Max Data Rate Channel Jitter Positive Power Supply Voltage. Ground (0 V) Reference. Minimum Input Voltage for Logic 1. Maximum Input Voltage for Logic 0. Input Leakage Current at the Control Inputs. OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state. ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state. Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when the switch input voltage is equal to the supply voltage. Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified amount of current through the switch. OFF Switch Capacitance. ON Switch Capacitance. Control Input Capacitance. This consists of BE and SEL. Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins. It is measured when all control inputs are at a logic high or low level and the switches are OFF. Extra power supply current component for the BE control input when the input is not driven at the supplies. Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant RON × CL, where CL is the load capacitance. Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on in response to the control signal, BE. Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.) Maximum Rate at which Data Can Be Passed through the Switch. Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel. –4– REV. A Typical Performance Characteristics–ADG3241 40 35 VCC = 2.3V TA = 25C SEL = VCC 35 30 30 VCC = 3.3V 20 15 RON () 25 VCC = 3V TA = 25C SEL = 0V 35 30 RON () RON () 40 40 VCC = 3V TA = 25C SEL = VCC 25 VCC = 2.5V 20 25 VCC = 3.3V 20 15 15 VCC = 3.6V VCC = 2.7V 10 VCC = 3.6V 5 0 0 0.5 1.0 2.0 1.5 VA/VB (V) 3.0 2.5 10 10 5 5 0 3.5 0 0 TPC 1. On Resistance vs. Input Voltage 1.0 0.5 2.0 1.5 VA/VB (V) 2.5 3.0 0 3.0 15 VCC = 3.3V 1.0 TA = 25C SEL = VCC IO = –5A VCC = 2.5V SEL = VCC 1.5 2.0 VA/VB (V) 2.5 3.0 3.5 TPC 3. On Resistance vs. Input Voltage TPC 2. On Resistance vs. Input Voltage 20 0.5 SEL = VCC 2.5 VCC = 3.6V 15 10 85C VOUT (V) RON () RON () 10 85C VCC = 3.3V VCC = 3V 1.5 1.0 5 5 2.0 40C 25C 25C 0.5 40C 0 0 1.0 VA/VB (V) 0.5 0 2.0 1.5 TPC 4. On Resistance vs. Input Voltage for Different Temperatures 0 0 0.5 VA/VB (V) 1.2 1.0 2.0 1.0 2.0 1.5 VA/VB (V) 2.5 3.0 3.5 500 2.5 TA = 25C SEL = VCC IO = –5A 0.5 TPC 6. Pass Voltage vs. VCC TPC 5. On Resistance vs. Input Voltage for Different Temperatures 2.5 0 VCC = 2.7V TA = 25C SEL = 0V IO = –5A 2.0 TA = 25C 450 VCC = 3.6V 400 VCC = 2.3V 1.0 1.5 VCC = 3.3V VCC = 3V 1.0 ICC (A) VCC = 2.5V VOUT (V) VOUT (V) 350 1.5 VCC = SEL = 3.3V 300 VCC = 3.3V SEL = 0V 250 200 150 0.5 0.5 100 VCC = SEL = 2.5V 50 0 0 0.5 1.0 2.0 1.5 VA/VB (V) 2.5 TPC 7. Pass Voltage vs. VCC REV. A 3.0 0 0 0.5 1.0 1.5 2.0 VA/VB (V) 2.5 3.0 TPC 8. Pass Voltage vs. VCC –5– 3.5 0 0 5 10 15 20 25 30 35 40 45 50 ENABLE FREQUENCY (MHz) TPC 9. ICC vs. Enable Frequency ADG3241 3.0 3.0 TA = 25C VA = 0V BE = 0 2.5 VCC = SEL = 3.3V 1.0 0.5 0 0.02 0.04 0.06 IO (A) 0.08 –0.8 0.5 –1.0 0 –0.10 ATTENUATION (dB) 0 –1 –2 –3 TA = 25C VCC = 3.3V/2.5V SEL = VCC VIN = 0dBm N/W ANALYZER: RL = RS = 50 –6 –7 –8 0.03 0.1 –0.06 –0.04 IO (A) –0.02 1.0 1.5 2.0 VA/VB (V) 2.5 3.0 TPC 12. Charge Injection vs. Source Voltage 3.5 ENABLE DISABLE VCC = SEL = 3.3V 3.0 –60 2.5 ENABLE DISABLE 2.0 1.5 VCC = 3.3V, SEL = 0V –70 1.0 0.5 –90 10 100 1.0 FREQUENCY (MHz) 1000 –100 0.1 1 10 100 FREQUENCY (MHz) 1000 DISABLE 2.0 1.5 70 60 50 40 30 20 20 40 60 0 TEMPERATURE (C) 80 TPC 16. Enable/Disable Time vs. Temperature 95 VCC = SEL = 3.3V 90 V = 1.5V p-p IN 85 20dB ATTENUATION 80 75 70 60 10 0 0.5 80 65 1.0 0.5 20 40 60 0 TEMPERATURE (C) 100 EYE WIDTH (%) VCC = SEL = 2.5V JITTER (ps p-p) ENABLE –20 TPC 15. Enable/Disable Time vs. Temperature VCC = SEL = 3.3V 90 V = 1.5V p-p IN 80 20dB ATTENUATION 2.5 0 –40 TPC 14. Off Isolation vs. Frequency 100 –20 0.5 4.0 –50 3.5 0 –40 0 –80 4.0 3.0 –1.2 0 0 TA = 25C –10 VCC = 3.3V/2.5V SEL = V CC –20 VIN = 0dBm –30 N/W ANALYZER: RL = RS = 50 –40 TPC 13. Bandwidth vs. Frequency TIME (ns) –0.08 TPC 11. Output High Characteristic 1 –4 VCC = 3.3V 1.0 V = SEL = 2.5V CC 0.10 2 –5 –0.6 VCC = 3.3V; SEL = 0V TPC 10. Output Low Characteristic ATTENUATION (dB) 1.5 VCC = SEL = 2.5V 0 VCC = 2.5V –0.4 QINJ (pC) 1.5 VCC = SEL = 3.3V 2.0 VCC = 3.3V; SEL = 0V VOUT (V) VOUT (V) 2.0 TA = 25C SEL = VCC ON OFF CL = 1nF –0.2 TIME (ns) 2.5 0 TA = 25C VA = VCC BE = 0 55 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 TPC 17. Jitter vs. Data Rate; PRBS 31 –6– % EYE WIDTH = ((CLOCK PERIOD – JITTER p-p)/CLOCK PERIOD) 100% 50 0.5 0.7 0.9 1.1 1.3 1.5 1.7 DATA RATE (Gbps) 1.9 TPC 18. Eye Width vs. Data Rate; PRBS 31 REV. A ADG3241 50mV/DIV 200ps/DIV VCC = 3.3V SEL = 3.3V VIN = 1.5V p-p 20dB ATTENUATION TA = 25C TPC 19. Eye Pattern; 1.5 Gbps, VCC = 3.3 V, PRBS 31 REV. A 20mV/DIV 200ps/DIV VCC = 2.5V SEL = 2.5V VIN = 1.5V p-p 20dB ATTENUATION TA = 25C TPC 20. Eye Pattern; 1.244 Gbps, VCC = 2.5 V, PRBS 31 –7– ADG3241 TIMING MEASUREMENT INFORMATION For the following load circuit and waveforms, the notation that is used is VIN and VOUT where VIN = VA and VOUT = VB or VIN = VB and VOUT = VA VCC PULSE GENERATOR CONTROL INPUT BE tPLH 0V VH VT VOUT DUT VL RL CL RT VT tPLH GND RL VOUT VIN VIH 2 VCC SW1 Figure 2. Propagation Delay NOTES PULSE GENERATOR FOR ALL PULSES: tR ⱕ 2.5ns, tF ⱕ 2.5ns, FREQUENCY ⱕ 10MHz. CL INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES. RT IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO ZOUT OF THE PULSE GENERATOR. Figure 1. Load Circuit Test Conditions Symbol VCC = 3.3 V ± 0.3 V (SEL = VCC) VCC = 2.5 V ± 0.2 V (SEL = VCC) VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit RL V⌬ CL VT 500 300 50 1.5 500 150 30 0.9 500 150 30 0.9 Ω mV pF V DISABLE ENABLE VINH VT CONTROL INPUT BE Table III. Switch Position 0V tPZL VIN = 0V VOUT SW1 @ 2VCC tPLZ VCC VCC VT VL + V VL tPZH VIN = VCC VOUT SW1 @ GND Test S1 tPLZ, tPZL tPHZ, tPZH 2 × VCC GND tPHZ VH VT 0V VH – V 0V Figure 3. Enable and Disable Times –8– REV. A ADG3241 BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation 2.5 V to 1.8 V Translation When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is 0 V to VCC, the maximum output signal will, as before, be clamped to within a voltage threshold below the VCC supply. In this case, the output will be limited to approximately 1.8 V, as shown in Figure 8. Bus switches can provide an ideal solution for interfacing between mixed voltage systems. The ADG3241 is suitable for applications where voltage translation from 3.3 V technology to a lower voltage technology is needed. This device can translate from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly to 2.5 V. 2.5V Figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor may not have 3.3 V tolerant inputs, therefore placing the ADG3241 between the two devices allows the devices to communicate easily. The bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. ADG3241 2.5V 1.8V Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC 2.5V 3.3V ADG3241 VOUT 3.3V ADC 2.5V MICROPROCESSOR 1.8V Figure 4. Level Translation between a 3.3 V ADC and a 2.5 V Microprocessor 3.3 V to 2.5 V Translation 0V When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is 0 V to VCC, the maximum output signal will be clamped to within a voltage threshold below the VCC supply. VIN 2.5V Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC The ADG3241 offers the option of interfacing between a 3.3 V device and a 1.8 V device. This is possible through use of the SEL pin. The SEL pin is an active low control pin. SEL activates internal circuitry in the ADG3241 that allows voltage translation between 3.3 V devices and 1.8 V devices. 2.5V ADG3241 3.3V 2.5V 2.5V SWITCH INPUT 3.3 V to 1.8 V Translation 3.3V 3.3V 2.5V SUPPLY SEL = 2.5V SWITCH OUTPUT 3.3V Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC In this case, the output will be limited to 2.5 V, as shown in Figure 6. This device can be used for translation from 2.5 V to 3.3 V devices and also between two 3.3 V devices. VOUT 1.8V Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V 3.3V SUPPLY SEL = 3.3V When VCC is 3.3 V and the input signal range is 0 V to VCC, the maximum output signal will be clamped to 1.8 V, as shown in Figure 9. To do this, the SEL pin must be tied to Logic 0. If SEL is unused, it should be tied directly to VCC. SWITCH OUTPUT 2.5V 0V ADG3241 3.3V SWITCH INPUT VOUT VIN 3.3V 3.3V SUPPLY SEL = 0V 1.8V SWITCH OUTPUT Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC 0V SWITCH INPUT VIN 3.3V Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V REV. A –9– ADG3241 Bus Isolation A common requirement of bus architectures is low capacitance loading of the bus. Such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. Because the ADG3241 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. The device isolates access to the bus, thus minimizing capacitance loading. LOAD A LOAD C Analog Switching Bus switches can be used in many analog switching applications, for example, video graphics. Bus switches can have lower on resistance, smaller ON and OFF channel capacitance, and thus improved frequency performance than their analog counterparts. The bus switch channel itself, consisting solely of an NMOS switch, limits the operating voltage (see TPC 1 for a typical plot), but in many cases, this does not present an issue. BUS/ BACKPLANE LOAD D LOAD B BUS SWITCH LOCATION There are many systems, such as docking stations, PCI boards for servers, and line cards for telecommunications switches, that require the ability to handle hot swapping. If the bus can be isolated prior to insertion or removal, there is more control over the hot swap event. This isolation can be achieved using bus switches. The bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the hot swap card must connect to the ground pin of the backplane before any other signal or power pins. Figure 11. Location of Bus Switched in a Bus Isolation Application High Impedance During Power-Up/Power-Down Hot Plug and Hot Swap Isolation The ADG3241 is suitable for hot swap and hot plug applications. The output signal of the ADG3241 is limited to a voltage that is below the VCC supply, as shown in Figures 6, 8, and 10. Therefore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage. To ensure the high impedance state during power-up or powerdown, BE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. CPU RAM ADG3241 ADG3241 In hot plug applications, the system cannot be shut down when new hardware is being added. To overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. The bus switch is turned off during hot plug. Figure 12 shows a typical example of this type of application. PLUG-IN CARD (1) CARD I/O PLUG-IN CARD (2) CARD I/O Figure 12. ADG3241 in a Hot Plug Application –10– REV. A ADG3241 OUTLINE DIMENSIONS 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 2.00 BSC 6 5 4 1 2 3 2.10 BSC 1.25 BSC PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.30 0.15 0.10 MAX 0.46 0.36 0.26 8 4 0 SEATING PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB 6-Lead Small Outline Transistor Package [SOT-66] (RY-6-1) Dimensions shown in millimeters 1.70 1.66 1.50 6 1.30 1.20 1.10 5 0.26 0.19 0.11 4 TOP VIEW PIN 1 1 2 3 12 MAX BOTTOM VIEW 0.10 NOM 0.05 MIN 0.60 0.57 0.53 0.18 0.17 0.13 0.34 MAX 0.27 NOM REV. A 1.70 1.65 1.50 0.20 MIN SEATING PLANE –11– 0.50 BSC 0.25 MAX 0.17 MIN 0.30 0.23 0.10 ADG3241 Revision History Location Page 10/04—Data Sheet changed from REV. 0 to REV. A. Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 –12– REV. A C04221–0–11/04(A) Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1