ISSI IS65WV10248DALL Ttl compatible interface level Datasheet

IS62WV10248DALL/BLL
IS65WV10248DALL/BLL
1M x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
MAY 2009
DESCRIPTION
The ISSI IS62WV10248DALL/ IS62WV10248DBLL are • High-speed access time: 45ns, 55ns
high-speed, 8M bit static RAMs organized as 1M words
by 8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields highperformance and low power consumption devices.
• CMOS low power operation
– 30 mW (typical) operating
– 12 µW (typical) CMOS standby
• TTL compatible interface levels
When CS1 is HIGH (deselected) or when CS2 is low
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
• Single power supply – 1.65V--2.2V Vdd (62/65WV10248DALL)
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
– 2.4V--3.6V Vdd (62/65WV10248DBLL)
• Fully static operation: no clock or refresh
required
The IS62WV10248DALL and IS62WV10248DBLL are
packaged in the JEDEC standard 48-pin mini BGA (9mm
x 11mm) and 44-Pin TSOP (TYPE II).
• Three state outputs
• Data control for upper and lower bytes
• Automotive temperature (-40oC to +125oC)
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1M x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
1
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
PIN CONFIGURATION (1M x 8 Low Power)
48-pin mini BGA (B) (9mm x 11mm)
1
2
3
4
5
44-pin TSOP (Type II)
6
A
NC
OE
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1
NC
C
I/O0
NC
A5
A6
NC
I/O4
D
GND
I/O1
A17
A7
I/O5
VDD
E
VDD
I/O2
NC
A16
I/O6
VSS
F
I/O3
NC
A14
A15
NC
I/O7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
A4
A3
A2
A1
A0
CS1
NC
NC
I/O0
I/O1
VDD
GND
I/O2
I/O3
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
NC
NC
I/O7
I/O6
GND
VDD
I/O5
I/O4
NC
NC
A9
A10
A11
A12
A13
A14
PIN DESCRIPTIONS
A0-A19
CS1 CS2 OE
WE I/O0-I/O7
NC
Vdd
GND
2
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
No Connection
Power
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
X
H
H
L
CS2
X
L
H
H
H
CS1
H
X
L
L
L
OE
X
X
H
L
X
I/O Operation
High-Z High-Z
High-Z
Dout
Din
Vdd Current
Isb1, Isb2
Isb1, Isb2
Icc
Icc
Icc
OPERATING RANGE (Vdd)
1.65V - 2.2V
2.4V - 3.6V
0°C to +70°C
IS62WV10248DALL (55ns)
IS62WV10248DBLL (55ns)*
Industrial
–40°C to +85°C
IS62WV10248DALL (55ns)
IS62WV10248DBLL (55ns)*
Automotive
–40°C to +125°C
IS65WV10248DALL (70ns)
IS65WV10248DBLL (55ns)
Range
Ambient Temperature
Commercial
*When operated in the range for 3.3V ± 5% or when operated in the temperature range of 0°C to 70°C,
the device meets 45ns.
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
5
7
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
3
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tbias
Vdd
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vdd Related to GND
Storage Temperature
Power Dissipation
Value
–0.2 to Vdd+0.3
–40 to +125
–0.2 to +3.8
–65 to +150
1.0
Unit
V
°C
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Voh
Output HIGH Voltage
Ioh = -0.1 mA
Ioh = -1 mA
Vol
Output LOW Voltage
Iol = 0.1 mA
Iol = 1 mA
Vih
Input HIGH Voltage
Vil(1)
Input LOW Voltage
Ili
Ilo
Input Leakage
Output Leakage
Vdd
1.65-2.2V
2.4-3.6V
1.65-2.2V
2.4-3.6V
1.65-2.2V
2.4-3.6V
1.65-2.2V
2.4-3.6V
GND ≤ Vin ≤ Vdd
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
1.8
—
—
1.4
2.0
–0.2
–0.2
–1
–1
Max.
—
—
0.2
0.4
Vdd + 0.2
Vdd + 0.3
0.4
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. Vil (min.) = –0.3V DC; Vil (min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max) = Vdd + 2.0V AC (pulse width < 10ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
R1(Ω)
R2(Ω)
Vref
62WV10248DALL
(Unit)
0.4V to Vdd-0.2
5 ns
Vref
See Figures 1 and 2
62W10248DALL
(1.65V - 2.2V)
3070
3150
62WV10248DBLL
(2.4V - 3.6V)
1029
1728
0.9V
1.8V
1.5V
3.0V
Vtm
62WV10248DBLL
(Unit)
0.4V to Vdd-0.3V
5ns
Vref
See Figures 1 and 2
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
R2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
5 pF
Including
jig and
scope
R2
Figure 2
5
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
1.65V-2.2V, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions Max.
Max.
Unit
55
70
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
20
20
mA
Supply Current
Iout = 0 mA, f = fmax
Ind. 25
25
Auto. –
35
typ.(1)
10
Icc1
Operating Supply
Vdd = Max., CS1 = 0.2V
Com.
4
4
mA
Current
WE = Vdd – 0.2V
Ind.
4
4
CS2 = Vdd – 0.2V, f = 1mhz
Auto. –
4
Isb2
CMOS Standby
Vdd = Max.,
Com. 20
20
µA
Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,
Ind. 40
40
CS2 ≤ 0.2V,
Auto. –
90
Vin ≥ Vdd – 0.2V, or
typ.(1) 4
Vin ≤ 0.2V, f = 0
Note:.
1. Typical values are measured at Vdd = 1.8V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
2.4V-3.6V, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions Max.
45
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
20
Supply Current
Iout = 0 mA, f = fmax
Ind. 25
Auto. –
typ.(2)
10
Icc1
Operating Supply
Vdd = Max., CS1 = 0.2V
Com. 5
Current
WE = Vdd – 0.2V
Ind. 5
CS2 = Vdd – 0.2V, f = 1mhz
Auto. –
Isb2
CMOS Standby
Vdd = Max.,
Com. 20
Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V,
Ind. 40
CS2 ≤ 0.2V,
Auto. –
Vin ≥ Vdd – 0.2V, or
typ. (2)
4
Vin ≤ 0.2V, f = 0
Max.
Unit
55
17
mA
22
35
5
5
5
20
40
110
mA
µA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
7
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tacs1/tacs2
tdoe
thzoe(2)
tlzoe(2)
thzcs1/thzcs2(2)
tlzcs1/tlzcs2(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CS1/CS2 Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
45 ns
Min.
45
—
10
—
—
—
5
0
10
55 ns
Min.
55
—
10
—
—
—
5
0
10
Max.
—
45
—
45
20
15
—
15
—
Max.
—
55
—
55
25
20
—
20
—
70 ns
Min.
70
—
10
—
—
—
5
0
10
Max.
—
70
—
70
35
25
—
25
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih)
tRC
ADDRESS
tAA
tOHA
DOUT
8
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= Vil. CS2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
9
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
twc
tscs1/tscs2
taw
tha
tsa
tpwe(4)
tsd
thd
thzwe(3)
tlzwe(3)
45ns
Min. Max.
45
—
35
—
35
—
0
—
0
—
35
—
20
—
0
—
—
20
5
—
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
55 ns
Min. Max.
55
—
45
—
45
—
0
—
0
—
40
—
25
—
0
—
—
20
5
—
70 ns
Min. Max.
70
—
60
—
60
—
0
—
0
—
50
—
30
—
0
—
—
30
5
—
Unit
ns
ns
ns
ns
ns
ns
ns
­ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can
go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tpwe > thzwe + tsd when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
10
tHD
DATA-IN VALID
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Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
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Rev. A
05/11/09
tHD
DATA-IN VALID
11
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V - 3.6V)
Symbol
Idr
Parameter
Vdd for Data Retention
Data Retention Current
tsdr
trdr
Data Retention Setup Time
Recovery Time
Vdr
Test Condition
See Data Retention Waveform
Vdd = 1.4V, CS1 ≥ Vdd – 0.2V
Com.
Ind.
Auto.
See Data Retention Waveform
See Data Retention Waveform
Min.
1.4
—
—
—
0
Typ.*
4
trc
Max.
3.6
20
40
95
—
—
Unit
V
µA
ns
ns
* Typical Values are measured at VDD = 3V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
Data Retention Mode
tSDR
tRDR
VDD
VDR
CS1
CS1
GND
VDD - 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
VDD
CE2
tSDR
tRDR
VDR
CS2
0.2V
GND
12
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Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
ORDERING INFORMATION
IS62WV10248DALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
55
Order Part No.
IS62WV10248DALL-55TI
IS62WV10248DALL-55TLI
IS62WV10248DALL-55MI
IS62WV10248DALL-55MLI
Package
TSOP-II
TSOP-II, Lead-free
mini BGA (9mmx11mm)
mini BGA (9mmx11mm), Lead-free
IS62WV10248DBLL (2.4V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
55*
Order Part No.
IS62WV10248DBLL-55TI
IS62WV10248DBLL-55TLI
IS62WV10248DBLL-55MI
IS62WV10248DBLL-55MLI
Package
TSOP-II
TSOP-II, Lead-free
mini BGA (9mmx11mm)
mini BGA (9mmx11mm), Lead-free
*When operated in the range for 3.3V ± 5% or when operated in the temperature range of 0°C to 70°C, the device meets 45ns.
IS65WV10248DBLL (2.4V - 3.6V)
Industrial Range: –40°C to +125°C
Speed (ns)
55
Order Part No.
IS65WV10248DBLL-55CTLA3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
Package
TSOP-II, Lead-free, Copper Lead-frame
13
14
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
08/21/2008
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
15
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