TI1 ADS7044IRUGR Ultra-low power, ultra-small size, 12-bit, 1-msps, sar adc Datasheet

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ADS7044
SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
ADS7044 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC
1 Features
3 Description
•
The ADS7044 is a 1-MSPS, analog-to-digital
converter (ADC). The device supports a wide analog
input voltage range (±1.65 V to ±3.6 V) and includes
a capacitor-based, successive-approximation register
(SAR) ADC with an inherent sample-and-hold circuit.
The SPI-compatible serial interface is controlled by
the CS and SCLK signals. The input signal is
sampled with the CS falling edge and SCLK is used
for conversion and serial data output. The device
supports a wide digital supply range (1.65 V to 3.6 V),
enabling direct interface to a variety of host
controllers. The device complies with the JESD8-7A
standard for normal DVDD range (1.65 V to 1.95 V).
1
•
•
•
•
•
•
•
•
Industry's First SAR ADC with Nanowatt Power
Consumption:
– 261 µW at 1 MSPS with 1.8-V AVDD
– 900 µW at 1 MSPS with 3-V AVDD
– 90 µW at 100 kSPS with 3-V AVDD
– Less than 1 µW at 1 kSPS with 3-V AVDD
Industry's Smallest SAR ADC:
– X2QFN-8 Package with 2.25-mm2 Footprint
1-MSPS Throughput with Zero Data Latency
Wide Operating Range:
– AVDD: 1.65 V to 3.6 V
– DVDD: 1.65 V to 3.6 V (Independent of AVDD)
– Temperature Range: –40°C to 125°C
Excellent Performance:
– 12-Bit Resolution with NMC
– ±1-LSB (Max) DNL and INL
– 71-dB SNR with 3-V AVDD
– –85-dB THD with 3-V AVDD
Unipolar, Differential Input Range:
–AVDD to AVDD
Integrated Offset Calibration
SPI™-Compatible Serial Interface: 16 MHz
JESD8-7A Compliant Digital I/O
The device is available in 8-pin, miniature, leaded,
and X2QFN packages and is specified for operation
from –40°C to 125°C. Miniature form-factor and
extremely low-power consumption make this device
suitable for space-constrained, battery-powered
applications.
Device Information(1)
PART NAME
ADS7044
PACKAGE
BODY SIZE (NOM)
X2QFN (8)
1.50 mm × 1.50 mm
VSSOP (8)
2.30 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
2 Applications
•
•
•
•
•
•
•
•
•
Low-Power Data Acquisition
Battery-Powered Handheld Equipment
Level Sensors
Ultrasonic Flow Meters
Motor Controls
Wearable Fitness
Portable Medical Equipment
Hard Drives
Glucose Meters
space
Typical Application
AVDD used as
Reference for device
AVDD
R
+
AVDD
AINP
Device
C
+
R
AINM
GND
RUG (8)
1.
5m
m
mm
1 .5
Actual Device Size
1.5 x 1.5 x 0.35(H) mm
NOTE: The device is smaller than a 0805
(2012 metric) SMD component.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7044
SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 15
7.1 Digital Voltage Levels ............................................. 14
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 23
10 Power-Supply Recommendations ..................... 29
10.1 AVDD and DVDD Supply Recommendations....... 29
10.2 Estimating Digital Power Consumption................. 29
10.3 Optimizing Power Consumed by the Device ........ 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision C (February 2015) to Revision D
Page
•
Changed Figure 1................................................................................................................................................................... 8
•
Changed Serial Interface section: changed last half of first paragraph, changed Figure 35 ............................................... 19
•
Changed Figure 38............................................................................................................................................................... 22
•
Added Community Resources section ................................................................................................................................ 31
Changes from Revision B (December 2014) to Revision C
Page
•
Changed Wide Operating Range Features bullet: changed the value of AVDD from 1.8 V to 1.65 V .................................. 1
•
Changed the wide analog input voltage range value to ±1.65 V in first paragraph of Description section ........................... 1
•
Changed AVDD parameter minimum specification in Recommended Operating Conditions table ...................................... 5
•
Changed EO parameter uncalibrated test conditions in Electrical Characteristics table ....................................................... 6
•
Changed Maximum throughput rate parameter test conditions in Electrical Characteristics table ....................................... 6
•
Changed AVDD parameter minimum specification in Electrical Characteristics table .......................................................... 7
•
Changed conditions for Timing Characteristics table: changed range of AVDD and added CLOAD condition ....................... 7
•
Changed tD_CKDO specification in Timing Characteristics table .............................................................................................. 7
•
Added fSCLK minimum specification to Timing Characteristics table ...................................................................................... 7
•
Changed titles of Figure 26 to Figure 30 .............................................................................................................................. 12
•
Changed Reference sub-section in Feature Description section ......................................................................................... 16
•
Changed AVDD range in description of fCLK-CAL parameter in Table 2 ................................................................................ 21
•
Changed AVDD range in description of fCLK-CAL parameter in Table 3 ................................................................................. 22
•
Changed Reference Circuit section in Application Information ............................................................................................ 25
•
Added last two sentences to AVDD and DVDD Supply Recommendations section ........................................................... 29
2
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SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
Changes from Revision A (November 2014) to Revision B
Page
•
Changed ESD Ratings table to latest standards ................................................................................................................... 5
•
Added footnote 3 to Electrical Characteristics table .............................................................................................................. 6
•
Changed y-axis unit in Figure 30 ......................................................................................................................................... 13
Changes from Original (November 2014) to Revision A
•
Page
Made changes to product preview data sheet........................................................................................................................ 1
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ADS7044
SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
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5 Pin Configuration and Functions
RUG Package
8-Pin X2QFN
Top View
DCU Package
8-Pin Leaded VSSOP
Top View
CS
1
SDO
SCLK
8
AINM
AINP
2
6
AVDD
3
5
GND
4
7
DVDD
1
8
GND
SCLK
2
7
AVDD
SDO
3
6
AINP
CS
4
5
AINM
DVDD
Pin Functions
PIN
NO.
NAME
RUG
DCU
I/O
AINM
8
5
Analog input
Analog signal input, negative
AINP
7
6
Analog input
Analog signal input, positive
AVDD
6
7
Supply
CS
1
4
Digital input
DVDD
4
1
Supply
Digital I/O supply voltage
GND
5
8
Supply
Ground for power supply, all analog and digital signals are referred to this pin
SCLK
3
2
Digital input
SDO
2
3
Digital output
4
DESCRIPTION
Analog power-supply input, also provides the reference voltage to the ADC
Chip-select signal, active low
Serial clock
Serial data out
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SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
3.9
V
DVDD to GND
–0.3
3.9
V
AINP to GND
–0.3
AVDD + 0.3
V
AINM to GND
–0.3
AVDD + 0.3
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Storage temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
AVDD
Analog supply voltage range
1.65
3.6
UNIT
V
DVDD
Digital supply voltage range
1.65
3.6
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
ADS7044
THERMAL METRIC (1)
RUG (X2QFN)
DCU (VSSOP)
8 PINS
8 PINS
UNIT
235.8
°C/W
RθJA
Junction-to-ambient thermal resistance
177.5
RθJC(top)
Junction-to-case (top) thermal resistance
51.5
79.8
°C/W
RθJB
Junction-to-board thermal resistance
76.7
117.6
°C/W
ψJT
Junction-to-top characterization parameter
1.0
8.9
°C/W
ψJB
Junction-to-board characterization parameter
76.7
116.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input
voltage range
CS
–AVDD
AVDD
AINP to GND
–0.1
AVDD + 0.1
AINM to GND
–0.1
AVDD + 0.1
Sampling capacitance
V
15
pF
12
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
12
INL
Integral nonlinearity
DNL
Differential nonlinearity
Uncalibrated offset error
EO
Calibrated offset error
dVOS/dT
EG
(3)
–1
±0.7
1
AVDD = 1.8 V
–2
±1
2
AVDD = 3 V
–0.99
±0.5
1
AVDD = 1.8 V
–0.99
±0.7
2
AVDD = 3 V
–3
±0.5
3
AVDD = 1.8 V
–4
±1
4
AVDD = 3 V
–0.1
±0.05
0.1
AVDD = 1.8 V
–0.2
±0.1
0.2
AVDD = 1.65 V to 3.6 V
5
Gain error drift with temperature
CMRR
Common-mode rejection ratio
LSB (2)
LSB
±12
Offset error drift with temperature
Gain error
Bits
AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
LSB
ppm/°C
%FS
2
ppm/°C
53
dB
SAMPLING DYNAMICS
tACQ
Acquisition time
Maximum throughput rate
200
ns
16-MHz SCLK, AVDD = 1.65 V to 3.6 V
1
MHz
DYNAMIC CHARACTERISTICS
SNR
Signal-to-noise ratio (4)
THD
Total harmonic distortion (4) (5)
SINAD
Signal-to-noise and distortion (4)
SFDR
BW(fp)
fIN = 2 kHz, AVDD = 3 V
70
fIN = 2 kHz, AVDD = 1.8 V
dB
70
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
71
–85
69.5
dB
71
dB
fIN = 2 kHz, AVDD = 1.8 V
70
Spurious-free dynamic range (4)
fIN = 2 kHz, AVDD = 3 V
85
dB
Full-power bandwidth
At –3 dB, AVDD = 3 V
25
MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
High-level input voltage (6)
0.65 DVDD
DVDD + 0.3
V
VIL
Low-level input voltage (6)
–0.3
0.35 DVDD
V
0.8 DVDD
DVDD
At Isource = 2 mA
DVDD – 0.45
DVDD
At Isink = 500 µA
0
0.2 DVDD
At Isink = 2 mA
0
0.45
VOH
High-level output voltage (6)
VOL
Low-level output voltage (6)
(1)
(2)
(3)
(4)
(5)
(6)
6
At Isource = 500 µA
V
V
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Refer to the Offset Calibration section for more details.
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. See the Digital Voltage Levels section for
more details.
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Electrical Characteristics (continued)
At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-SUPPLY REQUIREMENTS
AVDD
Analog supply voltage
1.65
3
3.6
V
DVDD
Digital I/O supply voltage
1.65
3
3.6
V
At 1 MSPS with AVDD = 3 V
IAVDD
Analog supply current
300
At 100 kSPS with AVDD = 3 V
30
At 1 MSPS with AVDD = 1.8 V
At 1 MSPS with AVDD = 3 V
PD
Power dissipation
µA
145
900
At 100 kSPS with AVDD = 3 V
90
At 1 MSPS with AVDD = 1.8 V
µW
261
6.6 Timing Characteristics
All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF,
unless otherwise specified.
MIN
TYP
MAX
UNIT
1
MSPS
TIMING SPECIFICATIONS
fTHROUGHPUT
Throughput
tCYCLE
Cycle time
tCONV
Conversion time
tDV_CSDO
tD_CKDO
tDZ_CSDO
1
µs
12.5 × tSCLK + tSU_CSCK
ns
Delay time: CS falling to data enable
10
ns
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.8 V to 3.6 V
30
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.65 V to 1.8 V
50
Delay time: CS rising to DOUT going to 3-state
ns
5
ns
ns
TIMING REQUIREMENTS
tACQ
Acquisition time
200
fSCLK
SCLK frequency
0.016
tSCLK
SCLK period
62.5
tPH_CK
SCLK high time
tPL_CK
SCLK low time
tPH_CS
CS high time
60
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
15
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
16
MHz
0.45
0.55
tSCLK
0.45
0.55
tSCLK
ns
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Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
SCLK
1
2
tDV_CSDO
SDO
0
0
tPH_CK
3
4
5
tPL_CK
6
7
8
9
10
11
12
tD_CKDO
D11
D10
tD_CKCS
tSCLK
13
14
tDZ_CSDO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data for Sample N
Figure 1. Timing Diagram
8
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6.7 Typical Characteristics
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
±60
±80
±100
±60
±80
±100
±120
±120
±140
±140
±160
±160
0
100
200
300
400
Input Frequency (kHz)
SNR = 72.58 dB
500
0
100
THD = –93 dB
fIN = 2 kHz
Number of samples = 32768
SNR = 71.95 dB
74
74
SNR and SINAD (dB)
SNR and SINAD (dB)
400
500
C002
Figure 3. Typical FFT
76
SNR
SINAD
72
300
THD = –76.5 dB
fIN = 250 kHz
Number of samples = 32768
Figure 2. Typical FFT
75
73
200
Input Frequency (kHz)
C001
71
SNR
72
70
SINAD
68
70
66
±40
26
±7
59
92
Free-Air Temperature (oC)
125
0
50
100
150
200
Input Frequency (kHz)
C003
250
C004
fIN = 2 kHz
Figure 4. SNR and SINAD vs Temperature
Figure 5. SNR and SINAD vs Input Frequency
75
Total Harmonic Distortion (dB)
±83
SNR and SINAD (dB)
74
SNR
73
SINAD
72
71
70
69
±85
±87
±89
±91
±93
1.8
2.1
2.4
2.7
3
Reference Voltage (V)
3.3
3.6
±40
C005
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
±7
26
59
92
Free-Air Temperature (oC)
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C006
Figure 7. THD vs Free-Air Temperature
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
±82
±70
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
±65
±75
±80
±85
±90
±95
±100
±84
±86
±88
±90
±92
0
50
100
150
200
Input Frequency (kHz)
250
1.8
Figure 8. THD vs Input Frequency
2.7
3
3.3
C010
Figure 9. THD vs Reference Voltage (AVDD)
94
92
90
88
103
98
93
88
83
78
73
68
±40
26
±7
59
92
Free-Air Temperature (oC)
0
125
50
100
150
200
250
Input Frequency (kHz)
C007
Figure 10. SFDR vs Free-Air Temperature
C009
Figure 11. SFDR vs Input Frequency
70000
95
60000
93
Number of Hits
50000
91
89
40000
30000
20000
87
10000
85
0
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
2046
3.6
2047
2048
Code
C011
Mean code = 2046.98
Figure 12. SFDR vs Reference Voltage (AVDD)
10
3.6
108
Spurious-Free Dynamic Range (dB)
Spurious-Free Dynamic Range (dB)
2.4
Reference Voltage (V)
96
Spurious-Free Dynamic Range (dB)
2.1
C008
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2049
C012
Sigma = 0.14
Figure 13. DC Input Histogram
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Typical Characteristics (continued)
12
12
10
10
8
8
6
6
Offset Error (LSB)
Offset Error (LSB)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
4
Calibrated
2
0
±2
±4
±6
4
0
±2
±4
±6
Un-Calibrated
±8
±8
±10
±10
±12
±12
±40
26
±7
59
92
125
Free-Air Temperature (oC)
1.8
2.4
2.7
3
3.3
Reference Voltage (V)
3.6
C014
Figure 15. Offset vs Reference Voltage (AVDD)
0.2
0.2
0.1
0.1
Gain Error (%FS)
Gain Error (%FS)
2.1
C013
Figure 14. Offset vs Free-Air Temperature
0
-0.1
0
-0.1
-0.2
-0.2
±40
26
±7
59
92
125
Free-Air Temperature (oC)
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
C015
Figure 16. Gain Error vs Free-Air Temperature
3.6
C016
Figure 17. Gain Error vs Reference Voltage (AVDD)
1
1
0.75
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Calibrated
2
0.5
0.25
0
-0.25
-0.5
0.5
0.25
0
-0.25
-0.5
-0.75
-0.75
-1
-1
0
512
1024
1536
2048
2560
3072
Code
AVDD = 3 V
3584
4096
0
512
1024
1536
2048
2560
3072
3584
Code
C017
4096
C018
AVDD = 3 V
Figure 18. Typical DNL
Figure 19. Typical INL
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1
0.5
0
-0.5
1
0.5
0
-0.5
-1
-1.5
-1
-2
0
512
1024
1536
2048
2560
3072
3584
Code
0
4096
512
2560
3072
3584
4096
C020
Figure 21. Typical INL
1
1
0.75
0.75
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2048
AVDD = 1.8 V
Figure 20. Typical DNL
0.5
0.25
Maximum
0
-0.25
Minimum
-0.5
-0.75
-1
0.5
Maximum
0.25
0
Minimum
-0.25
-0.5
-0.75
-1
±40
±7
26
59
92
Free-Air Temperature (oC)
125
1.8
2.4
2.7
3
3.3
Reference Voltage (V)
3.6
C022
Figure 23. DNL vs Reference Voltage (AVDD)
1
0.75
0.75
Integral Nonlinearity (LSB)
1
0.5
0.25
Maximum
0
-0.25
Minimum
-0.5
2.1
C021
Figure 22. DNL vs Free-Air-Temperature
Integral Nonlinearity (LSB)
1536
Code
AVDD = 1.8 V
0.5
0.25
Maximum
0
-0.25
-0.5
Minimum
-0.75
-0.75
-1
-1
±40
±7
26
59
92
Free-Air Temperature (oC)
125
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
C023
Figure 24. INL vs Free-Air Temperature
12
1024
C019
3.6
C024
Figure 25. INL vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
300
300
250
\Current (uA)
Current (uA)
280
260
240
220
200
150
100
50
200
0
±40
±7
26
59
92
125
Free-Air Temperature (oC)
0
200
400
600
800
1000
Throughput (Ksps)
C025
fSAMPLE = 1 MSPS
C026
AVDD = 3 V
Figure 26. AVDD Supply Current vs Free-Air Temperature
Figure 27. AVDD Supply Current vs Throughput
175
300
150
250
Current (uA)
Current (uA)
125
100
75
50
200
150
25
100
0
0
200
400
600
800
1.8
1000
Throughput (Ksps)
2.1
2.4
2.7
3
3.3
Supply Voltage (V)
C027
3.6
C028
AVDD = 1.8 V
Figure 28. AVDD Supply Current vs Throughput
Figure 29. AVDD Supply Current vs AVDD Voltage
100
Current (nA)
80
60
40
20
0
0
25
50
75
Free-Air Temperature (oC)
100
125
C029
Figure 30. AVDD Static Current vs Free-Air Temperature
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 31 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
-0.3V
VIL
DVDD = 1.65 V to 1.95 V
Figure 31. Digital Voltage Levels as per the JESD8-7A Standard
14
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8 Detailed Description
8.1 Overview
The ADS7044 is an ultralow-power, ultra-small analog-to-digital converter (ADC) that supports a wide analog
input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples
the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock
provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM
pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are
reconnected across the AINP and AINM pins and the device enters acquisition phase.
The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up
or during normal operation; see the Offset Calibration section for more details.
The device also provides a simple serial interface to the host controller and operates over a wide range of digital
power supplies. The device requires only a 16-MHz SCLK for supporting a throughput of 1 MSPS. The digital
interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram section
provides a block diagram of the device.
8.2 Functional Block Diagram
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
SCLK
Serial
Interface
AINM
SDO
SAR
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8.3 Feature Description
8.3.1 Reference
The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 32. TI recommends
decoupling the AVDD pin with a 1-µF, low equivalent series resistance (ESR) ceramic capacitor. The minimum
capacitor value required for AVDD is 200 nF. The AVDD pin functions as a switched capacitor load to the source
powering AVDD. The decoupling capacitor provides the instantaneous charge required by the internal circuit and
helps in maintaining a stable dc voltage on the AVDD pin. TI recommends powering the AVDD pin with a low
output impedance and low-noise regulator (such as the TPS79101).
1µF
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
SCLK
Serial
Interface
AINM
SDO
SAR
Figure 32. Reference for the Device
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Feature Description (continued)
8.3.2 Analog Input
The device supports differential analog inputs. The ADC samples the difference between AINP and AINM and
converts for this voltage. The device is capable of accepting a signal from 0 V to AVDD on the AINM input and a
signal from 0 V to AVDD on the AINP input. Figure 33 represents the equivalent analog input circuits for the
sampling stage. The device has a low-pass filter followed by the sampling switch and sampling capacitor. The
sampling switch is represented by an Rs (typically 50 Ω) resistor in series with an ideal switch and Cs (typically
15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD and ground.
AVDD
50
Rs
AINP
CS
10 pF
AVDD
50
Rs
AINM
CS
Figure 33. Equivalent Input Circuit for the Sampling Stage
The analog input full-scale range (FSR) is defined by the reference voltage of the ADC. The relationship between
the FSR and the reference voltage can be determined by: FSR = 2 × VREF = 2 × AVDD.
8.3.3 ADC Transfer Function
The device output is in twos compliment format. The device resolution can be computed by Equation 1:
1 LSB = FSR / 2N
where:
•
•
FSR = 2 × VREF = 2 × AVDD and
N = 12
(1)
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Feature Description (continued)
Figure 34 and Table 1 show the ideal transfer characteristics for the device.
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
-(VREF ± 1 LSB)
0 LSB
VIN
(VREF ± 1 LSB)
1 LSB
Analog Input
(AINP ± AINM)
Figure 34. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE (AINP-AINM)
CODE
DESCRIPTION
IDEAL OUTPUT CODE
≤ –(VREF – 1 LSB)
NFSC
Negative full-scale code
800
–(VREF – 1 LSB) to –(VREF – 2 LSBs)
NFSC + 1
—
801
0 to 1 LSB
MC
Mid code
000
1 LSB to 2 LSBs
MC + 1
—
001
≥VREF – 1 LSB
PFSC
Positive full-scale code
7FF
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8.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 35 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 12 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 14 SCLKs. A CS rising edge ends the frame and brings the serial data bus to 3-state. For the
acquisition of the next sample, a minimum time of tACQ must be provided after the conversion of the current
sample is completed. For details on timing specifications, see the Timing Characteristics table.
The device initiates offset calibration on first CS falling edge after power-up and the SDO output remains low
during the first serial transfer frame after power-up. For details, refer to the Offset Calibration section.
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
CS
SCLK
1
SDO
0
2
0
3
D11
4
5
6
7
8
9
10
11
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
13
D1
14
D0
Data for Sample N
Figure 35. Serial Interface Timing Diagram
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8.4 Device Functional Modes
8.4.1 Offset Calibration
The device includes a feature to calibrate its internal offset. The device initiates offset calibration on the first CS
falling edge after power up and during offset calibration, the analog input pins (AINP and AINM) are disconnected
from the sampling stage. After the first serial transfer frame, the device starts operating with either uncalibrated
or calibrated offset, depending on the number of SCLKs provided in the first serial transfer frame. Offset
calibration can also be initiated by the user during normal operation. Figure 36 shows the offset calibration
process. The SDO output remains low during the first serial transfer frame.
The device includes an internal offset calibration register (OCR) that stores the offset calibration result. The OCR
is an internal register and cannot be accessed by the user through the serial interface. The OCR is reset to zero
on power-up. Therefore, TI recommends calibrating the offset on power-up to bring the offset within the specified
limits. If there is a significant change in operating temperature or analog supply voltage, the offset can be
recalibrated during normal operation.
)
(4
le
yc
Po
rR
ec
th
Device
Power Up
Ca
lib
r
SDatio
O no
= nP
0x o
00 w e
0 rU
p
Data Capture(1)
Calibration during Normal operation(2)
wi
e
m
ra Ks
F
r
fe CL
ns S 0
ra 16 x00
lT n
ia tha = 0
r
e s O
t S les SD
rs
Fi
we
Normal Operation
With Uncalibarted
offset
(3
)
Po
:
we
rR
Data Capture(1)
ec
yc
le
(4
)
Normal Operation
With Calibarted
offset
Calibration during Normal Operation(2)
(1)
See the Timing Characteristics section for timing specifications.
(2)
See the Offset Calibration During Normal Operation section for details.
(3)
See the Offset Calibration on Power-Up section for details.
(4)
The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 36. Offset Calibration
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device starts offset calibration on the first CS falling edge after power-up and calibration completes if the CS
pin remains low for at least 16 SCLKs after the first CS falling edge. The SDO output remains low during
calibration. The minimum acquisition time must be provided after calibration for acquiring the first sample. If the
device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up, the OCR is not
updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 37
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
MIN
fCLK-CAL
SCLK frequency for calibration at 2.25 V < AVDD < 3.6 V
fCLK-CAL
SCLK frequency for calibration at 1.65 V < AVDD < 2.25 V
tPOWERUP-CAL
Calibration time at power-up
tACQ
tPH_CS
TYP
MAX
UNIT
16
MHz
12
MHz
16 tSCLK
ns
Acquisition time
200
ns
CS high time
tACQ
ns
Start
Power-up
Calibration
Sample
#1
tPH_CS
tPOWERUP-CAL
tACQ
CS
tD_CKCS
tSU_CSCK
SCLK(fCLK-CAL)
1
2
15
16
SDO
Figure 37. Offset Calibration on Power-Up Timing Diagram
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8.4.1.2 Offset Calibration During Normal Operation
The offset can also be calibrated during normal device operation. Offset calibration can be done during normal
device operation if at least 32 SCLKs are provided in one serial transfer frame. During the first 14 SCLKs, the
device converts the sample acquired on the CS falling edge and provides data on the SDO output. The device
initiates the offset calibration on the 17th SCLK falling edge and calibration is completed on the 32nd SCLK
falling edge. The SDO output remains low after the 14th SCLK falling edge and SDO goes to 3-state after CS
goes high. If the device is provided with less than 32 SCLKs during a serial transfer frame, the OCR is not
updated. Table 3 provides the timing parameters for offset calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in OCR. The conversion
result adjusted with the value stored in the OCR is provided by the device on the SDO output. Figure 38 shows
the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MAX
UNIT
fCLK-CAL
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
MIN
TYP
16
MHz
fCLK-CAL
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
12
MHz
tCAL
Calibration time during normal operation
16 tSCLK
ns
tACQ
Acquisition time
200
ns
tPH_CS
CS high time
tACQ
ns
Sample
N+1
Sample
N
tPH_CS
tCONV
tCAL
tACQ
CS
tSU_CSCK
tD_CKCS
SCLK(fCLK-CAL)
1
2
3
4
13
SDO
0
0
D11
D10
D1
14
15
16
17
18
31
32
D0
Data for Sample N
Figure 38. Offset Calibration During Normal Operation Timing Diagram
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing the input driver circuit, reference driver circuit, and provides
some application circuits designed for the ADS7044.
9.2 Typical Applications
9.2.1 Single-Supply DAQ with the ADS7044
R2
20 k
R1
20 k
AVDD
AVDD
+
OPA316
30
1 nF
AVDD
AINP
VIN
AVDD/2
Device
2.2 nF
R3
20 k
+
AVDD
OPA316
AINM
GND
30
1 nF
Device: 12-Bit, 1-MSPS
Differential Input
R4
20 k
Input Driver
Figure 39. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7044
with SNR greater than 71 dB and THD less than –85 dB for a differential input signal having an amplitude of
AVDD with a common-mode voltage of AVDD / 2 and input frequencies of 5 kHz at a throughput of
1 MSPS.
9.2.1.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an
antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
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Typical Applications (continued)
9.2.1.2.1 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the
Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and
folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing
filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An
antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise,
response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a highbandwidth filter is designed to allow the signal to be accurately set at the ADC inputs during the small acquisition
time window. Figure 40 provides the equation for determining the bandwidth of antialiasing filter.
AVDD
RFLT
f
1
3dB
AVDD
AINP
2Πu 2RFLT u CFLT
CFLT
Device
RFLT
AINM
GND
Figure 40. Antialiasing Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must be at least 20
times the specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is
equal to 15 pF. Thus, the value of CFLT must be greater than 300 pF. The capacitor must be a COG- or NPOtype because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical
characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly
recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with
the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers may
require more bandwidth than others to drive similar filters.
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Typical Applications (continued)
9.2.1.2.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be high enough to settle
the input signal in the acquisition time of the ADC. Higher bandwidth reduces the closed-loop output
impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter
at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In
order to maintain the overall stability of the input driver circuit, select the amplifier bandwidth as described in
Equation 2:
GBW t 4 u
1
2Πu 2R
FLT
u
C
FLT
where:
•
•
GBW = Unity-gain bandwidth
(2)
Noise: Noise contribution of the front-end amplifiers must be low enough to prevent any degradation in SNR
performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition
system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below
20% of the input-referred noise of the ADC. Noise from the input driver circuit is band limited by designing a
low cutoff frequency RC filter, as explained in Equation 3.
V1 f _AMP_PP 2 ª 2ue
«
6.6u2 E
¬«
2
n_RMS
2uin uE u R22 R42
2E
2u 4 kT u 1 E
2
2
u R1 R3
2
º Œ
4 kT R2 R4 »u uf
2
¼»
3dB
d
1 VREF
u
u 10
5
2
SNR(dB)
20
where:
•
•
•
•
•
•
•
•
V1/f_AMP_PP is the peak-to-peak flicker noise in µVrms,
en_RMS is the amplifier broadband noise,
f–3dB is the –3-dB bandwidth of the RC filter,
k is the Boltzmann's constant, and
T is absolute temperature in kelvin.
For symmetrical feedback, β = R1 / (R1 + R2) = R3 / (R3 + R4).
For details on noise analysis, refer to the technical brief Analysis of fully differential amplifiers (SLYT157)
(3)
Settling time: For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE
simulations before selecting the amplifier.
The OPA316 is selected for this application for its rail-to-rail input and output swing, low-noise (11 nV/√Hz), and
low-power (400 µA) performance to support a single-supply data acquisition circuit.
9.2.1.2.3 Reference Circuit
The analog supply voltage of the device is also used as a voltage reference for conversion. TI recommends
decoupling the AVDD pin with a 1-µF, low-ESR ceramic capacitor. The minimum capacitor value required for
AVDD is 200 nF.
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
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9.2.1.3 Application Curve
Figure 41 shows the FFT plot for the device with a 5-kHz input frequency for the circuit in Figure 39.
0
Signal Power (dB)
±20
±40
±60
±80
±100
±120
±140
±160
0
100
200
300
Input Frequency (kHz)
SNR = 72.2 dB
THD = –85.7 dB
400
500
C031
SINAD = 72 dB
Number of samples = 8192
Figure 41. Test Results for the ADS7044 and OPA316 for a 5-kHz Input
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9.2.2 Ultra-Low Power and Ultra-Small, High CMRR DAQ Circuit with the ADS7044
R2
20 k
AVDD
R1
20 k
AVDD
30
VIN-
1 nF
VOUT+
VIN
AVDD/2
VOCM
AVDD
AINP
THS4531A
Device
2.2 nF
VOUT-
AINM
GND
30
VIN+
1 nF
R3
20 k
Device: 12-Bit, 1-MSPS
Differential Input
R4
20 k
Input Driver
Figure 42. ADS7044 DAQ Circuit
9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 4 as input parameters.
Table 4. Design Parameters
DESIGN PARAMETER
GOAL VALUE
SINAD
71 dB
Throughput
1 MSPS
AVDD
3.3 V
AVDD current consumption
800 µA (at a 5-kHz fIN) and 1500 µA (at a 25-kHz fIN)
VIN to the THS4531A
–AVDD to AVDD
Common-mode voltage for VIN to the THS4531A
0 V to AVDD / 2
9.2.2.2 Detailed Design Procedure
See the Detailed Design Procedure section in the Single-Supply DAQ with the ADS7044 application for further
details.
To achieve a SINAD of 71 dB, the operational amplifier must have high bandwidth to settle the input signal within
the acquisition time of the ADC. The operational amplifier must have low noise to keep the total system noise
below 20% of the input-referred noise of the ADC.
For the application circuit shown in Figure 42, the THS4531A is selected for its high bandwidth (36 MHz), low
noise (10 nV/√Hz), and for its capability to set the common-mode voltage for the ADC. The THS4531A rejects
the variation of common-mode at its input and provides a CMRR of 90 dB (min).
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9.2.2.3 Application Curves
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
Figure 43 shows the FFT plot for the device with a 5-kHz input frequency for the circuit in Figure 42. Figure 44
shows the FFT plot for the device with a 25-kHz input frequency for the circuit in Figure 42.
±60
±80
±100
±80
±100
±120
±120
±140
±140
±160
±160
0
100
200
300
Input Frequency (kHz)
28
±60
400
500
0
100
200
300
Input Frequency (kHz)
C032
400
500
C033
SNR = 72.3 dB
THD = –87.8 dB
SINAD = 72.2 dB
AVDD current = 740 µA, Number of samples = 8192
SNR = 71.6 dB
THD = –85 dB
SINAD = 71.4 dB
AVDD current = 1375 µA, Number of samples = 8192
Figure 43. Test Results for the ADS7044 and THS4531A for
a 5-kHz Input
Figure 44. Test Results for the ADS7044 and THS4531A for
a 25-kHz Input
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10 Power-Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used
for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible ranges.
The AVDD supply also defines the full-scale input range of the device. Decouple the AVDD and DVDD pins
individually with 1-µF ceramic decoupling capacitors, as shown in Figure 45. The minimum capacitor value
required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies are powered from the same
source, a minimum capacitor value of 220 nF is required for decoupling.
AVDD
AVDD
1 PF
GND
1 PF
DVDD
DVDD
Figure 45. Power-Supply Decoupling
10.2 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO
line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on
every rising edge of the data output and is discharged on every falling edge of the data output. The current
consumed by the device from the DVDD supply can be calculated by Equation 4:
IDVDD = C × V × f
where:
•
•
•
C = Load capacitance on the SDO line,
V = DVDD supply voltage, and
f = Number of transitions on the SDO output.
(4)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on the SDO change on every SCLK. SDO changing on
every SCLK results in an output code of AAAh or 555h. For an output code of AAAh or 555h at a 1-MSPS
throughput, the frequency of transitions on the SDO output is 6 MHz.
To keep the current consumption at the lowest possible value, the DVDD supply must be kept at the lowest
permissible value and the capacitance on the SDO line must be kept as low as possible.
10.3 Optimizing Power Consumed by the Device
•
•
•
•
Keep the analog supply voltage (AVDD) as per the analog input full-scale range (FSR) requirement.
Keep the digital supply voltage (DVDD) at the lowest permissible value.
Reduce the load capacitance on the SDO output.
Run the device at optimum throughput. Power consumption reduces with throughput.
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11 Layout
11.1 Layout Guidelines
Figure 46 shows a board layout example for the ADS7044. Use a ground plane underneath the device and
partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and
keep the analog input signals and the reference input signals away from noise sources. In Figure 46, the analog
input and reference signals are routed on the top and left side of the device while the digital connections are
routed on the bottom and right side of the device.
The power sources to the device must be clean and well-bypassed. Use 1-μF ceramic bypass capacitors in close
proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and
DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance
paths. The AVDD supply voltage for the ADS7044 also functions as a reference for the device. Place the
decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins. CREF must be connected to the
device pins with thick copper tracks, as shown in Figure 46.
The fly-wheel RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG (NPO)
ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
11.2 Layout Example
Figure 46. Example Layout
30
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• OPA316 Data Sheet, SBOS703
• OPA835 Data Sheet, SLOS713
• THS4531A Data Sheet, SLOS823
• TPS79101 Data Sheet, SLVS325
• Analysis of fully differential amplifiers, SLYT157
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
TINA is a trademark of Texas Instruments, Inc.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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ADS7044
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PACKAGE OUTLINE
RUG0008A
X2QFN - 0.4 mm max height
SCALE 7.500
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00
0.08 C
SYMM
2X
0.35
0.25
2X
4
3
(0.15)
TYP
0.45
0.35
5
SYMM
2X
1
4X 0.5
2X
7
1
4X
8
PIN 1 ID
(45 X0.1)
6X
0.4
0.3
0.25
0.15
0.3
0.2
0.1
0.05
C A
C
B
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015
EXAMPLE BOARD LAYOUT
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP
4
SYMM
(1.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
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EXAMPLE STENCIL DESIGN
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
4
SYMM
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE:25X
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7044IDCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7044
ADS7044IDCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
7044
ADS7044IRUGR
ACTIVE
X2QFN
RUG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FX
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS7044IDCUR
VSSOP
DCU
8
ADS7044IDCUT
ADS7044IRUGR
VSSOP
DCU
X2QFN
RUG
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
8
3000
180.0
8.4
1.6
1.6
0.66
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7044IDCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
ADS7044IDCUT
VSSOP
DCU
8
250
202.0
201.0
28.0
ADS7044IRUGR
X2QFN
RUG
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
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