Low Capacitance, 4-/8-Channel, ±15 V/+12 V iCMOS Multiplexers ADG1208/ADG1209 FEATURES FUNCTIONAL BLOCK DIAGRAMS ADG1208 ADG1209 S1 S1A DA S4A D S1B DB S8 S4B 1-OF-8 DECODER 1-OF-4 DECODER A0 A1 A2 EN A0 APPLICATIONS A1 05713-001 <1 pC charge injection over full signal range 1 pF off capacitance 33 V supply range 120 Ω on resistance Fully specified at ±15 V/+12 V 3 V logic compatible inputs Rail-to-rail operation Break-before-make switching action Available in 16-lead TSSOP, 4 mm × 4 mm LFCSP_VQ, and 16-lead SOIC Typical power consumption < 0.03 μW EN Figure 1. Audio and video routing Automatic test equipment Data-acquisition systems Battery-powered systems Sample-and-hold systems Communication systems GENERAL DESCRIPTION 1.0 MUX (SOURCE TO DRAIN) 0.9 TA = 25°C 0.8 0.7 0.6 VDD = +15V VSS = –15V 0.5 0.4 0.3 VDD = +12V VSS = 0V 0.2 0.1 0 –15 VDD = +5V VSS = –5V –10 –5 0 VS (V) 5 10 15 05713-051 The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. CHARGE INJECTION (pC) The ADG1208 and ADG1209 are monolithic, iCMOS® analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1208 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG1209 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. Figure 2. Source to Drain Charge Injection vs. Source Voltage Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved. ADG1208/ADG1209 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ............................8 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Terminology .................................................................................... 14 Specifications..................................................................................... 3 Test Circuits ..................................................................................... 15 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 17 Single Supply ................................................................................. 5 Ordering Guide .......................................................................... 18 REVISION HISTORY 1/09—Rev. A to Rev. B Change to IDD Parameter, Table 1 ................................................... 4 Change to IDD Parameter, Table 2 ................................................... 6 4/07—Rev. 0 to Rev. A Added 16-lead SOIC .......................................................... Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Figure 10 and Figure 11 ............................................. 10 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 4/06—Revision 0: Initial Version Rev. B | Page 2 of 20 ADG1208/ADG1209 SPECIFICATIONS DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. 1 Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG1208 ADG1209 Channel On Leakage, ID, IS (On) ADG1208 ADG1209 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH +25ºC −40ºC to +85ºC −40ºC to +125ºC VSS to VDD 120 200 3.5 6 20 64 ±0.003 ±0.1 ±0.003 ±0.1 ±0.1 ±0.02 ±0.2 ±0.2 240 270 10 12 76 83 ±0.6 ±1 ±0.6 ±0.6 ±1 ±1 ±0.6 ±0.6 ±1 ±1 2.0 0.8 ±0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION 2 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA max nA typ nA max nA max V min V max μA max μA max pF typ Break-Before-Make Time Delay, tBBM 80 130 75 95 83 100 25 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise 0.4 −85 −85 0.15 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ −3 dB Bandwidth CS (Off ) 550 1 1.5 6 7 3.5 4.5 MHz typ pF typ pF max pF typ pF max pF typ pF max tON (EN) tOFF (EN) 165 185 105 115 125 140 10 CD (Off ) ADG1208 CD (Off ) ADG1209 Rev. B | Page 3 of 20 Test Conditions/Comments VS = ±10 V, IS = −1 mA, see Figure 29 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −1 mA VS = −5 V/0 V/+5 V, IS = −1 mA VD = ±10 V, VS = −10 V, see Figure 30 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 VS = VD = ±10 V, see Figure 31 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 34 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V, see Figure 33 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38 RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz, see Figure 39 RL = 50 Ω, CL = 5 pF, see Figure 37 f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V ADG1208/ADG1209 Parameter CD, CS (On) ADG1208 CD, CS (On) ADG1209 POWER REQUIREMENTS IDD +25ºC 7 8 5 6 −40ºC to +85ºC −40ºC to +125ºC 0.002 1.0 IDD 220 380 ISS 0.002 1.0 ISS 0.002 VDD/VSS 1 2 1.0 ±5/±16.5 Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design, not subject to production test. Rev. B | Page 4 of 20 Unit pF typ pF max pF typ pF max μA typ μA max μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V or VDD Digital inputs = 5 V |VDD | = |VSS| ADG1208/ADG1209 SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. 1 Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG1208 ADG1209 Channel On Leakage ID, IS (On) ADG1208 ADG1209 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM +25ºC −40ºC to +85ºC −40ºC to +125ºC 0 to VDD 300 475 5 16 60 ±0.003 ±0.1 ±0.003 ±0.1 ±0.1 ±0.02 ±0.2 ±0.2 567 625 26 27 CD (Off ) ADG1208 CD (Off ) ADG1209 CD, CS (On) ADG1208 CD, CS (On) ADG1209 V Ω typ Ω max Ω typ Ω max Ω typ Test Conditions/Comments VS = 0 V to 10 V, IS = −1 mA, see Figure 29 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −1 mA VS = 3 V/6 V/9 V, IS = −1 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 ±0.6 ±1 ±0.6 ±0.6 ±1 ±1 ±0.6 ±0.6 ±1 ±1 nA typ nA max nA typ nA max nA max nA typ nA max nA max 2.0 0.8 V min V max ±0.1 μA max pF typ VIN = VINL or VINH ns typ RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 34 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 34 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V, see Figure 33 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 35 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38 RL = 50 Ω, CL = 5 pF, see Figure 37 f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30 VS = VD = 1 V or 10 V, see Figure 31 ±0.001 3 100 170 90 110 105 130 45 210 235 140 160 155 175 ns typ ns typ 20 Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth CS (Off ) Unit −0.2 −85 −85 450 1.2 1.8 7.5 9 4.5 5.5 9 10.5 6 7.5 Rev. B | Page 5 of 20 ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max pF typ pF max pF typ pF max ADG1208/ADG1209 Parameter POWER REQUIREMENTS IDD +25ºC −40ºC to +85ºC −40ºC to +125ºC 0.002 1.0 IDD 220 VDD 1 2 380 5/16.5 Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design, not subject to production test. Rev. B | Page 6 of 20 Unit μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1208/ADG1209 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs 1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Industrial (Y Version) Storage Temperature Junction Temperature θJA, Thermal Impedance, TSSOP θJA, Thermal Impedance, LFCSP_VQ θJA, Thermal Impedance, SOIC_N Reflow Soldering Peak Temperature (Pb-Free) 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) 30 mA 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION –40°C to +125°C –65°C to +150°C 150°C 112°C/W 30.4°C/W 77°C/W 260(+0/−5)°C Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 7 of 20 ADG1208/ADG1209 A2 ADG1208 14 GND TOP VIEW (Not to Scale) 13 S1 2 ADG1208 12 S5 S2 3 S3 6 11 S6 TOP VIEW (Not to Scale) S4 7 10 S7 D 8 9 S8 S4 5 S3 4 05713-002 S2 5 S7 8 VDD S1 4 S8 7 PIN 1 INDICATOR 3 D 6 VSS 1 VSS 12 GND 11 VDD 10 S5 9 S6 05713-004 A1 13 A2 16 15 14 A1 16 EN A0 1 EN 2 15 A0 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADG1208 Pin Configuration (LFCSP_VQ), Exposed Pad Tied to Substrate, VSS Figure 3. ADG1208 Pin Configuration (TSSOP/SOIC) Table 4. ADG1208 Pin Function Descriptions Pin Number TSSOP/SOIC LFCSP_VQ 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Drain Terminal. Can be an input or an output. Source Terminal 8. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 5. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Table 5. ADG1208 Truth Table A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 Rev. B | Page 8 of 20 On Switch None 1 2 3 4 5 6 7 8 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 S2A 5 DB VSS 1 PIN 1 INDICATOR S1A 2 ADG1209 11 S1B S2A 3 TOP VIEW (Not to Scale) 10 S2B S3A 4 Figure 5. ADG1209 Pin Configuration (TSSOP/SOIC) 12 VDD 9 S3B 05713-005 S1B 14 A1 13 13 GND TOP VIEW (Not to Scale) S4B 8 VDD S1A 4 15 A0 ADG1209 14 DB 7 GND VSS 3 DA 6 A1 S4A 5 16 15 05713-003 A0 1 EN 2 16 EN ADG1208/ADG1209 Figure 6. ADG1209 Pin Configurations (LFCSP_VQ), Exposed Pad Tied to Substrate, VSS Table 6. ADG1209 Pin Function Descriptions Pin Number TSSOP/SOIC LFCSP_VQ 1 15 2 16 Mnemonic A0 EN 3 1 VSS 4 5 6 7 8 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 10 11 12 13 14 S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Drain Terminal A. Can be an input or an output. Drain Terminal B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Table 7. ADG1209 Truth Table A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4 Rev. B | Page 9 of 20 ADG1208/ADG1209 TYPICAL PERFORMANCE CHARACTERISTICS 250 200 TA = 25°C 180 VDD = +13.5V VSS = –13.5V 200 TA = +125°C 140 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 160 VDD = +15V VSS = –15V VDD = +15V VSS = –15V 120 VDD = +16.5V VSS = –16.5V 100 80 60 TA = +85°C 150 TA = +25°C 100 TA = –40°C 50 40 –9 –6 –3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18 0 –15 05713-030 0 –18 –15 –12 10 600 600 TA = 25°C VDD = +4.5V VSS = –4.5V 500 500 VDD = +5V VSS = –5V 400 VDD = +5.5V VSS = –5.5V 300 15 VDD = 12V VSS = 0V TA = +125°C ON RESISTANCE (Ω) 200 TA = +85°C 400 TA = +25°C 300 TA = –40°C 200 –6 –4 –2 0 2 SOURCE OR DRAIN VOLTAGE (V) 4 6 0 05713-031 0 0 2 4 6 8 SOURCE OR DRAIN VOLTAGE (V) 10 12 05713-034 100 100 Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 8. On Resistance as a Function of VD (VS) for Dual Supply 400 450 TA = 25°C 400 VDD = 10.8V VSS = 0V 350 LEAKAGE CURRENT (pA) VDD = 12V VSS = 0V 300 250 VDD = 13.2V VSS = 0V 200 VDD = +15V VSS = –15V VBIAS = +10V/–10V 300 150 100 ID, S (ON) + + 200 ID (OFF) + – 100 IS (OFF) + – 0 ID, S (ON) – – –100 ID (OFF) – + –200 IS (OFF) – + –300 50 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 14 Figure 9. On Resistance as a Function of VD (VS) for Single Supply –400 05713-032 0 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 100 110 120 05713-057 ON RESISTANCE (Ω) –5 0 5 SOURCE OR DRAIN VOLTAGE (V) Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply Figure 7. On Resistance as a Function of VD (VS) for Dual Supply ON RESISTANCE (Ω) –10 05713-033 20 Figure 12. ADG1208 Leakage Currents as a Function of Temperature, Dual Supply Rev. B | Page 10 of 20 ADG1208/ADG1209 150 6 VDD = 12V VSS = 0V VBIAS = 1V/10V 4 IS (OFF) + – CHARGE INJECTION (pC) ID, S (ON) + + 50 ID (OFF) + – 0 IS (OFF) – + ID, S (ON) – – –50 ID (OFF) – + –100 2 0 VDD = +12V VSS = 0V VDD = +15V VSS = –15V –2 –4 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 100 110 120 –6 –15 05713-058 –150 VDD = +5V VSS = –5V Figure 13. ADG1208 Leakage Currents as a Function of Temperature, Single Supply –10 –5 0 VS (V) 5 10 15 05713-041 LEAKAGE CURRENT (pA) 100 DEMUX (DRAIN TO SOURCE) TA = 25°C Figure 16. Drain-to-Source Charge Injection vs. Source Voltage 350 200 IDD PER CHANNEL TA = 25°C 180 300 160 VDD = +15V VSS = –15V VDD = +5V VSS = –5V 250 120 TIME (ns) IDD (µA) 140 100 80 60 200 VDD = +12V VSS = 0V 150 VDD = +15V VSS = –15V 100 40 2 4 6 8 10 LOGIC, INX (V) 12 14 16 0 –40 20 40 60 TEMPERATURE (°C) 80 100 120 0 1.0 MUX (SOURCE TO DRAIN) 0.9 TA = 25°C –10 0.8 –20 OFF ISOLATION (dB) 0.7 0.6 VDD = +15V VSS = –15V 0.5 0.4 0.3 VDD = +12V VSS = 0V 0.2 VDD = +15V VSS = –15V TA = 25°C –30 –40 –50 –60 –70 –80 –90 0.1 VDD = +5V VSS = –5V –10 –5 0 VS (V) –100 5 10 15 05713-040 CHARGE INJECTION (pC) 0 Figure 17. tON/tOFF Times vs. Temperature Figure 14. IDD vs. Logic Level 0 –15 –20 –110 10k 100k 1M 10M FREQUENCY (Hz) 100M Figure 18. Off Isolation vs. Frequency Figure 15. Source-to-Drain Charge Injection vs. Source Voltage Rev. B | Page 11 of 20 1G 05713-049 0 05713-035 0 05713-052 50 VDD = +12V VSS = 0V 20 ADG1208/ADG1209 20 10 VDD = +15V VSS = –15V 0 TA = 25°C LOAD = 10kΩ TA = 25°C 1 THD + N (%) CROSSTALK (dB) –20 –40 ADJACENT CHANNELS –60 VDD = +15V, VSS = –15V, VS = +5Vrms 0.1 NONADJACENT CHANNELS –80 VDD = +5V, VSS = –5V, VS = +3.5Vrms 100k 1M 10M FREQUENCY (Hz) 100M 1G 0.01 10 05713-042 –120 10k 100 Figure 19. ADG1208 Crosstalk vs. Frequency 12 –20 100k VDD = +15V VSS = –15V TA = 25°C 10 CAPACITANCE (pF) CROSSTALK (dB) 10k Figure 22. THD + N vs. Frequency 0 –40 –60 1k FREQUENCY (Hz) 05713-036 –100 ADJACENT CHANNELS –80 –100 8 SOURCE/DRAIN ON 6 DRAIN OFF 4 2 SOURCE OFF 100k 1M 10M FREQUENCY (Hz) 100M 1G 0 –15 05713-053 –120 10k –10 –5 5 10 15 Figure 23. ADG1208 Capacitance vs. Source Voltage, ±15 V Dual Supply Figure 20. ADG1209 Crosstalk vs. Frequency –6.0 12 –6.5 VDD = 12V VSS = 0V TA = 25°C 10 SOURCE/DRAIN ON CAPACITANCE (pF) –7.0 –7.5 –8.0 –8.5 8 DRAIN OFF 6 4 –9.0 100k 1M 10M FREQUENCY (Hz) 100M 1G 0 0 2 4 6 VBIAS (V) 8 10 Figure 24. ADG1208 Capacitance vs. Source Voltage, 12 V Single Supply Figure 21. On Response vs. Frequency Rev. B | Page 12 of 20 12 05713-045 –10.0 10k SOURCE OFF 2 –9.5 05713-054 ON RESPONSE (dB) 0 VBIAS (V) 05713-043 NONADJACENT CHANNELS ADG1208/ADG1209 12 8 VDD = 12V VSS = 0V TA = 25°C 7 SOURCE/DRAIN ON DRAIN OFF VDD = +5V VSS = –5V TA = 25°C 4 SOURCE/DRAIN ON 5 DRAIN OFF 4 3 2 2 1 SOURCE OFF –4 –3 –2 –1 0 1 2 3 4 5 VBIAS (V) Figure 25. ADG1208 Capacitance vs. Source Voltage, ±5 V Dual Supply 0 2 4 6 VBIAS (V) 12 10 Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply VDD = +15V VSS = –15V TA = 25°C 7 6 7 SOURCE/DRAIN ON 6 CAPACITANCE (pF) SOURCE/DRAIN ON 5 4 DRAIN OFF 3 5 4 3 DRAIN OFF VDD = +5V VSS = –5V TA = 25°C 2 2 SOURCE OFF SOURCE OFF 1 1 –10 –5 0 VBIAS (V) 5 10 15 0 –5 05713-046 0 –15 8 8 8 CAPACITANCE (pF) 0 05713-055 0 –5 SOURCE OFF Figure 26. ADG1209 Capacitance vs. Source Voltage, ±15 V Dual Supply –4 –3 –2 –1 0 1 VBIAS (V) 2 3 4 5 05713-056 6 CAPACITANCE (pF) CAPACITANCE (pF) 6 8 05713-047 10 Figure 28. ADG1209 Capacitance vs. Source Voltage, ±5 V Dual Supply Rev. B | Page 13 of 20 ADG1208/ADG1209 TERMINOLOGY tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. RON Ohmic resistance between D and S. ΔRON Difference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. ID (Off) Drain leakage current when the switch is off. VINL Maximum input voltage for Logic 0. ID, IS (On) Channel leakage current when the switch is on. VINH Minimum input voltage for Logic 1. VD (VS) Analog voltage on Terminal D, Terminal S. IINL (IINH) Input current of the digital input. CS (Off) Channel input capacitance for off condition. IDD Positive supply current. CD (Off) Channel output capacitance for off condition. ISS Negative supply current. CD, CS (On) On switch capacitance. Off Isolation A measure of unwanted signal coupling through an off channel. CIN Digital input capacitance. tON (EN) Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Delay time between the 50% and 90% points of the digital input and switch on condition. Bandwidth The frequency at which the output is attenuated by 3 dB. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. On Response The frequency response of the on switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. B | Page 14 of 20 ADG1208/ADG1209 TEST CIRCUITS V D IDS ID (ON) ID (OFF) A NC VD Figure 29. On Resistance 50% 50% S D A VD NC = NO CONNECT Figure 30. Off Leakage 3V ADDRESS DRIVE (VIN) D VS 05713-037 VS S Figure 31. On Leakage tr < 20ns tf < 20ns VDD VSS VDD VSS A0 0V VIN S1 A1 50Ω S2–S7 A2 tTRANSITION VS1 tTRANSITION VS8 S8 ADG12081 90% 2.4V OUTPUT OUTPUT D EN 300Ω GND 35pF 05713-022 90% 1SIMILAR CONNECTION FOR ADG1209. Figure 32. Address to Output Switching Times, tTRANSITION 3V ADDRESS DRIVE (VIN) VDD VSS VDD VSS A0 VIN 0V S1 A1 50Ω VS S2–S7 A2 S8 80% ADG12081 80% OUTPUT 2.4V OUTPUT D EN 300Ω GND 35pF 05713-023 tBBM 1SIMILAR CONNECTION FOR ADG1209. Figure 33. Break-Before-Make Delay, tBBM 3V 50% VDD VSS A0 50% S1 A1 0V ADG12081 tOFF (EN) 0.9VO 0.9VO 50Ω 1SIMILAR Figure 34. Enable Delay, tON (EN), tOFF (EN) Rev. B | Page 15 of 20 OUTPUT D EN VIN VS S2–S8 A2 tON (EN) OUTPUT VSS GND 300Ω CONNECTION FOR ADG1209. 35pF 05713-024 ENABLE DRIVE (VIN) VDD 05713-039 S A 05713-038 IS (OFF) ADG1208/ADG1209 3V VDD VSS VDD VSS A0 A1 VIN A2 ADG12081 VOUT RS ΔVOUT S D VOUT EN VS QINJ = CL × ΔVOUT CL 1nF GND 05713-025 VIN 1SIMILAR CONNECTION FOR ADG1209. Figure 35. Charge Injection VDD VSS VDD NETWORK ANALYZER NETWORK ANALYZER VSS S VOUT 0.1µF VDD D VS S2 D GND VOUT R 50Ω VS GND OFF ISOLATION = 20 log VOUT VS 05713-026 RL 50Ω VSS S1 RL 50Ω 50Ω 50Ω CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT VS Figure 38. Channel-to-Channel Crosstalk Figure 36. Off Isolation VDD VSS 0.1µF 0.1µF 05713-028 VDD 0.1µF VSS 0.1µF VDD VDD VSS S S D IN VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH VS V p-p D VIN 05713-027 INSERTION LOSS = 20 log AUDIO PRECISION VSS RS VS GND 0.1µF VDD 50Ω RL 50Ω VSS 0.1µF NETWORK ANALYZER GND RL 10kΩ Figure 39. THD + Noise Figure 37. Bandwidth Rev. B | Page 16 of 20 VOUT 05713-029 0.1µF ADG1208/ADG1209 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC 0.20 0.09 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ PIN 1 INDICATOR (BOTTOM VIEW) 13 12 0.65 BSC TOP VIEW 3.75 BSC SQ 0.75 0.60 0.50 9 8 16 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 5 4 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM 0.35 0.30 0.25 SEATING PLANE 0.20 REF COPLANARITY 0.08 021207-A 1.00 0.85 0.80 0.60 MAX 0.60 MAX COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) Figure 42. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. B | Page 17 of 20 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. ADG1208/ADG1209 ORDERING GUIDE Model ADG1208YRUZ1 ADG1208YRUZ-REEL71 ADG1208YCPZ-REEL1 ADG1208YCPZ-REEL71 ADG1208YRZ1 ADG1208YRZ-REEL71 ADG1209YRUZ1 ADG1209YRUZ-REEL71 ADG1209YCPZ-REEL1 ADG1209YCPZ-REEL71 ADG1209YRZ1 ADG1209YRZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Narrow Body Small Outline Package [SOIC_N] 16-Lead Narrow Body Small Outline Package [SOIC_N] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Narrow Body Small Outline Package [SOIC_N] 16-Lead Narrow Body Small Outline Package [SOIC_N] Z = RoHS compliant part. Rev. B | Page 18 of 20 Package Option RU-16 RU-16 CP-16-4 CP-16-4 R-16 R-16 RU-16 RU-16 CP-16-4 CP-16-4 R-16 R-16 ADG1208/ADG1209 NOTES Rev. B | Page 19 of 20 ADG1208/ADG1209 NOTES ©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05713-0-1/09(B) Rev. B | Page 20 of 20