ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS84320I-01 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL HiPerClockS™ High Frequency Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS84320I-01 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS84320I-01 make it an ideal clock source for 10 Gigabit Ethernet, SONET, and Serial Attached SCSI applications. • Dual differential 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 77.5MHz to 780MHz • Crystal input frequency range: 14MHz to 40MHz • VCO range: 620MHz to 780MHz • Parallel or serial interface for programming counter and output dividers • Duty cycle: 44% - 56% (N > 1) • RMS period jitter: 2.0ps (typical) • RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.38ps (typical) • RMS phase noise at 155.52MHz (typical) Offset Noise Power 100Hz ................ -90.5 dBc/Hz 1kHz ............... -114.2 dBc/Hz 10kHz ............... -123.6 dBc/Hz 100kHz ............... -128.1 dBc/Hz • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Available in both, Standard and RoHS/Lead-Free compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL XTAL_SEL XTAL_IN M0 M1 M2 M3 1 M4 OSC nP_LOAD 0 XTAL_IN VCO_SEL TEST_CLK XTAL_OUT 32 31 30 29 28 27 26 25 PLL PHASE DETECTOR MR VCO ÷M 1 FOUT0 nFOUT0 FOUT1 nFOUT1 CONFIGURATION INTERFACE LOGIC 1 24 XTAL_OUT M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR ICS84320I-01 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 9 10 11 12 13 14 15 16 TEST VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 M0:M8 VCC TEST S_LOAD S_DATA S_CLOCK nP_LOAD 0 ÷N ÷1 ÷2 ÷4 ÷8 M5 N0:N1 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84320AYI-01 www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. matically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relation-ship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS84320I-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 25 ≤ M ≤ 31. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84320I-01 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will auto- T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t H nP_LOAD t S PARALLEL LOADING M, N M0:M8, N0:N1 nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 84320AYI-01 www.icst.com/products/hiperclocks.html 2 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 2, 3, 4, 28, 29, 30, 31, 32 M5 M6, M7, M8, M0, M1, M2, M3, M4 5, 6 Type Input Description Pullup Input M divider inputs. Data latched on LOW-to-HIGH transition of Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. 7 nc Unused 8, 16 VEE Power 9 TEST Output 10 VCC Power Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power 22 XTAL_SEL Input Pullup 23 TEST_CLK XTAL_OUT, XTAL_IN Input Pulldown 26 nP_LOAD Input Pulldown 27 VCO_SEL Input Pullup Differential output for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, forces the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between cr ystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. 24, 25 Input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 84320AYI-01 www.icst.com/products/hiperclocks.html 3 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 25 0 0 0 0 1 1 0 0 1 • • • • • • • • • • 700 28 0 0 0 0 1 1 1 0 0 • • • • • • • • • • • VCO Frequency (MHz) M Divide 625 • 775 31 0 0 0 0 1 1 1 1 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz. 1 TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N1 N0 0 0 N Divider Value Output Frequency (MHz) Minimum Maximum 1 62 0 780 0 1 2 310 390 1 0 4 155 195 1 1 8 77.5 97.5 84320AYI-01 www.icst.com/products/hiperclocks.html 4 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 155 mA ICCA Analog Supply Current 22 mA Maximum Units 2 VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Test Conditions VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL IIL Input Low Current Minimum Typical M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VCC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2. 6 V VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO/2. 84320AYI-01 www.icst.com/products/hiperclocks.html 5 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter V OH Output High Voltage; NOTE 1 V OL Output Low Voltage; NOTE 1 Test Conditions Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 1.0 V Maximum Units VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit". TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical TEST_CLK; NOTE 1 14 40 MHz XTAL_IN, XTAL_OUT; fIN Input Frequency 14 40 MHz NOTE 1 S_CLOCK 50 MHz NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 ≤ M ≤ 55. Using the maximum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 40 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW 84320AYI-01 14 www.icst.com/products/hiperclocks.html 6 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions FOUT Output Frequency t jit(per) Period Jitter, RMS; NOTE 1 t sk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time tS tH Setup Time Hold Time Minimum Typical 77.5 fOUT > 100MHz 20% to 80% 2.0 100 Units 780 MHz 2.6 ps 15 ps 700 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns o dc Output Duty Cycle tPW Output Pulse Width N>1 49 51 % fOUT ≤ 625 44 56 % ƒ > 625 tPERIOD/2 - 150 tPERIOD/2 + 150 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 84320AYI-01 Maximum www.icst.com/products/hiperclocks.html 7 1 ps ms REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 155.52MHZ ➤ 0 -10 -20 OC-48 Sonet Bandpass Filter -30 -40 155.52MHz -50 RMS Phase Jitter (Random) 12kHz to 20MHz = 2.38ps (typical) Raw Phase Noise Data -70 ➤ -80 -90 -100 -110 -120 ➤ NOISE POWER dBc Hz -60 -130 -140 Phase Noise Result by adding Sonet Bandpass Filter to raw data -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 622.08MHZ ➤ 0 -10 -20 OC-48 Sonet Bandpass Filter -30 -40 622.08MHz -50 RMS Phase Jitter (Random) 12kHz to 20MHz = 2.48ps (typical) Raw Phase Noise Data -70 -80 -90 -100 -110 ➤ NOISE POWER dBc Hz ➤ -60 -120 -130 Phase Noise Result by adding Sonet Bandpass Filter to raw data -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 84320AYI-01 www.icst.com/products/hiperclocks.html 8 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V V CC , VCCA, VCCO Qx SCOPE nFOUTx FOUTx LVPECL nFOUTy nQx VEE FOUTy tsk(o) -1.3V ± 0.165V OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT VOH nFOUTx FOUTx VREF t PW t VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements odc = PERIOD t PW x 100% t PERIOD Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) PERIOD JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Phase Noise Plot Noise Power 80% 80% VSW I N G Clock Outputs Phase Noise Mask f1 Offset Frequency 20% 20% tR tF f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT RISE/FALL TIME RMS PHASE JITTER 84320AYI-01 www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84320I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 24Ω V CCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 84320AYI-01 www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3. A crystal can be characterized for either series or parallel mode operation. The ICS84320I-01 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy XTAL_OUT C1 18p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 3. CRYSTAL INPUt INTERFACE TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 84320AYI-01 FIN 50Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS84320I-01 layout example used in this layout guideline is shown in Figure 5A. The ICS84320I-01 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. C1 C2 M5 M6 M7 M8 N0 N1 nc VEE VCC ICS84320i-01 X_OUT T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE 1 2 3 4 5 6 7 8 9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16 U1 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN 32 31 30 29 28 27 26 25 X1 VCC 24 23 22 21 20 19 18 17 R7 10 REF_IN XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK C11 0.01u C16 10u VCC R1 125 R3 125 Zo = 50 Ohm C14 0.1u TL1 C15 0.1u + Zo = 50 Ohm - nTL1 VCC=3.3V R2 84 R4 84 FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT 84320AYI-01 www.icst.com/products/hiperclocks.html 12 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 25 (XTAL_IN) and 24 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. GND X1 C1 C2 VCC VIA U1 PIN 1 C16 C11 VCCA R7 Close to the input pins of the receiver TL1N C15 TL1 C14 TL1 R1 R2 TL1N R3 R4 TL1, TL21N are 50 Ohm traces and equal length FIGURE 5B. PCB BOARD LAYOUT FOR ICS84320I-01 84320AYI-01 www.icst.com/products/hiperclocks.html 13 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84320I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84320I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.08mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 537.08mW + 60mW = 597.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.597W * 42.1°C/W = 110.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84320AYI-01 www.icst.com/products/hiperclocks.html 14 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω) * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84320AYI-01 www.icst.com/products/hiperclocks.html 15 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84320I-01 is: 3776 84320AYI-01 www.icst.com/products/hiperclocks.html 16 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.75 L 0.45 0.60 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 84320AYI-01 www.icst.com/products/hiperclocks.html 17 REV. A AUGUST 11, 2005 ICS84320I-01 Integrated Circuit Systems, Inc. 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS84320AYI-01 ICS84320AI01 32 Lead LQFP tray -40°C to 85°C ICS84320AYI-01T ICS84320AI01 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS84320AYI-01LF TBD 32 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS84320AYI-01LFT TBD 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84320AYI-01 www.icst.com/products/hiperclocks.html 18 REV. A AUGUST 11, 2005