ICSI IC61LV25616-10K 256k x 16 high speed asynchronous cmos static ram with 3.3v supply Datasheet

IC61LV25616
Document Title
256K x 16 Hight Speed SRAM with 3.3V
1
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 11,2001
2
3
4
5
6
7
8
9
10
11
12
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
1
IC61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
•
•
•
•
•
High-speed access time: 8, 10, 12, and 15 ns
CMOS low power operation
TTL compatible interface levels
Single 3.3V ± 10% power supply
Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
DESCRIPTION
The ICSI IC61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC61LV25616 is packaged in the JEDEC standard
44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TFBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
IC61LV25616
PIN CONFIGURATIONS
44-Pin TSOP-2 and SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
48-Pin TF-BGA
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
N/C
B
I/O0
UB
A3
A4
CE
I/O8
C
I/O1
I/O2
A5
A6
I/O10
I/O9
D
GND
I/O3
A17
A7
I/O11
Vcc
E
Vcc
I/O4
NC
A16
I/O12
GND
F
I/O6
I/O5
A14
A15
I/O13
I/O14
G
I/O7
NC
A12
A13
WE
I/O15
H
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
PIN DESCRIPTIONS
A0-A17
Address Inputs
LB
Lower-byte Control (I/O0-I/O7)
I/O0-I/O15
Data Inputs/Outputs
UB
Upper-byte Control (I/O8-I/O15)
CE
Chip Enable Input
NC
No Connection
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
GND
Ground
8
9
10
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
CE
OE
LB
UB
X
H
X
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
11
ISB1, ISB2
ICC
12
ICC
ICC
3
IC61LV25616
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
VCC
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc+0.5
–45 to +90
–0.3 to +4.0
–65 to +150
1.0
Unit
V
°C
V
°C
W
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these
or any other conditions above those
indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
–0.3
0.8
V
Voltage(1)
VIL
Input LOW
ILI
Input Leakage
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC
Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
350
360
—
—
320
330
—
—
290
300
—
—
260
270
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
—
—
55
65
—
—
55
65
—
—
55
65
—
—
55
65
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CE ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
—
—
10
15
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
IC61LV25616
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
1
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol
Parameter
Min.
Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
Unit
tRC
Read Cycle Time
8
—
10
—
12
—
15
—
ns
tAA
Address Access Time
—
8
—
10
—
12
—
15
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE
CE Access Time
—
8
—
10
—
12
—
15
ns
tDOE
OE Access Time
—
4
—
5
—
6
—
7
ns
tHZOE(2) OE to High-Z Output
0
4
—
5
—
6
0
6
ns
(2)
tLZOE
OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHZCE(2
CE to High-Z Output
0
4
0
5
0
6
0
6
ns
tLZCE(2) CE to Low-Z Output
3
—
3
—
3
—
3
—
ns
tBA
LB, UB Access Time
—
4
—
5
—
6
—
7
ns
tHZB
LB, UB to High-Z Output
0
4
0
5
0
6
0
6
ns
tLZB
LB, UB to Low-Z Output
0
—
0
—
0
—
0
—
ns
3
4
5
6
7
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
8
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
9
10
See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
11
319 Ω
319 Ω
3.3V
353 Ω
5 pF
Including
jig and
scope
12
353 Ω
Figure 2
5
IC61LV25616
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CE
tACE
tHZCE
tLZCE
LB, UB
tBA
DOUT
HIGH-Z
tHZB
tLZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
IC61LV25616
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
Symbol
Parameter
Min.
Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
1
Unit
tWC
Write Cycle Time
8
—
10
—
12
—
15
—
ns
tSCE
CE to Write End
7
—
8
—
9
—
10
—
ns
tAW
Address Setup Time
to Write End
7
—
8
—
9
—
10
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
7
—
8
—
9
—
10
—
ns
tPWE
WE Pulse Width
7
—
8
—
9
—
10
—
ns
tSD
Data Setup to Write End
4.5
—
5
—
6
—
7
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
tHZWE(2) WE LOW to High-Z Output
—
4
—
5
—
6
—
7
ns
tLZWE(2) WE HIGH to Low-Z Output
3
—
3
—
3
—
3
—
ns
2
3
4
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
5
6
7
8
9
10
11
12
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
7
IC61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PWB
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
IC61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
1
t WC
ADDRESS
VALID ADDRESS
2
t HA
OE
CE
3
LOW
t AW
t PWE1
WE
t SA
4
t PWB
UB, LB
t HZWE
DOUT
t LZWE
5
HIGH-Z
DATA UNDEFINED
t SD
t HD
6
DATAIN VALID
DIN
7
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
8
VALID ADDRESS
OE
LOW
CE
LOW
t HA
9
t AW
10
t PWE2
WE
t SA
t PWB
11
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
12
t SD
DIN
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
t HD
DATAIN VALID
9
IC61LV25616
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PWB
t PWB
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
IC61LV25616
1
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
Speed (ns)
8
IC61LV25616-8T
IC61LV25616-8K
IC61LV25616-8B
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
10
IC61LV25616-10T
IC61LV25616-10K
IC61LV25616-10B
12
15
Order Part No.
Package
8
IC61LV25616-8TI
IC61LV25616-8KI
IC61LV25616-8BI
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
10
IC61LV25616-10TI
IC61LV25616-10KI
IC61LV25616-10BI
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
IC61LV25616-12T
IC61LV25616-12K
IC61LV25616-12B
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
12
IC61LV25616-12TI
IC61LV25616-12KI
IC61LV25616-12BI
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
IC61LV25616-15T
IC61LV25616-15K
IC61LV25616-15B
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
15
IC61LV25616-15TI
IC61LV25616-15KI
IC61LV25616-15BI
400mil TSOP-2
400mil SOJ
6*8mm TF-BGA
2
3
4
5
6
7
8
9
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
AHSR022-0A 09/11/2001
11
10
11
12
Similar pages