IXYS CPC7220K Low charge injection, 8-channel high voltage analog switch Datasheet

CPC7220
Low Charge Injection, 8-Channel
High Voltage Analog Switch
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Features
Description
• Processed with BCDMOS on SOI (Silicon On
Insulator)
• Flexible High Voltage Supplies up to VPP-VNN=200V
• DC to 10MHz Analog Signal Frequency
• -60dB Minimum Output-Off Isolation at 5MHz
• Low Quiescent Power Dissipation (< 1A typical)
• Output On-Resistance Typically 20
• TTL I/O's for 3.3V Interface
• Adjustable High Voltage Supplies
• Surface Mount Package
The CPC7220 is a low charge injection 8-channel
high-voltage analog switch integrated circuit (IC) for
use in applications requiring high voltage switching.
Control of the high voltage switching is via low voltage
TTL logic level compatible inputs for direct connectivity
to the system controller.
Applications
•
•
•
•
Because the CPC7220 is capable of switching high
load voltages and has a flexible load voltage range,
e.g. VPP/VNN : +40V/-160V or +100V/-100V, it is well
suited for many medical and industrial applications
such as medical ultrasound imaging, printers, and
industrial measurement equipment.
Ultrasound Imaging
Printers
Industrial Controls and Measurement
Piezoelectric Transducer Drivers
Figure 1. Block Diagram
SHIFT
REGISTER
LATCHES
LEVEL
SHIFTERS
SR0
L0
D
LE
CL
LS0
SR1
L1
D
LE
CL
SR2
L2
D
LE
CL
SR3
L3
D
LE
CL
SR4
L4
D
LE
CL
SWITCHES
CLK
DIN
SR5
SR6
SR7
DOUT
CL
LE
L5
D
LE
CL
L6
D
LE
CL
L7
D
LE
CL
Switch manipulation is managed by an 8-bit serial to
parallel shift register whose outputs are buffered and
stored by an 8-bit transparent latch. Level shifters
buffer the latch outputs and operate the high voltage
switches.
SW0
Construction of the high voltage switches using IXYS
Integrated Circuits Division's reliable BCDMOS
process technology on SOI (Silicon On Insulator)
allow the switches to be organized as solid state
switches with direct gate drive.
Ordering Information
SW1
Part Number Description
LS1
SW2
LS2
SW3
CPC7220W
CPC7220WTR
CPC7220K
CPC7220KTR
28-Lead PLCC in Tubes (37/Tube)
28-Lead PLCC Tape & Reel (500/Reel)
48-Lead LQFP in Trays (250/Tray)
48-Lead LQFP Tape & Reel (2000/Reel)
LS3
SW4
LS4
SW5
LS5
SW6
LS6
SW7
LS7
VPP VNN
Pb
DS-CPC7220-R00L
PRELIMINARY
e3
1
INTEGRATED CIRCUITS DIVISION
CPC7220
PRELIMINARY
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout, PLCC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Package Pinout, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Absolute Maximum Ratings @ 25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Logic Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Board Wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 CPC7220W 28-Pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 CPC7220K 48-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1 CPC7220WTR PLCC-28 Tape & Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.2 CPC7220KTR LQFP-48 Tape & Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
PRELIMINARY
R00L
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1. Specifications
1.1 Package Pinout, PLCC-28
25
23
22
21
20
19
26
18
27
17
28
16
1
15
2
14
3
13
4
12
5
R00L
24
1.2 Pin Description
6
7
8
9
10
11
Pin
Name
1
2
3
4
5
6
7
8
10
SW3
SW3
SW2
SW2
SW1
SW1
SW0
SW0
VPP
SW3 Output
SW3 Output
SW2 Output
SW2 Output
SW1 Output
SW1 Output
SW0 Output
SW0 Output
Switch Positive High Voltage Supply
12
13
14
VNN
Switch Negative High Voltage Supply
Ground
Logic Positive Voltage Supply
GND
VDD
DIN
16
17
18
CLK
LE
19
CL
20
DOUT
21
22
23
24
25
26
27
28
9, 11, 15
SW7
SW7
SW6
SW6
SW5
SW5
SW4
SW4
N/C
PRELIMINARY
Description
Serial Data Input
Clock Input, Positive Edge Trigger
Latch Enable, Active Low
Latch Clear, Active High Clears Latches
And Opens Switches
Serial Data Output
SW7 Output
SW7 Output
SW6 Output
SW6 Output
SW5 Output
SW5 Output
SW4 Output
SW4 Output
No Connection
3
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.4 Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
1.3 Package Pinout, LQFP-48
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
4
Pin
Name
1
3
5
8
10
12
14
16
18
20
22
24
SW5
SW4
SW4
SW3
SW3
SW2
SW2
SW1
SW1
SW0
SW0
VPP
SW5 Output
SW4 Output
SW4 Output
SW3 Output
SW3 Output
SW2 Output
SW2 Output
SW1 Output
SW1 Output
SW0 Output
SW0 Output
Switch Positive High Voltage Supply
25
28
29
VNN
Switch Negative High Voltage Supply
Ground
GND
VDD
DIN
Description
Logic Positive Supply Voltage
33
34
35
CLK
LE
36
CL
37
DOUT
39
41
43
45
47
2, 4, 6,
7, 9, 11,
13, 15,
17, 19,
21, 23,
26, 27,
30, 31,
32, 38,
40, 42,
44, 46,
48
SW7
SW7
SW6
SW6
SW5
Serial Data Input
Clock Input, Positive Edge Trigger
Latch Enable, Active Low
Latch Clear, Active High Clears Latches
And Opens Switches
Serial Data Output
SW7 Output
SW7 Output
SW6 Output
SW6 Output
SW5 Output
N/C
No Connection
PRELIMINARY
R00L
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.5 Absolute Maximum Ratings @ 25°C
Parameter
VDD Logic Power Supply Voltage
VPP - VNN Supply Voltage
Min
Max
Units
-0.5
6
V
-
220
V
VPP Positive High Voltage Supply
-0.5
VNN+200
V
VNN Negative High Voltage Supply
+0.5
VPP-200
V
Logic input voltages
-0.5
VDD+0.3
V
Analog signal range
VNN
VPP
V
-
1
A
-
2.5
2.3
W
-60
50
53
+150
Peak analog signal current per channel
Power dissipation
28-Lead PLCC
48-Lead LQFP
Thermal Resistance, Junction to Ambient
28-Lead PLCC
48-Lead LQFP
Storage temperature
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
C/W
C
1.6 Operating Conditions
Parameter
Symbol
Value
Logic power supply voltage 1, 3
VDD
4.5V to 6V
1, 3
VPP
40V to VNN + 200V
VNN
-40V to -160V
VSIG
VNN+10V to VPP-10V
TA
0°C to 70°C
Positive high voltage supply
Negative high voltage supply 1, 3
Analog signal voltage, peak-to-peak
Operating temperature
2
1
Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last.
2
VSIG must be VNN  VSIG  VPP or floating during power up/down transition.
3
Rise and fall times of power supplies, VDD , VPP , and VNN , should not be less than 1ms.
R00L
PRELIMINARY
5
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7 Electrical Characteristics
1.7.1 Switch Characteristics (over recommended operating conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
0°C
Small Signal Switch
On-Resistance Matching
+70°C
min
max
min
typ
max
min
max
-
20
38
-
48
VPP=40V, VNN=-160V, ISW=5mA
Small Signal Switch
On-Resistance
+25°C
Units
-
30
VPP=40V, VNN=-160V, ISW=200mA
-
25
-
-
27
-
32
VPP=100V, VNN=-100V, ISW=5mA
-
25
-
20
27
-
33
VPP=100V, VNN=-100V, ISW=200mA
-
18
-
15
24
-
27
VPP=160V, VNN=-40V, ISW=5mA
-
23
-
20
25
-
30
VPP=160V, VNN=-40V, ISW=200mA
-
22
-
-
25
-
27
RONS ISW=5mA, VPP=100V, VNN=-100V
-
20
-
4
20
-
20
%
-
-
-
16
-
-
-

A
RONS
Large Signal Switch On-resistance
RONL
VSIG=VPP-10V, ISIG=0.8A
Switch Off Leakage Per Switch
ISOL
VSIG=VPP-10V and VNN+10V

-
5
-
0.4
10
-
15
DC Offset, Switch Off
-
RL=100k
-
100
-
0.2
100
-
100
DC Offset, Switch On
-
RL=100k
-
100
-
0.2
100
-
100
Switch Output Peak Current
-
VSIG duty cycle = 0.1%
-
-
-
-
0.8
-
-
A
Duty cycle = 50%
-
-
-
-
50
-
-
kHz
-
20
-
-
20
-
20
V/ns
Output Switch Frequency
fSW
mV
VPP=160V, VNN=-40V
Maximum VSIG Slew Rate
dV/dt
VPP=100V, VNN=-100V
VPP=40V, VNN=-160V
Off Isolation
KO
f=5MHz, 1k/15pF load
f=5MHz, 50 load
-30
-58
-
-30
-58
-
-
-30
-58
-
dB
Switch Crosstalk
KCR
f=5MHz, 50 load
-60
-
-60
-
-
-60
-
dB
-
300
-
-
300
-
300
mA
Output Switch
Isolation Diode Current
IID
300ns pulse width, 2.0% duty cycle
Off Capacitance, SW to GND
CSG(OFF) VSW=0V, 1MHz
5
17
5
-
25
5
20
On Capacitance, SW to GND
CSG(ON) VSW=0V, 1MHz
25
40
20
-
40
25
50
VPP=40V, VNN=-160V, RL=50
-
-
-
150
-
-
VPP=100V, VNN=-100V, RL=50
-
-
-
150
-
-
VPP=160V, VNN=-40V, RL=50
-
-
-
150
-
-
+VSPK
-VSPK
Output Voltage Spike
+VSPK
-VSPK
+VSPK
-VSPK
Charge Injection
6
Q
VPP=100V, VNN=-100V, VSIG=0V
PRELIMINARY
-
37
93
35
80
46
72
880
-
pF
mV
pC
R00L
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7.2 Logic DC Characteristics (over recommended operating conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
0°C
+25°C
min
max
min
typ
+70°C
max
min
max
DOUT Source Capability
VOH
IOUT= - 400A
-
-
-
-
-
DOUT Sink Capability
VOL
IOUT= +400A
-
-
-
0.04
0.7
-
-
Logic Input Capacitance
CIN
-
10
-
-
10
-
10
Logic Input High
VIH
4.75V < VDD < 5.25V
2
-
2
-
-
2
-
Logic Input Low
VIL
4.75V < VDD < 5.25V
-
0.8
-
-
0.8
-
0.8
-
VDD-0.7 VDD-0.1
Units
V
pF
V
1.7.3 Logic Timing Characteristics (over recommended operating conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
Setup Time Before LE Rises
tSD
Time Width of LE
tWLE
Clock Delay Time to Data Out
tDO
Time Width of CL
0°C
+25°C
70°C
min
max
min
typ
max
min
max
-
150
-
150
-
-
150
-
-
150
-
150
-
-
150
-
-
-
150
-
62
150
-
150
tWCL
-
150
-
150
-
-
150
-
Setup Time, Data to Clock
tSU
-
15
-
15
8
-
20
-
Hold Time, Data from Clock
tH
-
35
-
35
-
-
35
-
Clock Frequency
fCLK
Clock Rise and Fall Times
tR, tF
Turn-On Time
tON
Turn-Off Time
tOFF
R00L
50% duty cycle, fDATA=fCLK/2
VSIG=VPP-10V, RL=10k
PRELIMINARY
Units
ns
-
5
-
-
5
-
5
MHz
-
50
-
-
50
-
50
ns
-
5
-
5
-
5
s
2
3
7
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.7.4 Supply DC Characteristics (over recommended operating conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
0°C
+25°C
+70°C
min
max
min
typ
max
min
max
Units
VPP Quiescent Supply Current
IPPQ
All Switches OFF
All Switches ON, ISW=5mA
-
-
-
0.1
10
-
-
VNN Quiescent Supply Current
INNQ
All Switches OFF
All Switches ON, ISW=5mA
-
-
-
-0.1
-10
-
-
VPP=40V,
VNN=-160V
-
6.5
-
-
7
-
8
-
5
-
-
5.5
-
5.5
-
5
-
-
5
-
5.5
-
6.5
-
-
7
-
8
-
5
-
-
5.5
-
5.5
-
5
-
-
5
-
5.5
-
4
-
-
4
-
4
mA
-
10
-
0.03
10
-
10
A
VPP Operating Supply Current
IPP
50kHz Output
Switching
Frequency with
No Load
VPP=100V,
VNN=-100V
VPP=160V,
VNN=-40V
VPP=40V,
VNN=-160V
VNN Operating Supply Current
INN
50kHz Output
Switching
Frequency with
No Load
VPP=100V,
VNN=-100V
VPP=160V,
VNN=-40V
VDD Average Supply Current
IDD
VDD Quiescent Supply Current
IDDQ
8
fCLK=5MHz, VDD=5V
-
PRELIMINARY
A
mA
mA
R00L
INTEGRATED CIRCUITS DIVISION
CPC7220
PRELIMINARY
2. Functional Description
The CPC7220 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of each
shift register is shifted through from SR(n) to SR(n+1).
A high data bit, a "1," represents an ON switch; a low
data bit, a "0," represents an OFF switch. Data is input
and shifted through the internal shift register until all
eight shift register positions, SR0 through SR7, are in
the desired state.
DIN: The data-in line presents data bits to be shifted
through the internal shift register.
CLK: The clock signal's rising edge is associated only
with shifting data into and through the shift register.
CL: The clear line overrides all other inputs. When CL
is high, the shift register is cleared to all 0s and all
latches are set low, which causes all output switches
to be turned OFF immediately. When CL is low, all
output switches remain in whatever state they are in,
ON or OFF, in response to CLK, latch inputs, and the
LE signal.
The high-voltage output switches are turned on and off
in response to the data sent into the latches from the
shift register: data 0 turns a switch OFF, data 1 turns a
switch ON.
Two or more CPC7220 devices can be cascaded to
form an n-switch arrangement. The DOUT pin of the
first is connected to the DIN pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to DIN of the CPC7220,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in line
after the application of a full clocking sequence of 8
clock pulses per CPC7220. Setting the serial I/O
device to output the most significant bit (MSB) first,
results in the MSB appearing on SW7 of the last
device in line after a full clocking sequence..
LE: latch enable controls the state of the latches and
thus the state of the eight switches. If LE is high, then
the latches do not change states, but retain their most
recent status: either ON or OFF. With LE high, input
data and CLK have no effect on the state of the output
switches. If LE is low, then all latch outputs and their
switch states follow the inputs from the shift register.
LE is overridden by CL: regardless of LE’s state, CL
clears the latches. See “Truth Table” on page 10.
DOUT: The data-out pin is the output of SR7. After
eight clock pulses, the first bit of eight input data bits is
shifted to SR7 and appears on DOUT.
SW0 - SW7: The CPC7220 provides eight
high-voltage SPST output switches with a typical
on-resistance of 20 The two connections of each
switch are not polarity-sensitive.
DIN
DIN
CLK
CLK
SW0
CPC7220
CL
CL
LE
LE
SW7
DOUT
DIN
CLK
SW0
CPC7220
CL
LE
SW7
DOUT
DIN
CLK
VPP and VNN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level of
the latch output signals to an appropriate level for the
voltages being switched.
SW0
CPC7220
CL
LE
DOUT
R00L
PRELIMINARY
SW7
9
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
2.1 Truth Table
D0
D1
D2
D3
D4
D5
D6
D7
LE
CL
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the rising edge of the CLK signal.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift
register data flows through the latch.
4. DOUT is high when switch 7 is on.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
10
PRELIMINARY
R00L
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
2.2 Logic Timing Waveforms
DN-1
DN
DIN
50%
LE
50%
DN+1
50%
50%
tWLE
tSD
tSU
tDO
DOUT
tH
50%
tOFF
VOUT OFF
(TYP)
50%
50%
CLK
tON
90%
10%
ON
CL
50%
50%
tWCL
R00L
PRELIMINARY
11
INTEGRATED CIRCUITS DIVISION
CPC7220
PRELIMINARY
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC7220W / CPC7220K
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC7220W
CPC7220K
245°C for 30 seconds
260°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
12
e3
PRELIMINARY
R00L
CPC7220
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
3.5 Mechanical Dimensions
3.5.1 CPC7220W 28-Pin PLCC Package
12.446 ± 0.254
(0.490 ± 0.010)
11.506 ± 0.102
(0.453 ± 0.004)
PCB Land Pattern
Pin 1
Designator
11.20
(0.441)
0.508 MIN
(0.020 MIN)
12.446 ± 0.254
(0.490 ± 0.010)
11.506 ± 0.102
(0.453 ± 0.004)
0.65
(0.026)
11.20
(0.441)
0.432 TYP
(0.017 TYP)
2.20
(0.087)
2.667 ± 0.381
(0.105 ± 0.015)
1.27 TYP
(0.050 TYP)
1.27
(0.050)
4.382 ± 0.254
(0.173 ± 0.010)
Dimensions
mm
(inches)
3.5.2 CPC7220K 48-Pin LQFP Package
9.00 ± 0.20
(0.354 ± 0.008)
7.00 ± 0.10
(0.276 ± 0.004)
PCB Land Pattern
7.00 ± 0.10
(0.276 ± 0.004)
9.00 ± 0.20
(0.354 ± 0.008)
0.50
(0.020)
8.40
(0.331)
Pin 48
Pin 1
0.22 ± 0.05
(0.009 ± 0.002)
1.40 ± 0.05
(0.055 ± 0.002)
0.60, +0.15/-0.10
(0.024, +0.006/-0.004)
R00L
8.40
(0.331)
1.60 Max
(0.063Max)
0.05 Min / 0.15 Max
(0.002 Min - 0.006 Max)
0.50
(0.020)
Dimensions
mm
(inches)
PRELIMINARY
0.30
(0.012)
1.50
(0.059)
13
INTEGRATED CIRCUITS DIVISION
CPC7220
PRELIMINARY
3.6 Tape and Reel Specifications
3.6.1 CPC7220WTR PLCC-28 Tape & Reel
330.2 DIA.
(13.00 DIA.)
24.0±0.3
(0.945±0.012)
B0=13.0
(0.512)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
K0=4.9
(0.193)
A0=13.0
(0.512)
16.00
(0.63)
Dimensions
mm
(inches)
Embossed Carrier
Embossment
NOTE: Unless otherwise noted, tolerance ±0.1 (0.004)
3.6.2 CPC7220KTR LQFP-48 Tape & Reel
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
16.0±0.3
(0.63±0.012)
B0=9.30
(0.366)
K0=2.20
(0.087)
A0=9.30
(0.366)
K1=1.60
(0.063)
12.00
(0.472)
Dimensions
mm
(inches)
Embossed Carrier
Embossment
NOTE: Unless otherwise specified, tolerance ±0.1 (0.004)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC7220-R00L
© Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/22/2012
14
PRELIMINARY
R00L