MC14514B, MC14515B 4−Bit Transparent Latch / 4−to−16 Line Decoder The MC14514B and MC14515B are two output options of a 4 to 16 line decoder with latched inputs. The MC14514B (output active high option) presents a logical “1” at the selected output, whereas the MC14515B (output active low option) presents a logical “0” at the selected output. The latches are R−S type flip−flops which hold the last input data presented prior to the strobe transition from “1” to “0”. These high and low options of a 4−bit latch / 4 to 16 line decoder are constructed with N−channel and P−channel enhancement mode devices in a single monolithic structure. The latches are R−S type flip−flops and data is admitted upon a signal incident at the strobe input, decoded, and presented at the output. These complementary circuits find primary use in decoding applications where low power dissipation and/or high noise immunity is desired. http://onsemi.com MARKING DIAGRAMS 24 1 PDIP−24 P SUFFIX CASE 709 MC145xxBCP AWLYYWWG 1 Features • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−power TTL Loads or One Low−power • Schottky TTL Load the Rated Temperature Range Pb−Free Packages are Available* 1 SOIC−24 DW SUFFIX CASE 751E 24 MC145xxB AWLYYWWG 1 MAXIMUM RATINGS (Voltages Referenced to VSS) xx A WL YY WW G = 14 or 15 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Symbol Value Unit VDD −0.5 to +18.0 V Vin, Vout −0.5 to VDD +0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ± 10 mA Power Dissipation per Package (Note 1) PD 500 mW ST 1 24 TA −55 to +125 °C VDD Ambient Temperature Range D1 2 23 INH Storage Temperature Range Tstg −65 to +150 °C D2 3 22 D4 Lead Temperature (8−Second Soldering) TL 260 °C S7 4 21 D3 S6 5 20 S10 S5 6 19 S11 S4 7 18 S8 S3 8 17 S9 S1 9 16 S14 Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) PIN ASSIGNMENT Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 S2 10 15 S15 S0 11 14 S12 VSS 12 13 S13 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14514B/D MC14514B, MC14515B BLOCK DIAGRAM VDD = PIN 24 VSS = PIN 12 DATA 1 DATA 2 DATA 3 DATA 4 STROBE INHIBIT 2 A 3 B 21 TRANSPARENT LATCH 22 C D 1 4 TO 16 DECODER DECODE TRUTH TABLE (Strobe = 1)* S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 11 9 10 8 7 6 5 4 18 17 20 19 14 13 16 15 ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD 23 Selected Output Data Inputs Inhibit D C B A MC14514 = Logic “1” MC14515 = Logic “0” 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 S0 S1 S2 S3 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 S4 S5 S6 S7 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 S8 S9 S10 S11 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 S12 S13 S14 S15 1 X X X X All Outputs = 0, MC14514 All Outputs = 1, MC14515 X = Don’t Care *Strobe = 0, Data is latched ORDERING INFORMATION Device Package Shipping† MC14514BCP PDIP−24 MC14514BCPG PDIP−24 (Pb−Free) 15 Units / Rail MC14514BDW SOIC−24 30 Units / Rail MC14514BDWR2 SOIC−24 MC14514BDWR2G SOIC−24 (Pb−Free) MC14515BCP PDIP−24 MC14515BCPG PDIP−24 (Pb−Free) 15 Units / Rail MC14515BDW SOIC−24 30 Units / Rail MC14515BDWR2 SOIC−24 MC14515BDWR2G SOIC−24 (Pb−Free) 1000 / Tape & Reel 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 MC14514B, MC14515B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 – 1.2 – 0.25 – 0.62 – 1.8 − − − − – 1.0 – 0.2 – 0.5 – 1.5 – 1.7 – 0.36 – 0.9 – 3.5 − − − − – 0.7 – 0.14 – 0.35 – 1.1 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) ITL 5.0 10 15 Characteristic Output Voltage Vin = VDD or 0 Symbol “0” Level “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink VIL Vdc VIH Vdc IOH mAdc IT = (1.35 mA/kHz) f + IDD IT = (2.70 mA/kHz) f + IDD IT = (4.05 mA/kHz) f + IDD mAdc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 3 MC14514B, MC14515B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL Propagation Delay Time; Data, Strobe to S tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.86 ns/pF) CL + 192 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns tPLH, tPHL Inhibit Propagation Delay Times tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 117 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL Setup Time Data to Strobe VDD Min Typ (Note 6) Max 5.0 10 15 − − − 180 90 65 360 180 130 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 550 225 150 1100 450 300 5.0 10 15 − − − 400 150 100 800 300 200 5.0 10 15 250 100 75 125 50 38 − − − 5.0 10 15 – 20 0 10 – 100 – 40 – 30 − − − 5.0 10 15 350 100 75 175 50 38 − − − Unit ns ns ns ns tsu Hold Time Strobe to Data th Strobe Pulse Width ns tWH ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD VDS STROBE INHIBIT For MC14514B 1. For P−channel: Inhibit = VSS 1. and D1−D4 constitute 1. binary code for “output 1. under test.” 2. For N−channel: Inhibit = VDD D1 D2 D3 D4 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 For MC14515B 1. For P−channel: Inhibit = VDD 2. For N−channel: Inhibit = VSS 2. and D1−D4 constitute binary 2. code for “output under test.” ID EXTERNAL POWER SUPPLY VSS Figure 1. Drain Characteristics Test Circuit http://onsemi.com 4 ns MC14514B, MC14515B VDD ID 24 PULSE GENERATOR VDD 0.01 mF CERAMIC 500 mF D1 S0 D2 D3 D4 STROBE INHIBIT S15 12 20 ns 20 ns Vin CL VDD 90% 10% VSS CL VSS Figure 2. Dynamic Power Dissipation Test Circuit and Waveform VDD STROBE INHIBIT PROGRAMMABLE PULSE GENERATOR OUTPUT S0 OUTPUT S1 S0 S1 tTLH CL CL INPUT D1 10% tTHL VDD 90% 50% VSS tPHL VDD tPLH D2 90% 50% 10% OUTPUT D3 D4 20 ns OUTPUT S15 S15 VSS CL Figure 3. Switching Time Test Circuit and Waveforms http://onsemi.com 5 tTLH VSS tTHL http://onsemi.com 6 INHIBIT 23 STROBE 1 DATA 4 22 DATA 3 21 DATA 2 3 DATA 1 2 Q Q R Q R S Q Q R S Q Q R S Q S D C B A LOGIC DIAGRAM IN MC14515B ONLY AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD AB CD 15 S15 16 S14 13 S13 14 S12 19 S11 20 S10 17 S9 18 S8 4 S7 5 S6 6 S5 7 S4 8 S3 10 S2 9 S1 11 S0 MC14514B, MC14515B MC14514B, MC14515B COMPLEX DATA ROUTING times faster then the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the 3−state bus is redistributed by the MC14514B four−bit latch/decoder. Using the four−bit address, D1 thru D4, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, A thru P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented. Two MC14512 eight−channel data selectors are used here with the MC14514B four−bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3−state data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be re−routed or intermixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the eight inputs on both MC14512 data selectors. One register is assigned to each input. The signals on A0, A1, and A2 choose one of eight inputs for transfer out to the 3−state data bus. A fourth signal, labelled Dis, disables one of the MC14512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1 thru 16, the rate of transfer of the sequential information can also be varied. That is, if the MC14512 were addressed at a rate that is eight DATA ROUTING SYSTEM REGISTER 1 D0 D1 D2 D3 D4 D5 D6 DIS 3−STATE DATA BUS DATA DISTRIBUTION OUTPUT REGISTERS Q D1 D2 D3 D4 S0 STROBE S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 INHIBIT S14 S15 D7 A0 A1 A2 REGISTER A MC14514B REGISTER 8 DATA TRANSFER MC14512 INPUT REGISTERS DATA SELECT A0 A1 A2 D0 Q D1 D2 D3 D4 D5 D6 D7 DIS MC14512 REGISTER 9 REGISTER 16 http://onsemi.com 7 REGISTER P MC14514B, MC14515B PACKAGE DIMENSIONS PDIP−24 CASE 709−02 ISSUE D NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. J 24 13 L B 1 12 A M N DIM A B C D F G H J K L M N C K H F G SEATING PLANE D INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 SOIC−24 CASE 751E−04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 24 13 −B− 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R X 45 _ C −T− SEATING PLANE DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 M 22X G K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC14514B/D