ESMT M53S128324A-2E Bi-directional data strobe (dqs) Datasheet

ESMT
M53S128324A (2E)
Mobile DDR SDRAM
1M x 32 Bit x 4 Banks
Mobile DDR SDRAM
Features
z
z
z
z
z
z
z
z
z
z
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
PASR (Partial Array Self Refresh)
Internal TCSR (Temperature Compensated Self
Refresh)
DS (Drive Strength)
z
z
z
z
z
z
z
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
VDD/VDDQ = 2.5V ± 0.2V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
LVCMOS-compatible inputs
Ordering Information
Product ID
Max Freq.
M53S128324A -5BG2E
200MHz
M53S128324A -6BG2E
166MHz
M53S128324A -7.5BG2E
133MHz
VDD
Package
Comments
2.5V
144 ball FBGA
Pb-free
Functional Block Diagram
Clock
Generator
Bank D
Bank C
Bank B
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
CLK
CLK
CKE
Bank A
DQS
DM
WE
Elite Semiconductor Memory Technology Inc.
Column Decoder
Data Control Circuit
Input & Output
Buffer
CAS
Column
Address
Buffer
&
Refresh
Counter
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
DQ
Publication Date : Jan. 2013
Revision : 1.0
1/47
ESMT
M53S128324A (2E)
BALL CONFIGURATION (TOP VIEW)
(BGA144, 12mmX12mmX1.4m Body, 0.8mm Ball Pitch)
2
3
4
5
6
7
8
9
10
11
12
13
B
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
C
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
D
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
E
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
F
DQ17
DQ16
VDDQ
VSSQ
VSSQ
VDDQ
DQ15
DQ14
G
DQ19
DQ18
VDDQ
VSSQ
VSSQ
VDDQ
DQ13
DQ12
H
DQS2
DM2
NC
VSSQ
Thermal
VSSQ
NC
DM1
DQS1
J
DQ21
DQ20
VDDQ
VSSQ
VSS
VSS
VSS
VSS
Thermal
Thermal
Thermal
Thermal
VSSQ
VDDQ
DQ11
DQ10
K
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
L
CAS
WE
VDD
VSS
A10/AP
VDD
VDD
NC
VSS
VDD
NC
NC
M
RAS
NC
NC
BA1
A2
A11
A9
A5
NC
CLK
CLK
NC
N
CS
NC
BA0
A0
A1
A3
A4
A6
A7
A8
CKE
NC
VSS
Thermal
VSS
VSS
VSS
Thermal
Thermal
Thermal
VSS
VSS
VSS
VSS
Thermal
Thermal
Thermal
Thermal
VSS
VSS
VSS
VSS
Thermal
Thermal
Thermal
Ball Description
Ball Name
A0~A11,
BA0~BA1
DQ0~DQ31
Function
Ball Name
Function
Address inputs
- Row address A0~A11
- Column address A0~ A7
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
DM0~DM3
DM is an input mask signal for write data.
DM0 corresponds to the data on
DQ0~DQ7; DM1 correspond to the data on
DQ8~DQ15; DM2 correspond to the data
on DQ16~DQ23; DM3 correspond to the
data on DQ24~DQ31.
Data-in/Data-out
CLK, CLK
Clock input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
VDDQ
Supply Voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power
NC
No connection
DQS0~DQS3
CKE
CS
Clock enable
Chip select
Bi-directional Data Strobe. DQS0
corresponds to the data on DQ0~DQ7;
DQS1 correspond to the data on
DQ8~DQ15; DQS2 correspond to the data
on DQ16~DQ23; DQS3 correspond to the
data on DQ24~DQ31.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 3.6
V
TA
0 ~ +70
°C
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Operating ambient temperature
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Supply voltage
VDD
2.3
2.7
V
I/O Supply voltage
VDDQ
2.3
2.7
V
Input logic high voltage (for Address and Command)
VIH (DC)
0.8 x VDDQ
VDDQ + 0.3
V
Input logic low voltage (for Address and Command)
VIL (DC)
-0.3
0.2 x VDDQ
V
Input logic high voltage (for DQ, DM, DQS)
VIHD (DC)
0.7 x VDDQ
VDDQ + 0.3
V
Input logic low voltage (for DQ, DM, DQS)
VILD (DC)
-0.3
0.3 x VDDQ
V
Output logic high voltage
VOH (DC)
0.9 x VDDQ
-
V
IOH = -0.1mA
Output logic low voltage
VOL (DC)
-
0.1 x VDDQ
V
IOL = 0.1mA
Input Voltage Level, CLK and CLK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CLK and CLK inputs
VID (DC)
0.4 x VDDQ
VDDQ + 0.6
V
II
-2
2
μA
IOZ
-5
5
μA
Input leakage current
Output leakage current
Note
1
Note:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
DC Characteristics
Recommended operating condition (Voltage reference to VSS = 0V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in
power-down
mode
Symbol
IDD2P
Active Standby
Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
-6
-7.5
55
50
45
Unit
CS = HIGH between valid commands; address inputs
are SWITCHING; data input signals are STABLE
All banks idle, CKE = LOW; CS = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
mA
900
μA
900
μA
All banks idle, CKE = LOW; CS = HIGH, CLK = LOW,
IDD2PS
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
All banks idle, CKE = HIGH; CS = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
10
9
8
mA
10
9
8
mA
All banks idle, CKE = HIGH; CS = HIGH, CLK = LOW,
IDD2NS
IDD3P
Active Standby
Current
in power-down
mode
-5
tRC= tRC (min); tCK = tCK (min); CKE = HIGH;
IDD0
IDD2N
Precharge Standby
Current in non
power-down mode
Version
Test Condition
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
One bank active, CKE = LOW; CS = HIGH,
tCK = tCK (min); address & control inputs are
SWITCHING; data input signals are STABLE
3
mA
1.2
mA
One bank active, CKE = LOW; CS = HIGH,
IDD3PS
IDD3N
CLK = LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
One bank active, CKE = HIGH, CS = HIGH,
tCK = tCK (min); address & control inputs are
SWITCHING; data input signals are STABLE
30
27
25
mA
7
6
5
mA
One bank active, CKE = HIGH; CS = HIGH,
IDD3NS
CLK= LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
IDD4R
One bank active; BL=4; CL=3; tCK = tCK (min);
continuous read bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data changing each burst
120
110
100
mA
IDD4W
One bank active; BL=4; tCK = tCK (min); continuous
write bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data changing each burst
100
90
80
mA
IDD5
Burst refresh; tCK = tCK (min);
tRFC= tRFC(min)
70
60
50
mA
tRFC= tREFI
10
8
6
mA
Auto Refresh
Current
CKE = HIGH; address inputs are
SWITCHING; data input signals are
IDD5A
STABLE
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
TCSR range
45
85
°C
Full array
950
1000
μA
1/2 array
900
950
μA
1/4 array
850
900
μA
1/8 array
800
850
μA
CKE = LOW, CLK = LOW,
Self Refresh Current
IDD6
CLK = HIGH; EMRS set to all
0’s; address & control & data bus
inputs are STABLE
Deep Power Down
Current
IDD8
address & control & data inputs are STABLE
μA
10
Note: 1. Input slew rate is 1V/ns.
2. IDD specifications are tested after the device is properly initialized.
3. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * V DDQ;
HIGH is defined as V IN ≥ 0.9 * V DDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIHD(AC)
0.8 x VDDQ
VDDQ+0.3
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VILD(AC)
-0.3
0.2 x VDDQ
V
Input Differential Voltage, CLK and CLK inputs
VID(AC)
0.6 x VDDQ
VDDQ+0.6
V
1
Input Crossing Point Voltage, CLK and CLK inputs
VIX(AC)
0.4 x VDDQ
0.6 x VDDQ
V
2
Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 2.5V, VDDQ = 2.5V, TA = 25 °C , f = 1MHz)
Parameter
Symbol
Min
Max
Unit
CIN1
1.5
3.0
pF
Input capacitance (CLK, CLK )
CIN2
1.5
3.0
pF
Data & DQS input/output capacitance
COUT
3.0
5.0
pF
Input capacitance (DM)
CIN3
3.0
5.0
pF
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
AC Operating Test Conditions (VDD = 2.5V ± 0.2V)
Parameter
Value
Unit
1.0
V/ns
0.8 x VDDQ / 0.2 x VDDQ
V
Input timing measurement reference level
0.5 x VDDQ
V
Output timing measurement reference level
0.5 x VDDQ
V
Input signal minimum slew rate
Input levels (VIH/VIL)
AC Timing Parameter & Specifications
(VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V)
Parameter
Clock Period
Symbol
CL3
tCK
CL2
-5
-6
-7.5
Unit
min
max
min
max
min
max
5
100
6
100
7.5
100
ns
12
100
12
100
12
100
ns
Note
12
CL3
tAC(3)
2
5
2
5.5
2
6
ns
CL2
tAC(2)
2
6.5
2
6.5
2
6.5
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CL3
tDQSCK (3)
2
5
2
5.5
2
6
ns
CL2
tDQSCK (2)
2
6.5
2
6.5
2
6.5
ns
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
Data-in and DM setup time (to DQS)
(fast slew rate)
tDS
0.55
0.6
0.8
ns
13,14
,15
Data-in and DM hold time (to DQS)
(fast slew rate)
tDH
0.55
0.6
0.8
ns
13,14
,15
Data-in and DM setup time (to DQS)
(slow slew rate)
tDS
0.58
0.7
0.9
ns
13,14
,16
Data-in and DM hold time (to DQS)
(slow slew rate)
tDH
0.58
0.7
0.9
ns
13,14
,16
tDIPW
1.8
1.8
1.8
ns
17
Input setup time (fast slew rate)
tIS
0.9
1.1
1.3
ns
15,18
Input hold time (fast slew rate)
tIH
0.9
1.1
1.3
ns
15,18
Input setup time (slow slew rate)
tIS
1.1
1.3
1.5
ns
16,18
Input hold time (slow slew rate)
tIH
1.1
1.3
1.5
ns
16,18
tIPW
2.3
2.7
3.0
ns
17
DQS input high pulse width
tDQSH
0.4
0.4
0.4
tCK
DQS input low pulse width
tDQSL
0.4
0.4
0.4
tCK
DQS falling edge to CLK rising-setup
time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CLK
rising-hold time
tDSH
0.2
0.2
0.2
tCK
Data strobe edge to output data edge
tDQSQ
Access time from CLK/ CLK
Data strobe edge to clock
edge
Clock to first rising edge of DQS delay
DQ and DM input pulse width (for
each input)
Control and Address input pulse width
Elite Semiconductor Memory Technology Inc.
0.4
0.5
0.6
ns
20
Publication Date : Jan. 2013
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ESMT
M53S128324A (2E)
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-5
min
-6
max
min
-7.5
max
min
max
Unit
Note
Data-out high-impedance
CL3
tHZ (3)
5
5.5
6
ns
19
window from CLK/ CLK
CL2
tHZ (2)
6.5
6.5
6.5
ns
19
Data-out low-impedance window from
tLZ
1.0
1.0
1.0
ns
19
Half Clock Period
tHP
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns
10,11
DQ-DQS output hold time
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ns
11
Data hold skew factor
tQHS
0.75
ns
11
ACTIVE to PRECHARGE command
tRAS
40
70K
ns
Row Cycle Time
tRC
55
60
67.5
ns
AUTO REFRESH Row Cycle Time
tRFC
80
80
80
ns
ACTIVE to READ,WRITE delay
tRCD
15
18
22.5
ns
PRECHARGE command period
tRP
15
18
22.5
ns
Minimum tCKE High/Low time
tCKE
2
2
2
tCK
ACTIVE bank A to ACTIVE bank B
command
tRRD
10
12
15
ns
WRITE recovery time
tWR
15
15
15
ns
Write data in to READ command delay
tWTR
2
2
2
tCK
Col. Address to Col. Address delay
tCCD
1
1
1
tCK
Refresh period
tREF
64
64
64
ms
Average periodic refresh interval
tREFI
15.6
15.6
15.6
μs
Write preamble
tWPRE
0.25
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
22
CL3
tRPRE (3)
0.9
1.1
0.9
1.1
0.9
1.1
tCK
23
CL2
tRPRE (2)
0.5
1.1
0.5
1.1
0.5
1.1
tCK
23
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWPRES
0
0
0
ns
Load Mode Register / Extended Mode
register cycle time
tMRD
2
2
2
tCK
Exit self refresh to first valid command
tXSR
200
200
200
ns
24
Exit power-down mode to first valid
command
tXP
25
25
25
ns
25
Auto precharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
ns
26
CLK/ CLK
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup
time
0.5
70K
0.65
42
70K
0.25
45
0.25
9
tCK
21
Notes:
1. All voltages referenced to VSS.
2.
All parameters assume proper device initialization.
3.
Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device operation are
guaranteed for the full voltage and temperature range specified.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
4.
M53S128324A (2E)
The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission
line terminated at the tester electronics). For the half strength driver with a nominal 10 pF load parameters tAC and tQH are
expected to be in the same range. However, these parameters are not subject to production test but are estimated by design /
characterization. Use of IBIS or other simulation tools for system design validation is suggested.
I/O
Timing Reference Load
5.
Z0 = 50 ohms
20 pF
The CLK/ CLK input reference voltage level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;
the input reference voltage level for signals other than CLK/ CLK is VDDQ/2.
6.
The timing reference voltage level is VDDQ/2.
7.
AC and DC input and output voltage levels are defined in AC/DC operation conditions.
8.
A CLK/ CLK differential slew rate of 2.0 V/ns is assumed for all parameters.
9.
A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given Mobile DDR,
meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 8 x tREFI.
10. Refer to the smaller of the actual clock low time and the actual clock high time as provided to the device.
11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during power-down or self-refresh modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC)
to VIL(AC) for falling input signals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no
writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in
progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in
the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
24. There must be at least two clock pulses during the tXSR period.
25. There must be at least one clock pulse during the tXP period.
26. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.
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Publication Date : Jan. 2013
Revision : 1.0
8/47
ESMT
M53S128324A (2E)
Command Truth Table
COMMAND
CKEn-1 CKEn CS
RAS
CAS
WE
DM
BA0,1
A10/AP
A11,
A9~A0
Note
Register
Extended MRS
H
X
L
L
L
L
X
OP CODE
1,2
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
Auto Refresh
Refresh
Entry
Self Refresh
Exit
H
L
L
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
V
V
Entry
H
L
L
H
H
L
X
Exit
L
H
H
X
X
X
L
H
H
H
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Entry
H
L
H
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
L
H
H
H
H
X
H
X
X
X
L
H
H
H
Bank Active & Row Addr.
Read &
Column
Address
Auto Precharge Disable
Write &
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Deep Power Down Mode
Burst Terminate
Precharge
H
Bank Selection
All Banks
Active Power Down Mode
Precharge Power Down
Mode
Deselect (NOP)
No Operation (NOP)
3
3
3
3
Row Address
L
H
L
H
Column
Address
(A0~A7)
Column
Address
(A0~A7)
4
4
4,8
4,6,8
X
X
X
V
L
X
H
7
X
5
X
X
X
X
X
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding and
coincident DM is “High”. (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
9/47
ESMT
M53S128324A (2E)
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a high state (all other inputs may be undefined.)
-
Apply VDD before or at the same time as VDDQ.
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK, CLK ), apply NOP.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLOCK
CKE
High level is necessary
CS
tRFC
tRP
tRFC
tMRD
tMRD
RAS
CAS
ADDR
Key
Key
RA
BA1
BS
BA0
BS
A10/AP
RA
DQ
High-Z
WE
DQM
High level is necessary
Precharge
Auto Refresh
(All Banks)
Auto Refresh
Mode Register Set
Row Active
Extended Mode
Register Set
: Don't care
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS latency,
addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of different
applications. The default value of the register is not defined, therefore the mode register must be written in the power up sequence
of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0~BA1 (The Mobile
DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address
pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1
BA0
A11~ A7
0*
0*
0*
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
A3
Burst Type
0
Sequential
1
Interleave
Address Bus
Mode Register
Burst Length
CAS Latency
BA1 BA0
0
0
1
0
Operating Mode
MRS Cycle
EMRS Cycle
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latency
Sequential
Reserved
2
4
8
16
Reserved
Reserved
Reserved
Interleave
Reserved
2
4
8
16
Reserved
Reserved
Reserved
* BA0~BA1 and A11~A7 should stay “0” during MRS cycle
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
Burst Address Ordering for Burst Length
Burst
Length
Starting Column
Address
A3
A2
A1
A0
2
4
8
16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sequential Mode
Interleave Mode
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1
3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2
4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3
5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4
6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5
7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6
8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7
9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8
A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A
C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B
D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C
E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D
F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, B, A, D, C, F, E
2, 3, 0, 1, 6, 7, 4, 5, A, B, 8, 9, E, F, C, D
3, 2, 1, 0, 7, 6, 5, 4, B, A, 9, 8, F, E, D, C
4, 5, 6, 7, 0, 1, 2, 3, C, D, E, F, 8, 9, A, B
5, 4, 7, 6, 1, 0, 3, 2, D, C, F, E, 9, 8, B, A
6, 7, 4, 5, 2, 3, 0, 1, E, F, C, D, A, B, 8, 9
7, 6, 5, 4, 3, 2, 1, 0, F, E, D, C, B, A, 9, 8
8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7
9, 8, B, A, D, C, F, E, 1, 0, 3, 2, 5, 4, 7, 6
A, B, 8, 9, E, F, C, D, 2, 3, 0, 1, 6, 7, 4, 5
B, A, 9, 8, F, E, D, C, 3, 2, 1, 0, 7, 6, 5, 4
C, D, E, F, 8, 9, A, B, 4, 5, 6, 7, 0, 1, 2, 3
D, C, F, E, 9, 8, B, A, 5, 4, 7, 6, 1, 0, 3, 2
E, F, C, D, A, B, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
F, E, D, C, B, A, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
Extended Mode Register Set (EMRS)
The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE , BA0
and high on BA1 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in
the extended mode register. Refer to the table for specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as long
as all banks are in the idle state.
Internal Temperature Compensated Self Refresh (TCSR)
1.
In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control
the self refresh cycle automatically according to the device temperature.
2.
If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
BA1 BA0
1
0*
A11 ~ A8
0*
A7
A6 A5
DS
A4 A3
TCSR
A2
A1 A0
PASR
Address bus
Extended Mode Register Set
A2-A0
000
001
PASR
010
011
100
101
110
111
Self Refresh Coverage
Full array
1/2 array (BA1 = 0)
1/4 array
(BA1 = BA0 =0)
Reserved
Reserved
1/8 array
Reserved
Reserved
Internal TCSR
DS
A7-A5
000
001
010
011
100
Drive Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
3/4 Strength
* BA0 and A11~ A8 should stay “0” during EMRS cycle
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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ESMT
M53S128324A (2E)
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control
inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both
Deselect and NOP, the device should finish the current operation when this command is issued.
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ESMT
M53S128324A (2E)
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The Mobile DDR SDRAM has four independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
2
3
4
5
6
CLK
CLK
Address
Bank A
Col. Addr.
Bank A
Row Addr.
RAS-CAS delay (tRCD)
Command
Bank A
Activate
NOP
NOP
Bank A
Row. Ad dr.
Bank B
Row Addr.
RAS-RAS delay (tRRD)
Write A
with Auto
Prec harge
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time (tRC)
: Don't Care
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , RAS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth
table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , RAS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The
length of the burst will be determined by the values programmed during the MRS command.
Elite Semiconductor Memory Technology Inc.
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ESMT
M53S128324A (2E)
Essential Functionality for Mobile DDR SDRAM
Burst Read Operation
Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst read
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK)
after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of
burst and burst length. The first output data is available after the CAS Latency from the READ command, and the consecutive
data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR SDRAM until the burst length is
completed.
<Burst Length = 4, CAS Latency = 3>
0
CLK
1
2
3
4
5
6
7
8
CLK
COMMAND
NOP
READ A
NOP
NOP
tDQSCK
NOP
NOP
NOP
NOP
NOP
tDQSCK
tRPST
tRPRE
DQS
CAS Latency=3
tDQSQ(max)
tAC
Dout0 Dout1 Dout2 Dout3
DQ's
tQH
tQHS
tQH
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock
(CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write
cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled
after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on
each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CLK
CLK
CO MMAND
NOP
NOP
W RITEA
W RITEB
NOP
NOP
NOP
NOP
PREB
tWR
tDQSS(max)
DQS
tWPRES
DQ's
Din0
Din1
Din2
Din3
Din0
Din1
Din2
Din3
tWR
tDQSS(min)
DQS
tWPRES
DQ's
Din0
Din1
Din2
Din3
Din0
Din1
Din2
Din3
tDS tDH
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ESMT
M53S128324A (2E)
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 clock.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
CLK
CLK
tCCD(min)
COMMAND
DQS
READ A
RE AD B
NOP
NOP
NOP
NOP
NOP
tDQSCK
Hi-Z
tRPST
tRPRE
DQ's
NOP
NOP
Hi-Z
D o u t A 0 D o u t A 1 D ou t B 0 D o u t B 1 D o u t B 2 D o u t B 3
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O
bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning
the write operation, Burt Terminate command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］
before the Write command.
<Burst Length = 4, CAS Latency = 3>
CLK
0
1
2
3
4
5
6
7
8
CLK
COMMAND
READ
Burst
Te r m i n a t e
NOP
NOP
NOP
DQS
tRPST
tWPST
tW PRES
tAC
DQ's
NOP
NOP
tDQSS
tDQSCK
tRPRE
NOP
W RITE
D ou t 0 D o u t 1
Din 0 Din 1 Din 2
Din 3
tWPRE
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU (CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
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ESMT
M53S128324A (2E)
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
CLK
0
1
2
3
4
5
6
7
8
CLK
1tCK
COMMAND
READ
Precha rge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS
tRPRE
tAC
DQ's
D ou t 0 D ou t 1 D o ut 2 D o ut 3 D ou t 4 D ou t 5 Do ut 6 D o ut 7
Interrupted by precharge
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before
the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst
and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP.
3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with auto precharge commands where tRAS(min) must still be satisfied such that a Read with auto
precharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
Elite Semiconductor Memory Technology Inc.
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ESMT
M53S128324A (2E)
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses
are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
CLK
1
2
3
4
5
6
7
8
CL K
1tCK
C OMM AN D
N OP
WR IT E A
WR IT E B
N OP
NO P
N OP
NO P
N OP
N OP
D QS
D Q's
D in A 0
D in A 1
Di n B 0
D in B 1
Di n B 2
D in B 3
tCCD
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ESMT
M53S128324A (2E)
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to
avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is
initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of
write command.
<Burst Length = 8, CAS Latency = 3>
0
CLK
1
2
3
4
5
6
7
8
CLK
COMMAND
NOP
NOP
W RITE
tDQSS(max)
DQS
NOP
NOP
READ
NOP
NOP
NOP
tWTR
Hi-Z
5)
tWPRES
DQ's
H i- Z
Dina0 Dina1 Dina2 Dina3 Dina4 D ina5 Dina6 Dina7
Dout0 Dout1
DM
tDQSS(min)
DQS
tWTR
Hi-Z
5)
tWPRES
DQ's
Hi-Z
Dina0 Dina1 D ina2 Dina3 Dina4 Dina5 Dina6 D ina7
Dout0 Dout1
DM
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the
memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM.
5. It is illegal for a Read command interrupt a Write with auto precharge command.
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ESMT
M53S128324A (2E)
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted,
any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
CLK
1
2
3
4
5
6
7
8
CLK
CO MMAND
W RITE A
NOP
NOP
NOP
NOP
t DQ SS(max)
DQS
Hi-Z
DQ's
H i- Z
NOP
tWR
PrechargeA
NOP
W RITE B
tDQSS(max)
tWPRES
tWPRES
Dina0 Dina1 Dina2 Dina3
Dinb0
DM
tDQS S(min)
DQS
tWR
tWPRES
DQ's
t DQSS(min)
Hi-Z
Hi-Z
tWPRES
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
Dinb0 Dinb1
DM
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow “Write recovery” which is the time
required by a Mobile DDR SDRAM core to properly store a full “0” or “1” level before a Precharge operation. For Mobile DDR
SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge
command to the same bank.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge
that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP
where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes
in the Bank Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same
time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with auto precharge commands where tRAS(min) must still be satisfied such that a Write with auto
precharge command has the same timing as a Write command followed by the earliest possible Precharge command which
does not interrupt the burst.
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ESMT
M53S128324A (2E)
Burst Terminate
The Burst Terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The Burst Terminate command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the Burst Terminate command is issued during a burst read cycle, the pair of data
and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
Burst Terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
2
3
4
5
6
7
8
CLK
CLK
CO MMAND
READ A
Burst
Terminat e
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst read ends after a deley equal to the CAS lantency.
DQS
Hi-Z
DQ's
Hi-Z
D out 0 Dout 1
The Burst Terminate command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required.
1.
2.
3.
4.
5.
6.
The BST command may only be issued on the rising edge of the input clock, CLK.
BST is only a valid command during Read burst.
BST during a Write burst is undefined and shall not be used.
BST applies to all burst lengths.
BST is an undefined command during Read with auto precharge and shall not be used.
When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
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ESMT
M53S128324A (2E)
DM masking
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
CLK
0
1
2
3
4
5
6
7
8
CLK
CO MMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS
DQS
Hi-Z
tWPRES
DQ's
D ina0 D ina1 D ina2 Dina3 Dina4 Dina5 D ina6 Dina7
Hi-Z
DM
masked by DM=H
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ESMT
M53S128324A (2E)
Read with Auto Precharge
If a read with auto precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2
clock later from a read with auto precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will
be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
CLK
0
1
2
3
4
5
6
7
10
9
8
CLK
CO MMAND
Bank A
ACTIVE
NOP
NOP
NOP
Read A
Aut o Precharge
NOP
NOP
NOP
NOP
tRP
DQS
DQ's
NOP
NOP
Bank can be reactivated at
completion of tRP 1)
Hi-Z
Dout 0 Dout 1 Do ut 2 Dout 3
Hi-Z
Auto-Precharge starts
tRAS(m in)
Note: The row active command of the precharge bank can be issued after tRP from this point.
Asserted
For Same Bank
Command
For Different Bank
5
6
7
5
6
7
READ + No AP
Illegal
Illegal
Legal
Legal
Legal
READ + AP
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
READ
1
READ + AP
Note: 1. AP = Auto Precharge
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ESMT
M53S128324A (2E)
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of the CLK
with the tWR delay after the last data-in.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CLK
COMMAND
Bank A
ACTIVE
NOP
NOP
W r ite A
Auto Prech arge
NOP
NOP
NOP
D IN 0
D IN 2
NOP
NOP
NOP
NOP
NOP
NOP
DQS
*Bank can be reactivated at
completion of tRP
DQ's
D IN 1
D IN 3
tWR
tRP
Internal precharge s tart
Note: The row active command of the precharge bank can be issued after tRP from this point.
For Same Bank
Asserted
Command
For Different Bank
5
6
7
8
9
10
5
6
7
8
9
WRITE
WRITE +
NO AP
WRITE +
NO AP
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE +
1
AP
WRITE +
AP
WRITE +
AP
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ +
No AP
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
READ
Illegal
READ +
READ +
No AP + DM2 No AP+ DM
Illegal
READ +
AP+ DM
READ +
AP+ DM
READ +
AP
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ + AP
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by Precharge & DM”
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ESMT
M53S128324A (2E)
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the
clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given Mobile DDR, meaning
that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x tREFI.
CLK
CLK
CO MMA ND
Auto
Refr esh
PRE
CMD
CKE = High
tRFC
tRP
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock
(CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self
refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power
consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than tXSR.
CLK
CLK
CO MMAND
NOP
Sel f
Ref resh
NOP
NOP
NOP
NOP
Auto
Ref resh
NOP
tXSR(min)
CKE
tIS
tIS
Note: After self refresh exit, input an auto refresh command immediately.
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M53S128324A (2E)
Power Down
Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is
referred to as active power-down.
Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low
must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is specified by tCKE. However,
power down duration is limited by the refresh requirements of the device.
The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid
command may be applied tXP after exit from power down.
CLK
CLK
tCKE
tRP
tCKE
tXP
tXP
CKE
tIS
tIS
CO MMAND
Precharge
tIS
tIS
Active
E n t e r P re c h a rg e
p o w e r- d o wn
mode
Exit Precharge
p o we r -d o wn
mo de
Read
E n t e r Ac ti v e
p o w e r- d o wn
mode
E x it A c t i v e
p o we r -d o w n
mo de
Functional Truth Table
Truth Table – CKE [Note 1~10]
CKE n-1
CKE n
Current State
COMMAND n
L
L
Power Down
X
Maintain Power Down
L
L
Self Refresh
X
Maintain Self Refresh
L
L
Deep Power Down
X
Maintain Deep Power Down
L
H
Power Down
NOP or DESELECT
Exit Power Down
5,6,9
L
H
Self Refresh
NOP or DESELECT
Exit Self Refresh
5,7,10
L
H
Deep Power Down
NOP or DESELECT
Exit Deep Power Down
5,8
H
L
All Banks Idle
NOP or DESELECT
Precharge Power Down Entry
5
Active Power Down Entry
5
H
L
Bank(s) Active
NOP or DESELECT
H
L
All Banks Idle
AUTO REFRESH
H
L
All Banks Idle
BURST TERMINATE
H
H
ACTION n
NOTE
Self Refresh Entry
Enter Deep Power Down
See the other Truth Tables
Notes:
1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of Mobile DDR immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power Down exit procedure must be followed the figure of Deep Power Down Mode Entry & Exit Cycle.
9. The clock must toggle at least once during the tXP period.
10. The clock must toggle at least once during the tXSR time.
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ESMT
M53S128324A (2E)
Truth Table – Current State Bank n
Current State
CS
Command to Bank n
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
disabled)
Write
(Auto Precharge
disabled)
Read with
Auto Precharge
Write with
Auto Precharge
CAS
WE
COMMAND / ACTION
NOTE
H
X
X
X
DESELECT (NOP / continue previous operation)
L
H
H
H
No Operation (NOP / continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
9
L
L
L
L
MODE REGISTER SET
9
L
H
L
H
READ (select column & start read burst)
L
H
L
L
WRITE (select column & start write burst)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
4
L
H
L
H
READ (select column & start new read burst)
5
L
H
L
L
WRITE (select column & start write burst)
5, 12
L
L
H
L
PRECHARGE (truncate read burst, start precharge)
L
H
H
L
BURST TERMINATE
10
L
H
L
H
READ (select column & start read burst)
5,11
L
H
L
L
WRITE (select column & start new write burst)
5
L
L
H
L
PRECHARGE (truncate write burst, start precharge)
11
DESELECT (NOP / continue previous operation)
Command to Bank m
Any
RAS
[Note 1~12]
[Note 1~3,6, 11~16]
H
X
X
X
L
H
H
H
No Operation (NOP / continue previous operation)
X
X
X
X
Any command allowed to bank m
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
16
16
L
H
L
L
WRITE (select column & start write burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start new read burst)
16
L
H
L
L
WRITE (select column & start write burst)
12,16
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
11,16
L
H
L
L
WRITE (select column & start new write burst)
16
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start new read burst)
13,16
L
H
L
L
WRITE (select column & start write burst)
12,13,16
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
13,16
L
H
L
L
WRITE (select column & start new write burst)
13,16
L
L
H
L
PRECHARGE
Notes:
1. The table applies when both CKE n-1 and CKE n are HIGH, and after tXSR or tXP has been met if the previous state was Self
Refresh or Power Down.
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ESMT
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
M53S128324A (2E)
DESELECT and NOP are functionally interchangeable.
All states and sequences not shown are illegal or reserved.
This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for
precharging.
The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.
Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses
are in progress.
Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and the part of Command to Bank n, according to the part of
Command to Bank m.
Precharging: starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will
be in the idle state.
Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be
in the ‘row active’ state.
Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP
has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied to
each positive clock edge during these states.
Refreshing: starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the device
will be in an ‘all banks idle’ state.
Accessing Mode Register: starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the device will be in an ‘all banks idle’ state.
Precharging All: starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank
will be in the idle state.
Not bank-specific; requires that all banks are idle and no bursts are in progress.
Not bank-specific. BURST TERMINATE affects the most recent read burst, regardless of bank.
Requires appropriate DM masking.
A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be
issued to end the READ prior to asserting a WRITE command.
Read with AP enabled and Write with AP enabled: the Read with Auto Precharge enabled or Write with Auto Precharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all the data in the burst. For Write with AP, the precharge period begins when tWR
ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and
ends where the precharge period (or tRP) begins. During the precharge period of the Read with AP enabled or Write with AP
enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access
period, only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related
limitations apply (e.g. contention between READ data and WRITE data must be avoided).
AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and
WRITEs with Auto Precharge disabled.
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ESMT
M53S128324A (2E)
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
tCH tCL
tCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
CLK
HIGH
CKE
tIS
CS
tIH
RAS
CAS
BA0, BA1
BAa
A1 0/AP
Ra
ADDR
(A0~An)
Ra
BAa
tDQSS
BAb
Ca
tD QSS
Cb
WE
tDSH tDSS
Hi-Z
DQS
tDQSCK
tLZ
DQ
Hi-Z
tDQSL
tWPST
Hi-Z
tQH
tDQSQ
Qa0
tAC
tDQSS
tRPST
tRPRE
Qa1
Qa2
tW PRES
tHZ
Qa3
Db0
Hi-Z
Hi-Z
tDQSH
tWPRE
Db1
Db2
Db3
Hi-Z
tDS tDH
tQHS
DM
CO MMAND
Active
READ
WRITE
10122B32R.B
Note: tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
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M53S128324A (2E)
Multi Bank Interleaving READ (@BL=4, CL=3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
BAa
BAb
Ca
Cb
WE
tRRD
tCCD
DQS
Hi-Z
DQs
H i-Z
Qa0
Qa1
Qa2
Qa 3
Qb0
Qb1
Qb2
Qb3
DM
tRCD
COMMAND
ACTIVE
ACTIVE
READ
READ
10122B32R.B
Elite Semiconductor Memory Technology Inc.
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ESMT
M53S128324A (2E)
Multi Bank Interleaving WRITE (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
BAa
tRRD
BAb
tCCD
Rb
Cb
Ca
WE
DQS
Hi- Z
DQ
Hi-Z
Da 0
Da1
Da2
Da3
Db 0
Db1
Db2
Db3
DM
tRCD
CO MMAND
ACTIVE
ACTIVE
WRITE
WRITE
10122B32R.B
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ESMT
M53S128324A (2E)
Read with Auto Precharge (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIG H
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAa
A10/AP
Ra
ADDR
(A0~A n)
Ca
Ra
WE
Auto prec har ge s tart
tRP
1)
Note
DQ S(CL=3)
DQ(CL=3)
Hi-Z
Qa0
H i-Z
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
DM
COMMAND
READ
ACTIVE
10122B32R.B
Note: The row active command of the precharge bank can be issued after tRP from this point.
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ESMT
M53S128324A (2E)
Write with Auto Precharge (@BL=8)
CLK
0
1
2
3
4
5
6
7
8
9
10
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAa
A10 /AP
ADDR
(A0~An)
Ra
Ca
Ra
WE
tD AL
tWR
Auto prechar ge start
Note1
tRP
DQS
DQ
Da 0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
DM
CO MMA ND
WRITE
ACTIVE
10122B32R.B
Note: The row active command of the precharge bank can be issued after tRP from this point.
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ESMT
M53S128324A (2E)
Read Interrupted by Precharge (@BL=8)
.
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
DQS
Hi-Z
DQs
Hi-Z
2
Qa0
Qa1
Qa2
tCK
Qa3
Valid
Qa4
Qa5
DM
CO MMA ND
READ
PRE
CHARGE
10122B32R.B
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ESMT
M53S128324A (2E)
Read Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
Ca
Cb
A10 /AP
ADDR
(A0~An)
WE
DQS
Hi-Z
DQs
Hi-Z
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb6
Qb7
DM
CO MMA ND
READ
READ
10122B32R.B
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ESMT
M53S128324A (2E)
Read Interrupted by a Write & Burst Terminate (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~A n)
WE
DQS
Hi-Z
DQs
Hi-Z
Qa0
Qa1
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
DM
CO MMAND
READ
Burst
Terminate
WRITE
10122B32R.B
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ESMT
M53S128324A (2E)
Write followed by Precharge (@BL=4)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAa
A10/AP
ADDR
(A0~A n)
Ca
WE
tWR
DQS
Da0
DQ
Da1
Da2
Da3
DM
COMMAND
WRITE
PRE
CHARGE
10122B32R.B
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ESMT
M53S128324A (2E)
Write Interrupted by Precharge & DM (@BL=8)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAa
BAb
A10/AP
ADDR
(A0~An)
Cb
Ca
WE
DQS
Da0
DQ
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2
Db3
Db4
Db5
DM
tWR
CO MMA ND
WRITE
PRE
CHARGE
WRITE
10122B32R.B
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ESMT
M53S128324A (2E)
Write Interrupted by a Read (@BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
WE
DQS
DQ
Hi-Z
Hi-Z
Da0
Da1
Da2
Da3
Da4
Da5
Qb0
Qb 1
Qb2
Qb3
Qb4
Qb5
Maskecd by DM
DM
tWTR
COMMAND
WRITE
READ
10122B32R.B
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ESMT
M53S128324A (2E)
DM Function (@BL=8) only for write
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0, BA1
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
DQS(CL=3)
DQ(CL=3)
Da 0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
DM
COMMAND
WRITE
10122B32R.B
Elite Semiconductor Memory Technology Inc.
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ESMT
M53S128324A (2E)
Deep Power Down Mode Entry & Exit Cycle
Note:
DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM:
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of
the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the
device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1)
2)
3)
The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the
clock. While CKE is low.
Clock must be stable before exited deep power down mode.
Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) 200μs wait time is required to exit from Deep Power Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
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ESMT
M53S128324A (2E)
Mode Register Set
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CLK
HIGH
CKE
CS
RAS
CAS
WE
BA0, BA1
KEY
A10/AP
KEY
ADDRESS KEY
KEY
ADDR
(A0~An)
Hi-Z
DQS
tRP
tMRD
DQs
Hi-Z
DM
CO MMAND
Precharge
Command
All Bank
Any
Command
10122B32R.B
MRS
Command
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ESMT
M53S128324A (2E)
Simplified State Diagram
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Elite Semiconductor Memory Technology Inc.
Write = Write w/o Auto Precharge
Write A = Write with Auto Precharge
Read = Read w/o Auto Precharge
Read A = Read with Auto Precharge
PRE = Precharge
BST = Burst Terminate
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power-Down
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ESMT
PACKING
M53S128324A (2E)
DIMENSIONS
144-BALL FBGA DDR DRAM (12x12mm)
Symbol
A
A1
Φb
D
E
D1
E1
e
aaa
bbb
ddd
eee
fff
MD/ME
Dimension in mm
Min
Norm
Max
1.14
1.40
0.30
0.35
0.40
0.40
0.45
0.50
11.90
12.00
12.10
11.90
12.00
12.10
8.80
8.80
0.80
0.10
0.10
0.12
0.15
0.08
12/12
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.049
0.055
0.012
0.014
0.016
0.016
0.018
0.020
0.469
0.472
0.476
0.469
0.472
0.476
0.346
0.346
0.031
0.004
0.004
0.005
0.004
0.006
12/12
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ESMT
M53S128324A (2E)
Revision History
Revision
Date
1.0
2013.01.04
Elite Semiconductor Memory Technology Inc.
Description
Original
Publication Date : Jan. 2013
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ESMT
M53S128324A (2E)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.
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