LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 LP8728-Q1 Quad-Output Step-Down DC/DC Converter Check for Samples: LP8728-Q1 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • LP8728-Q1 is an Automotive Grade Product that is AECQ-100 Grade 1 Qualified Four High Efficiency Step-Down DC/DC Converters: – 93% Peak Efficiency ( VIN = 5.0V, VOUT 3.3V) – Max Output Current 1.0A – Forced PWM Operation – Soft-Start Control – VOUT1 = 3.3V – VOUT2 = 1.25V – VOUT3 = 1.8V or 2.65V (pin selectable) – VOUT4 = 1.8V Separate Enable Inputs for each Converter Control Separate Power Good Outputs for each Converter Output Over-Current and Input Over-Voltage Protection Over-Temperature Protection Under-Voltage Lockout (UVLO) 28-pin 0.5 mm Pitch QFN Package FPGA, DSP Core Power Processor Power for Mobile Devices Peripheral I/O Power Automotive Safety Cameras Automotive Infotainment DESCRIPTION The LP8728-Q1 is a quad-output Power Management Unit, optimized for low-power FPGAs, microprocessors, and DSPs. This device integrates four highly efficient step-down DC/DC converters into one package. All the converters operate above the AM band with a fixed 3.2 MHz switching frequency. Each buck converter's high-side switch turn-on time is phase shifted to minimize input current spikes. The protection features include output short-circuit protection, switch current limits, input over-voltage protection, input under-voltage lockout, and thermal shutdown functions. During startup, the device controls the output slew rate to minimize output voltage overshoot and the input inrush current. The device comes in a 5 x 5 x 0.8 mm 28-pin QFN package with 0.5 mm pitch. TYPICAL APPLICATION CIRCUIT VIN VIN 10 μF VIN_B1 AVDD 1 μF 1.5 μH VOUT1 10 μF SW_B1 BYP FB_B1 1 μF VIN 10 μF VIN_B2 VDDIO 1.5 μH VOUT2 10 μF SW_B2 FB_B2 LP8728 PG_B1 PG_B3 Micro Controller VIN 10 μF VIN_B3 PG_B2 1.5 μH PG_B4 FB_B3 EN_B1 SW_B3 VOUT3 10 μF EN_B2 VIN 10 μF VIN_B4 EN_B3 GND_B3 GND_B4 GND_B2 AGND DEFSEL GND_B1 EN_B4 FB_B4 SW_B4 1.5 μH VOUT4 10 μF 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating ambient temperature range (unless otherwise noted). PARAMETER VALUE UNIT VIN Voltage on power pins (AVDD, VIN_Bx) –0.3 to 6.0 V VFB Voltage on feedback pins (FB_Bx) –0.3 to 6.0 V (GND_Bx – 0.2 V) to (VIN_Bx + 0.2 V) with 6.0V max V (AGND – 0.2V) to (AVDD + 0.2 V) with 6.0 max V VSW Voltage on buck converter switch pins (SW_Bx) VDIG Voltage on digital pins (PG_Bx, EN_Bx, DEFSEL) VBYP Voltage on BYP pin TJ(MAX) Maximum operating junction temperature (3) TSTG Storage temperature range –0.3 to 2.0 V +150 °C –65 to +150 °C Electrostatic discharge (HBM) 2000 V Electrostatic discharge (CDM) 750 V (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). THERMAL PROPERTIES QFN-28 package thermal properties PARAMETER θJA (1) VALUE Junction-to-Ambient Thermal Resistance (1) UNIT 36.3 °C/W Calculated using 4-layer standard JEDEC thermal test board with 5 thermal vias between the die attach pad in the first copper layer and second copper layer. RECOMMENDED OPERATING CONDITIONS (1) Over operating ambient temperature range (unless otherwise noted). PARAMETER MIN NOM MAX 5.0 5.5 V +125 °C 12 µF VIN Input Voltage on AVDD, VIN_B1, VIN_B2, VIN_B3 and VIN_B4 Pins 4.5 TA Operating ambient temperature range (2) –40 COUT Effective output capacitance during operation. Min value over TA –40°C to 125°C. 5.0 10 CIN Effective input capacitance during operation. 4.5V ≤ VIN_Bx ≤ 5.5V. Min value over TA –40°C to 125°C. 2.5 10 L Effective inductance during operation Min value over TA –40°C to 125°C. 0.47 1.5 (1) (2) 2 UNIT µF 2 µH All voltage values are with respect to network ground terminal. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 ELECTRICAL CHARACTERISTICS (1) (2) Typical values and limits appearing in normal type apply for TA = 25ºC. Unless otherwise noted, VIN = 5.0 V. Limits appearing in boldface type apply over junction temperature range, TJ = –40 ºC to 125ºC. PARAMETER ISHDN Shutdown Supply Current into Power Connections IOP Operating Current TEST CONDITIONS MIN TYP MAX EN_Bx = 0V 1.0 6 All buck-converters active, IOUT = 0mA 20 UNIT μA mA LOGIC INPUTS (EN_Bx, DEFSEL) VIL Input Low Level 0.4 V VIH Input High Level 1.6 RPD_DI EN_Bx and DEFSEL Internal Pulldown Resistance 300 TH_MIN Minimum EN_Bx High Time 1 ms TL_MIN Minimum EN_Bx Low Time 10 µs V 520 820 kΩ LOGIC OUTPUTS (PG_Bx) VOL Output Low Level RPU Recommended Pull-up Resistor ISINK = 3mA 0.4 V 10 kΩ BUCK CONVERTERS VOUT1 Output Voltage for Buck 1 Fixed voltage 3.3 V VOUT2 Output Voltage for Buck 2 Fixed voltage 1.25 V DEFSEL = 1 2.65 DEFSEL = 0 1.8 VOUT3 Output Voltage for Buck 3 VOUT4 Output Voltage for Buck 4 VFB_Bx Output voltage accuracy Fixed voltage V 1.8 –3 V 3 % Line Regulation 4.5 V ≤ VIN_Bx ≤ 5.5 V ILOAD = 10 mA 3 mV Load Regulation VIN = 5.0 V 100 mA ≤ ILOAD ≤ 900 mA 3 mV IOUT Output Current DC load FSW Switching Frequency GBW Gain Bandwidth ILIMITP High Side Switch Current Limit ILIMITN Low Side Switch Current Limit Reverse current 500 RDSONP Pin-Pin Resistance for PFET IOUT = 200 mA RDSONN Pin-Pin Resistance for NFET IOUT = 200 mA ILK_SW Switch Pin Leakage Current VOUT = 1.8V RPD_FB Pull-down Resistor from FB_Bx pin to GND Only active when converter disabled. KRAMP Slew Rate Control DEFSEL from 0 to 1 TSTART Startup Time Time from first EN_Bx high to start of switching KSTART Soft-Start VOUT Slew Rate ΔVOUT 3.03 3.2 1000 mA 3.37 MHz 300 1200 40 1500 kHz 1800 mA 210 300 mΩ 140 240 mΩ 1 µA 100 Ω 70 mA 10 mV/µs 420 µs 18 mV/µs VOLTAGE MONITORING Power good threshold for voltage rising 93.5 96 98 % Power good threshold for voltage falling 91 93 95 % Input Over-voltage Protection Trigger Point Voltage monitored on AVDD Pin, voltage rising 5.5 5.7 5.9 Input Under-voltage Lockout (UVLO) turn-on threshold. Voltage monitored on AVDD Pin, voltage falling VPG Power Good Threshold Voltage VOVP VUVLO (1) (2) Hysteresis Hysteresis 80 4.35 80 V mV V mV All voltage values are with respect to network ground terminal. Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5.0 V and TJ = 25ºC. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 3 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS(1)(2) (continued) Typical values and limits appearing in normal type apply for TA = 25ºC. Unless otherwise noted, VIN = 5.0 V. Limits appearing in boldface type apply over junction temperature range, TJ = –40 ºC to 125ºC. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN AND MONITORING TSD Thermal Shutdown Threshold, Temperature rising 150 Hysteresis °C 20 SYSTEM CHARACTERISTICS (1) (2) (3) Typical values and limits appearing in normal type apply for TA = 25ºC. Unless otherwise noted, VIN = 5.0 V. Limits appearing in boldface type apply over junction temperature range, TJ = –40 ºC to 125ºC. PARAMETER (1) (2) (3) 4 TYP MAX UNIT 70 mV IOUT 90% max load → 10% max load, 1µs load step 70 mV Line Transient Response VIN_Bx stepping 4.5V ↔ 5.5V tr = tf = 10 µs, IOUT = 400 mA 20 mV Output voltage ripple COUT ESR = 10 mΩ, IOUT = 200 mA 10 mVPP VOUT = 3.3V, IOUT = 300 mA 94 VOUT = 2.65V, IOUT = 300 mA 92 VOUT = 1.8V, IOUT = 300 mA 89 VOUT = 1.2V, IOUT = 300 mA 85 ΔVOUT η MIN IOUT 10% max load → 90% max load, 1µs load step Load Transient Response VRIPPLE TEST CONDITIONS Efficiency % All voltage values are with respect to network ground terminal. Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5.0 V and TJ = 25ºC. System Characteristics are highly dependent on external components and pcb layout. System Characteristics are verified using inductor type: TOKO MDT2520-CN1R5M, input and output capacitor type: MuRata GRM21BR71A106KE51L. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 PIN ASSIGNMENTS VIN_B2 SW_B2 GND_B2 GND_B1 SW_B1 VIN_B1 EN_B1 TOP VIEW 7 6 5 4 3 2 1 PIN 1 ID FB_B2 8 28 FB_B1 EN_B2 9 27 PG_B1 PG_B2 10 26 AVDD DEFSEL 11 25 BYP PG_B3 12 24 AGND EN_B3 13 23 PG_B4 FB_B3 14 22 FB_B4 16 17 18 19 20 21 GND_B3 GND_B4 SW_B4 VIN_B4 EN_B4 VIN_B3 15 SW_B3 DAP Figure 1. Connection Diagram Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 5 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com Table 1. PIN DESCRIPTIONS 6 PIN # PIN NAME TYPE 1 EN_B1 D/I DESCRIPTION 2 VIN_B1 P Positive power supply input for Buck 1 3 SW_B1 P Switch node for Buck 1 4 GND_B1 G Power ground for Buck 1 5 GND_B2 G Power ground for Buck 2 6 SW_B2 P Switch node for Buck 2 7 VIN_B2 P Positive power supply input for Buck 2 8 FB_B2 A Feedback pin for Buck 2. Referenced against AGND. Enable buck 1 9 EN_B2 D/I Enable Buck 2 10 PG_B2 D/O Open-drain Power Good output for Buck 2 11 DEFSEL D/I Buck 3 output voltage selection pin 12 PG_B3 D/O Open-drain Power Good output for Buck 3 13 EN_B3 D/I Enable buck 3 14 FB_B3 A Feedback pin for Buck 3. Referenced against AGND. 15 VIN_B3 P Positive power supply input for Buck 3 16 SW_B3 P Switch node for Buck 3 17 GND_B3 G Power ground for Buck 3 18 GND_B4 G Power ground for Buck 4 19 SW_B4 P Switch node for Buck 4 20 VIN_B4 P Positive power supply input for Buck 4 21 EN_B4 D/I Enable Buck 4 22 FB_B4 A 23 PG_B4 D/O Feedback pin for Buck 4. Referenced against AGND. 24 AGND G Analog ground 25 BYP A Internal 1.8V supply voltage capacitor pin. A ceramic low ESR 1.0 μF capacitor should be connected from this pin to AGND. The BYP voltage is generated internally, do not supply or load this pin externally. 26 AVDD P Analog positive power supply pin (VIN level) 27 PG_B1 D/O 28 FB_B1 A DAP Die Attachment Pad Open-drain Power Good output for Buck 4 Open-drain Power Good output for Buck 1 Feedback pin for Buck 1. Referenced against AGND. Exposed die attachment pad should to be connected to GND plane with thermal vias to improve the thermal performance of the system. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 FUNCTIONAL BLOCK DIAGRAM VIN AVDD 1 µF VIN_B1 VIN BYP 10 µF LDO 1 µF Buck1 (Active Pulldown) Oscillator FB_B1 SW_B1 1.5 µH UVLO 10 µF VOUT1 ( 3.3V ) Reference Voltage VIN_B2 Thermal Shutdown VIN 10 µF OTP Buck2 (Active Pulldown) PG_B1 FB_B2 SW_B2 1.5 µH 10 µF PG_B2 PG_B3 VIN_B3 VOUT2 ( 1.25V ) VIN 10 µF PG_B4 Buck3 (Active Pulldown) DEFSEL Control Logic FB_B3 SW_B3 EN_B1 1.5 µH 10 µF VOUT3 ( 1.8V / 2.65V ) EN_B2 VIN_B4 EN_B3 VIN 10 µF Buck4 (Active Pulldown) EN_B4 FB_B4 SW_B4 1.5 µH VOUT4 ( 1.8V ) GND_B4 GND_B3 GND_B2 GND_B1 AGND 10 µF Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 7 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS Unless otherwise noted, VIN = 5.0V, TA = +25°C 100 90 EFFICIENCY (%) 80 VOUT1 100mV/div 70 60 SW_B1 5V/div 50 40 3.3V 30 2.65V 20 1.8V 10 1.25V Inductor current 500mA/div 0 0 100 200 300 400 500 600 700 800 900 200s/div 1000 OUTPUT CURRENT (mA) C001 C000 Figure 2. EFFICIENCY vs OUTPUT CURRENT Figure 3. SHORT-CIRCUIT WAVEFORMS 3280 3260 3240 EN_B1 3220 PG_B1 fSW (Hz) 3200 3180 3160 3140 3120 VOUT1 1V/div 3100 3080 3060 -60 -40 -20 0 20 40 60 80 100 120 100s/div 140 TEMPERATURE (C) C012 C012 Figure 4. SWITCHING FREQUENCY vs TEMPERATURE Figure 5. STARTUP DELAY VOUT1 50mV/div VOUT1 50mV/div VIN 1V/div IOUT 500mA/div 10s/div 40s/div C013 Figure 6. LOAD TRANSIENT RESPONSE, IOUT from 0mA to 1A 8 Submit Documentation Feedback C014 Figure 7. LINE TRANSIENT RESPONSE, VIN from 4.5V to 5.5V Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 TYPICAL CHARACTERISTICS (continued) 3.33 3.33 3.32 3.32 3.31 3.31 VOUT1 (V) VOUT1 (V) Unless otherwise noted, VIN = 5.0V, TA = +25°C 3.30 3.29 3.28 3.29 +125°C 3.28 +125°C +25°C +25°C 3.27 3.30 3.27 -40°C -40°C 3.26 3.26 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IOUT1 (A) 1.0 4.4 4.5 4.7 1.26 1.26 1.25 1.25 VOUT2 (V) 1.27 1.24 1.23 5.0 5.1 5.2 5.3 5.4 5.6 1.24 1.23 +25°C +125°C +25°C 1.21 -40°C -40°C 1.20 1.20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IOUT2 (A) 1.0 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 SUPPLY VOLTAGE (V) C008 Figure 10. BUCK2 LOAD REGULATION 5.6 C009 Figure 11. BUCK2 LINE REGULATION 5.0 25 + 125°C 4.0 + 85°C 3.5 + 25°C 3.0 - 40°C 24 SUPPLY CURRENT (mA) 4.5 ISHDN (A) 5.5 C007 1.22 +125°C 1.21 4.9 Figure 9. BUCK1 LINE REGULATION 1.27 1.22 4.8 SUPPLY VOLTAGE (V) Figure 8. BUCK1 LOAD REGULATION VOUT2 (V) 4.6 C006 2.5 2.0 23 22 21 20 19 18 - 40°C 17 + 25°C 0.5 16 + 125°C 0.0 15 1.5 1.0 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 SUPPLY VOLTAGE (V) 5.6 4.4 4.5 Figure 12. SHUTDOWN CURRENT CONSUMPTION 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 SUPPLY VOLTAGE (V) C010 5.6 C011 Figure 13. ACTIVE MODE CURRENT CONSUMPTION (ALL BUCKS ACTIVE) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 9 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VIN = 5.0V, TA = +25°C SW1 SW2 SW3 SW4 80ns/div C013 Figure 14. SWITCH TURN ON PHASE SHIFTING 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 OPERATION DESCRIPTION The LP8728 has four integrated high-efficiency buck converters. Each buck converter has individual enable input and power good output pins. When the first enable pin is pulled high there is a 420-µs startup delay when the device wakes up from shutdown mode and all internal reference blocks are started up. Once reference blocks have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit the inrush current during startup. Once a buck output reaches 96% (typ.) of the desired output voltage, the powergood pin is pulled high (see Figure 15). When at least one buck core is active, the remaining buck converters will start up without any startup delay. If the output voltage drops below 93% (typ.) of desired voltage due to, for example, an overload condition, the corresponding power-good pin is pulled low. The power-good signal is always held low for at least 50 ms. When the enable pin is pulled low, the corresponding buck converter's power good signals are set low, and the buck converter is instantly shut down. An output capacitor is then discharged through an internal 70Ω (typ.) pull-down resistor. The pull-down resistor is connected between buck feedback pin and ground and is only active when the enable pin is set low. When all enable signals are pulled low, the LP8728-Q1 enters a low-current shutdown mode. Buck Information The buck converters are operated in forced PWM mode. Even with light load a minimum switching pulse is generated with every switching cycle. Each buck converter's high-side switch turn-on time is phase shifted to minimize the input current ripple (see Figure 14). Features The following features are supported for all converters: • • • • • • Synchronous rectification Current mode feedback loop with PI compensator Forced PWM operation Soft start Power-good output Over-voltage comparator In addition to the aforementioned features, buck3 output voltage can be selected with the DEFSEL pin. If the DEFSEL pin is pulled low, VOUT3 is set to 1.8 V. If DEFSEL is pulled high, VOUT3 is set to 2.65V. 96% 93% Active pulldown VOUTx Overload condition 5% EN_Bx PG_Bx TSTART TRAMP 50ms Figure 15. Buck Converter Startup and Shutdown Thermal Shutdown (TSD) Thermal shutdown function shuts down all buck regulators if the device's junction temperature TJ rises above 150ºC (typ.). All power-good signals are pulled low 5 ms before buck regulators are shut down. Once TJ falls below 130ºC (typ.), the LP8728 will automatically start up the buck regulators. There is a 2-second safety delay included in the restart function. Buck regulators are not restarted until 2 seconds have elapsed after TJ falls below 130ºC (typ.). To minimize the inrush current during restarting, regulators are started in a buck1 → buck2 → buck3 → buck4 sequence. A 500-µs delay is included between each buck startup. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 11 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com 150°C Junction 130°C Temperature TJ TSD (Internal Signal) PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 2s 500us 500us 500us Figure 16. TSD Timing Diagram Under-Voltage Lockout (UVLO) Under-voltage lockout pulls the PG_Bx pins low if the input voltage drops below 4.35V (typ.) (Figure 17). PG_Bx pins are always held low for at least 50 ms. Once an under-voltage condition has lasted for 5 ms, all buck converters are shut down. Buck converters are restarted once the input voltage rises above UVLO level. If an under-voltage condition has lasted more than 5 ms, but less than 50 ms, PG_Bx pins are released high once 50 ms has elapsed and corresponding output voltage has settled. If an over-voltage condition has lasted more than 50 ms, power-good signals are released high once corresponding output voltage has settled. If an under-voltage condition lasts less than 5 ms, the buck converters are not shut down. Even in this case PG_Bx pins are held low for 50 ms. Regulators are always restarted in a buck1 → buck2 → buck3 → buck4 sequence. A 500-µs delay is included between each buck startup. 5.0V VIN 4.35V UVLO PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms Figure 17. UVLO Operation 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 Over-Voltage Protection (OVP) Over-voltage protection protects the device in case of an over-voltage condition. If input voltage exceeds 5.7V (typ.), all PG_Bx pins are pulled low. PG_Bx pins are always held low for at least 50 ms. Once the PG_Bx pins are pulled low, the system has 5 ms time to power down. After over-voltage condition has lasted for 5 ms, all buck converters are shut down. Buck converters are restarted once input voltage falls below 5.62V (typ). Regulators are started in a buck1 → buck2 → buck3 → buck4 sequence. A 500-µs delay is included between each buck startup. If an over-voltage condition lasted more than 5 ms, but less than 50 ms, the PG_Bx pins are released high once 50 ms has elapsed and corresponding output voltage has settled (Figure 18). VIN 5.7V OVP PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 500μs 500μs 500μs 50 ms Figure 18. OVP Duration less than 50 ms If an over-voltage condition has lasted more than 50 ms, power-good signals are released high once corresponding output voltage has settled. Regulators are started in a buck1 → buck2 → buck3 → buck4 sequence. A 500-µs delay is included between each buck startup (Figure 19). If an over-voltage condition has lasted less than 5 ms, buck converters are not shut down. Even in this case the PG_Bx pins are held low for 50 ms. Note: Since regulators are allowed to operate for 5 ms during over-voltage condition it is the system designer’s responsibility to verify that input voltage doesn’t exceed limits stated in the ABSOLUTE MAXIMUM RATINGS (1) (2) table. Exceeding these limits may cause permanent damage to the device. (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 13 LP8728-Q1 SNVS972 – AUGUST 2013 www.ti.com VIN 5.7V OVP PG_B1 PG_B2 PG_B3 PG_B4 VOUT1 VOUT3 VOUT4 VOUT2 5 ms 50 ms 500μs 500μs 500μs Figure 19. OVP Duration more than 50 ms 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 LP8728-Q1 www.ti.com SNVS972 – AUGUST 2013 APPLICATION INFORMATION Inductor The four converters operate with 1.5 µH inductors. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductor directly influences the efficiency of the converter. Therefore, an inductor with the lowest dc resistance should be selected for the highest efficiency. The inductor should have a saturation current rating equal or higher than the high-side switch current limit (1500 mA) to minimize radiated noise use shielded inductor. The inductor should be connected to the SW pin as close to the IC as possible. Input and Output Capacitors Because buck converters have a discontinuous input current, a low ESR input capacitor is required for best input-voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. Each dcdc converter requires a 10-µF ceramic input capacitor on its input pin VIN_Bx. The input capacitor can be increased without any limit for better input voltage filtering. A small 100-nF capacitor can be used in parallel to minimize high-frequency interferences. Input capacitors should be placed as close to VIN_Bx pins as possible. Routing from input capacitor to VIN_Bx pins should be done on top layer without using any vias. An output capacitor with a typical value of 10 µF is recommended for each converter. Ceramic capacitors with low ESR value have lowest output voltage ripple and are recommended. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied DC voltage (DC bias effect). The capacitance value can fall below half of the nominal capacitance. This needs to be taken into consideration and, if necessary, use a capacitor with higher value or higher voltage rating. Table 2. Recommended External Components Component Description Value Type Example CIN_B1,2,3,4 Buck regulator input capacitor 10µF Ceramic, 10V, X7R MuRata, GRM21BR71A106KE51L COUT_B1,2,3,4 Buck regulator output capacitor 10µF Ceramic, 10V, X7R MuRata, GRM21BR71A106KE51L CAVDD AVDD pin input capacitor 1µF Ceramic, 10V, X7R MuRata, GRM188R71A105KA61D CBYP Internal LDO bypass capacitor 1uF Ceramic, 10V, X7R MuRata, GRM188R71A105KA61D Buck regulator inductor 1.5µH ISAT>1.5A, DCR<100mΩ TOKO MDT2520-CN1R5M LSW1,2,3 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 15 PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LP8728QSQE-A/NOPB ACTIVE WQFN RSG 28 250 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 8728Q-A LP8728QSQX-A/NOPB ACTIVE WQFN RSG 28 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 8728Q-A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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