ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 HIGH SPEED QUAD DIGITAL ISOLATORS FEATURES 1 • • • • • • • Selectable Failsafe Output (ISO7240CF) 25 and 150-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew; 1 ns Max – Low Pulse-Width Distortion (PWD); 2 ns Max – Low Jitter Content; 1 ns Typ at 150 Mbps Typical 25-Year Life at Rated Working Voltage (see application note SLLA197 and Figure 17) 4000-Vpeak Isolation, 560-Vpeak VIORM – UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1, IEC 60950-1 and CSA Approved • 4 kV ESD Protection Operate With 3.3-V or 5-V Supplies High Electromagnetic Immunity (see application report SLLA181) –40°C to 125°C Operating Range APPLICATIONS • • • • Industrial Fieldbus Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same direction and one channel in opposition. The ISO7242 has two channels in each direction. The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter or the additional propagation delay. The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the output. When the inputs are disabled, the outputs are set by the CTRL pin. These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V, 5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. These devices are characterized for operation over the ambient temperature range of –40°C to 125°C. VCC1 GND1 INA INB INC IND DISABLE GND1 ISO7240CF 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 ISO7240 VCC2 VCC1 GND2 GND1 OUTA INA INB OUTB INC OUTC OUTD IND CTRL NC GND2 GND1 1 2 3 4 5 6 7 8 ISO7241 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC OUTD EN GND2 VCC1 GND1 INA INB INC OUTD EN1 GND1 1 2 3 4 5 6 7 8 ISO7242 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC IND EN2 GND2 VCC1 GND1 INA INB OUTC OUTD EN1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB INC IND EN2 GND2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. Device Function Table ISO724x INPUT VCC OUTPUT VCC PU (1) (1) INPUT (IN) OUTPUT ENABLE (EN) OUTPUT (OUT) H H or Open H L H or Open L PU X L Z Open H or Open H PD PU X H or Open H PD PU X L Z PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level Table 2. ISO7240CF Function Table VCC1 VCC2 DATA INPUT (IN) DISABLE INPUT (DISABLE) FAILSAFE CONTROL INPUT (CTRL) DATA OUTPUT (OUT) PU PU H L or Open X H PU PU L L or Open X L X PU X H H or Open H X PU X H L L PD PU X X H or Open H PD PU X X L L AVAILABLE OPTIONS PRODUCT SIGNALING RATE INPUT THRESHOLD CHANNEL CONFIGURATION MARKED AS ISO7240CDW 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7240CF 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7240MDW 150 Mbps Vcc/2 (CMOS) ISO7240M ISO7241CDW 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7241C ISO7241MDW 150 Mbps Vcc/2 (CMOS) ISO7241M ISO7242CDW 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7242C ISO7240C 4/0 ISO7240CF 3/1 2/2 ISO7242MDW (1) 2 150 Mbps Vcc/2 (CMOS) ISO7242M ORDERING NUMBER (1) ISO7240CDW (rail) ISO7240CDWR (reel) ISO7240CFDW (rail) ISO7240CFDWR (reel) ISO7240MDW (rail) ISO7240MDWR (reel) ISO7241CDW (rail) ISO7241CDWR (reel) ISO7241MDW (rail) ISO7241MDWR (reel) ISO7242CDW (rail) ISO7242CDWR (reel) ISO7242MDW (rail) ISO7242MDWR (reel) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS (1) (2) VCC Supply voltage VI Voltage at IN, OUT, EN, DISABLE, CTRL , VCC1, VCC2 IO Output current ESD Electrostatic Field-Induced-Charged Device discharge Model TJ Maximum junction temperature Human Body Model Machine Model (1) (2) JEDEC Standard 22, Test Method A114-C.01 JEDEC Standard 22, Test Method C101 VALUE UNIT –0.5 to 6 V –0.5 to 6 V ±15 mA ±4 All pins kV ±1 ANSI/ESDS5.2-1996 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN (1) VCC Supply voltage IOH High-level output current IOL Low-level output current tui Input pulse width 1/tui Signaling rate VIH High-level input voltage (IN) VIL Low-level input voltage (IN) VIH High-level input voltage (IN, DISABLE, CTRL, EN) VIL Low-level input voltage (IN, DISABLE, CTRL, EN) TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification (1) (2) , VCC1, VCC2 TYP MAX 3.15 5.5 4 –4 40 ISO724xM 6.67 5 ISO724xC 0 30 (2) 25 ISO724xM 0 200 (2) 150 ISO724xC V mA mA ISO724xC ISO724xM UNIT ns Mbps 0.7 VCC VCC V 0 0.3 VCC V 2 VCC V 0 0.8 V 150 °C 1000 A/m For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Typical value at room temperature and well-regulated power supply. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 3 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION , over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 3 7 10.5 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 6.5 10 12 18 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 10 16 15 24 VI = VCC or 0 V, All channels, no load, EN2 at 3 V 15 22 17 25 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 13 20 18 28 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 10 16 15 24 UNIT SUPPLY CURRENT ISO7240C/M ICC1 ISO7241C/M ISO7242C/M ISO7240C/M ICC2 ISO7241C/M ISO7242C/M Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 (1) 4 EN at 0 V, Single channel µA 0 IOH = –4 mA, See Figure 1 VCC – 0.8 IOH = –20 µA, See Figure 1 VCC – 0.1 V IOL = 4 mA, See Figure 1 0.4 IOL = 20 µA, See Figure 1 0.1 150 IN from 0 V to VCC mV 10 –10 25 V µA 2 pF 50 kV/µs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 12 µs twake Wake time from input disable See Figure 4 15 µs Peak-to-peak eye-pattern jitter 150 Mbps NRZ data input, Same polarity input on all channels, See Figure 6 1 ns (1) (2) (3) ISO724xC 42 UNIT Propagation delay tjit(pp) 18 MAX tPLH, tPHL 2.5 See Figure 1 10 ISO724xM 23 1 ISO724xC (2) 8 ISO724xM (3) 0 ISO724xC 3 2 ISO724xM 0 1 2 See Figure 1 ISO724xM 2 ns ns ns ns 2 See Figure 2 ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 5 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 3 7 10.5 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 6.5 10 12 18 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 10 16 15 24 9.5 15 10.5 17 UNIT SUPPLY CURRENT ISO7240C/M ICC1 ISO7241C/M ISO7242C/M ISO7240C/M ICC2 ISO7241C/M ISO7242C/M Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps Quiescent 25 Mbps VI = VCC or 0 V, All channels, no load, EN2 at 3 V VI = VCC or 0 V, All channels, no load, EN2 at 3 V 8 13 11.5 18 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 6 10 9 14 EN at 0 V, Single channel 0 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current VOH High-level output voltage IOH = –4 mA, See Figure 1 IOH = –20 µA, See Figure 1 VCC – 0.8 V VCC – 0.1 0.4 IOL = 20 µA, See Figure 1 0.1 Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 6 VCC – 0.4 ISO724x (5-V side) IOL = 4 mA, See Figure 1 VOL (1) ISO7240 µA 150 IN from 0 V to VCC mV 10 –10 25 V µA 2 pF 50 kV/µs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TYP Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion(1) |tPHL – tPLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 18 µs twake Wake time from input disable See Figure 4 15 µs Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data input, Same polarity input on all channels, See Figure 6 1 ns (1) (2) (3) 50 UNIT PWD tjit(pp) 20 MAX Propagation delay ISO724xC See Figure 1 MIN tPLH, tPHL 3 ISO724xM 12 29 1 ISO724xC (2) 10 ISO724xM (3) 0 ISO724xC 5 3 ISO724xM 0 1 2 See Figure 1 ISO724xM 2 ns ns ns ns 2 See Figure 2 ns ns Also known as pulse skew tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 7 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.5 1 3 5 4 7 6.5 11 6 10 9 14 15 22 17 25 13 20 18 28 10 16 15 24 UNIT SUPPLY CURRENT ISO7240C/M ISO7241C/M ICC1 Quiescent VI = VCC or 0 V, All channels, no load, EN2 at 3 V 25 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 25 Mbps ISO724C/M Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 25 Mbps ISO7240C/M ISO7241C/M ICC2 Quiescent VI = VCC or 0 V, All channels, no load, EN2 at 3 V 25 Mbps Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 25 Mbps ISO7242C/M Quiescent VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V 25 Mbps mA mA mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current VOH High-level output voltage EN at 0 V, Single channel IOH = –4 mA, See Figure 1 IOH = –20 µA, See Figure 1 VCC – 0.4 ISO724x (5-V side) VCC – 0.8 V VCC – 0.1 0.4 IOL = 20 µA, See Figure 1 0.1 Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 8 ISO7240 IOL = 4 mA, See Figure 1 VOL (1) µA 0 150 IN from 0 V to VCC mV 10 –10 25 V µA 2 pF 50 kV/µs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 22 51 UNIT tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion(1) |tPHL – tPLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 12 µs twake Wake time from input disable See Figure 4 15 µs Peak-to-peak eye-pattern jitter 150 Mbps NRZ data input, Same polarity input on all channels, See Figure 6 1 ns tjit(pp) (1) (2) (3) ISO724xC 3 See Figure 1 12 ISO724xM 30 1 ISO724xC (2) 10 ISO724xM (3) 0 ISO724xC 5 2.5 ISO724xM 0 1 2 See Figure 1 ISO724xM 2 ns ns ns ns 2 See Figure 2 ns ns Also known as pulse skew tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 9 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240C/M ISO7241C/M ICC1 Quiescent 25 Mbps Quiescent 25 Mbps ISO7242C/M Quiescent 25 Mbps ISO7240C/M ISO7241C/M ICC2 Quiescent 25 Mbps Quiescent 25 Mbps ISO7242C/M Quiescent 25 Mbps VI = VCC or 0 V, all channels, no load, EN2 at 3 V 0.5 1 3 5 4 7 6.5 11 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 6 10 9 14 VI = VCC or 0 V, all channels, no load, EN2 at 3 V 9.5 15 10.5 17 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 8 13 11.5 18 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V 6 10 9 14 EN at 0 V, single channel 0 VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V mA mA mA mA ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 (1) 10 IOH = –4 mA, See Figure 1 VCC – 0.4 IOH = –20 µA, See Figure 1 VCC – 0.1 µA V IOL = 4 mA, See Figure 1 0.4 IOL = 20 µA, See Figure 1 0.1 150 IN from 0 V or VCC mV 10 –10 25 V µA 2 pF 50 kV/µs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 25 56 UNIT tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss See Figure 3 18 µs twake Wake time from input disable See Figure 4 15 µs Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data input, same polarity input on all channels, See Figure 6 1 ns tjit(pp) (1) (2) (3) ISO724xC 4 See Figure 1 12 ISO724xM 34 1 ISO724xC (2) 10 ISO724xM (3) 0 ISO724xC 5 3.5 ISO724xM 0 1 2 See Figure 1 ISO724xM 2 ns ns ns ns 2 See Figure 2 ns ns 15 20 15 20 15 20 15 20 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 11 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms Vcc Vcc ISOLATION BARRIER 0V RL = 1 kW ±1% IN Input Generator VI OUT EN Vcc/2 VI t PZL VO VO CL Vcc/2 0V t PLZ Vcc 0.5 V 50% NOTE B 50 W VOL 3V ISOLATION BARRIER NOTE A IN Input Generator VI Vcc OUT VO Vcc/2 VI Vcc/2 0V EN 50 W t PZH CL NOTE B RL = 1 kW ±1% VO VOH 50% 0.5 V t PHZ 0V NOTE A A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) VI 0V or VCC1 VCC1 ISOLATION BARRIER VCC1 IN 2.7 V VI OUT 0V VO tfs VOH CL NOTE B VO 50% fs low VOL A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. 3V Generator IN ( Note A) DISABLE ISOLATION BARRIER Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms OUT t wake ISOLATION BARRIER DISABLE ( Note B) 50 % VO 0V V CC 2 OUT VO VI V CC2/2 0V t wake CTRL CL Input Generator VCC2 CL 50 W IN VCC2/2 0V 0V 0V VI CTRL Input VI VCC2 VO VI 3V V CC2 (Note B ) 50 W VO ( Note A ) 50 % 0V NOTE: Which ever test yields the longest time is used in this datasheet A. Whichever test yields the longest time is used in this data sheet. Figure 4. Wake Time From Input Disable Test Circuit and Voltage Waveforms Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 13 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC1 VCC2 ISOLATION BARRIER C = 0.1 mF± 1% IN S1 GND1 C = 0.1 mF± 1% OUT NOTE B Pass-fail criteria: Output must remain stable VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform VCC1 DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s. Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 14 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER L(I01) TEST CONDITIONS MIN TYP MAX UNIT Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance Input to output CI Input capacitance to ground L(I02) >1012 Ω VI = 0.4 sin (4E6πt) 2 pF VI = 0.4 sin (4E6πt) 2 pF DEVICE I/O SCHEMATICS Enable VCC Output Input VCC VCC VCC VCC VCC 1 MW 500 W IN EN 8W 500 W OUT 13 W 1 MW REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Low-K Thermal Resistance (1) 168 High-K Thermal Resistance 96.1 UNIT θJA Junction-to-air θJB Junction-to-Board Thermal Resistance 61 °C/W θJC Junction-to-Case Thermal Resistance 48 °C/W PD (1) Device Power Dissipation VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50% duty cycle square wave °C/W 220 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 15 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTIC CURVES ISO7240C/M RMS SUPPLY CURRENT vs SIGNALING RATE ISO7241C/M RMS SUPPLY CURRENT vs SIGNALING RATE 45 45 TA = 25°C, Load = 15 pF, All Channels 40 ICC - Supply Current - mA/RMS ICC - Supply Current - mA/RMS 40 35 5-V ICC2 30 3.3-V ICC2 25 20 5-V ICC1 15 10 5 35 5-V ICC2 30 20 3.3-V ICC2 15 50 75 100 Signaling Rate - Mbps 125 5 0 0 150 75 100 Figure 8. ISO7242C/M RMS SUPPLY CURRENT vs SIGNALING RATE PROPAGATION DELAY vs FREE-AIR TEMPERATURE 125 150 45 TA = 25°C, Load = 15 pF, All Channels 40 C 3.3-V tpLH, tpHL 35 30 Propagation Delay - ns ICC - Supply Current - mA/RMS 16 50 Figure 7. 35 5-V ICC1,ICC2 25 20 15 3.3-V ICC1,ICC2 C 5-V tpLH, tpHL 30 25 M 3.3-V tpLH, tpHL 20 15 M 5-V tpLH, tpHL 10 10 5 5 0 0 25 Signaling Rate - Mbps 45 40 3.3-V ICC1 10 3.3-V ICC1 25 5-V ICC1 25 0 0 TA = 25°C, Load = 15 pF, All Channels TA = 25°C, Load = 15 pF, All Channels 0 25 50 75 100 125 150 Signaling Rate - Mbps 80 65 35 20 50 TA - Free-Air Temperature - °C Figure 9. Figure 10. Submit Documentation Feedback -40 -25 -10 5 95 110 125 Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTIC CURVES (continued) INPUT VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE VCC1 FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE 1.4 3 5 V Vth+ 1.3 2.9 VCC1 - Failsafe Threshold - V Input Voltage Threshold - V 1.35 3.3 V Vth+ 1.25 1.2 Air Flow at 7 cf/m, Low_K Board 1.15 5 V Vth1.1 2.8 VCC at 5 V or 3.3 V, Load = 15 pF, Air Flow at 7/cf/m, Low-K Board 2.7 Vfs+ 2.6 2.5 Vfs- 2.4 2.3 2.2 1.05 1 -40 3.3 V Vth-25 -10 2.1 5 20 35 50 65 80 TA - Free-Air Temperature - °C 95 110 2 -40 125 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C Figure 11. Figure 12. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 50 VCC = 5 V Load = 15 pF, TA = 25°C Load = 15 pF, TA = 25°C 45 40 IO - Output Current - mA 40 IO - Output Current - mA -25 VCC = 3.3 V 30 20 35 VCC = 3.3 V 30 25 VCC = 5 V 20 15 10 10 5 0 0 0 2 4 VO - Output Voltage - V Figure 13. Copyright © 2007–2008, Texas Instruments Incorporated 6 0 1 2 3 VO - Output Voltage - V 4 5 Figure 14. Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 17 ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com APPLICATION INFORMATION 2 mm max. from VCC1 VCC1 2 mm max. from VCC2 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUT A IN B 4 13 OUT B IN C 5 12 OUT C IN D 6 11 OUT D 7 10 8 9 GND1 GND2 NC EN GND2 GND1 ISO7240x Figure 15. Typical ISO7240x Application Circuit 2 mm max. from VCC1 VCC1 2 mm max. from VCC2 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUT A IN B 4 13 OUT B IN C 5 12 OUT C 6 11 GND1 IN D GND2 DISABLE OUT D CTRL 7 10 8 9 GND2 GND1 ISO7240CF Figure 16. Typical ISO7240CF Failsafe-Low Application Circuit 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M ISO7240CF, ISO7240C,, ISO7240M ISO7241C, ISO7241M ISO7242C, ISO7242M www.ti.com........................................................................................................................................ SLLS868I – SEPTEMBER 2007 – REVISED DECEMBER 2008 LIFE EXPECTANCY vs. WORKING VOLTAGE WORKING LIFE -- YEARS 100 VIORM at 560-V 28 Years 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (VIORM) -- V Figure 17. Time-Dependant Dielectric Breakdown Testing Results Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240CF, ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M 19 PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO7240CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242MDW ACTIVE SOIC DW 16 CU NIPDAU Level-3-260C-168 HR 40 Addendum-Page 1 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2008 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO7242MDWG4 ACTIVE SOIC DW 16 ISO7242MDWR ACTIVE SOIC DW ISO7242MDWRG4 ACTIVE SOIC DW 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.75 10.7 2.7 12.0 16.0 Q1 ISO7240CDWR SOIC DW 16 2000 330.0 16.4 ISO7240CFDWR SOIC DW 16 2000 330.0 16.4 10.9 10.78 3.0 12.0 16.0 Q1 ISO7240MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7241CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7241MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7242CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7242MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7240CDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7240CFDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7240MDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7241CDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7241MDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7242CDWR SOIC DW 16 2000 358.0 335.0 35.0 ISO7242MDWR SOIC DW 16 2000 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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