[ /Title (CD74 HC404 6A, CD74 HCT40 46A) /Subject (HighSpeed CMOS CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Data sheet acquired from Harris Semiconductor SCHS204J High-Speed CMOS Logic Phase-Locked Loop with VCO February 1998 - Revised December 2003 Features Description • Operating Frequency Range - Up to 18MHz (Typ) at VCC = 5V - Minimum Center Frequency of 12MHz at VCC = 4.5V The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the “4000B” series. They are specified in compliance with JEDEC standard number 7. • Choice of Three Phase Comparators - EXCLUSIVE-OR - Edge-Triggered JK Flip-Flop - Edge-Triggered RS Flip-Flop The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator. • Excellent VCO Frequency Linearity The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption • Minimal Frequency Drift • Operating Power Supply Voltage Range - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V Ordering Information • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC4046AF3A -55 to 125 16 Ld CERDIP CD54HCT4046AF3A -55 to 125 16 Ld CERDIP • Balanced Propagation Delay and Transition Times CD74HC4046AE -55 to 125 16 Ld PDIP • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC4046AM -55 to 125 16 Ld SOIC CD74HC4046AMT -55 to 125 16 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC4046AM96 -55 to 125 16 Ld SOIC CD74HC4046ANSR -55 to 125 16 Ld SOP CD74HC4046APWR -55 to 125 16 Ld TSSOP CD74HC4046APWT -55 to 125 16 Ld TSSOP • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HCT4046AE -55 to 125 16 Ld PDIP • Wide Operating Temperature Range . . . -55oC to 125oC CD74HCT4046AM -55 to 125 16 Ld SOIC CD74HCT4046AMT -55 to 125 16 Ld SOIC CD74HCT4046AM96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Applications • FM Modulation and Demodulation • Frequency Synthesis and Multiplication • Frequency Discrimination • Tone Decoding • Data Synchronization and Conditioning • Voltage-to-Frequency Conversion • Motor-Speed Control CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Pinout CD54HC4046A, CD54HCT4046A (CERDIP) CD74HC4046A (PDIP, SOIC, SOP, TSSOP) CD74HCT4046A (PDIP, SOIC) TOP VIEW PCPOUT 1 16 VCC PC1OUT 2 15 PC3OUT COMPIN 3 14 SIGIN VCOOUT 4 13 PC2OUT INH 5 12 R2 C1A 6 11 R1 C1B 7 10 DEMOUT 9 VCOIN GND 8 Functional Diagram 2 PC1OUT 3 COMPIN 15 14 φ SIGIN PC3OUT 13 PC2OUT 1 PCPOUT 6 C1A C1B R1 R2 VCOIN 7 4 11 12 VCOOUT VCO 10 9 DEMOUT 5 INH Pin Descriptions PIN NUMBER SYMBOL NAME AND FUNCTION 1 PCPOUT Phase Comparator Pulse Output 2 PC1OUT Phase Comparator 1 Output 3 COMPIN Comparator Input 4 VCOOUT VCO Output 5 INH Inhibit Input 6 C1A Capacitor C1 Connection A 7 C1B Capacitor C1 Connection B 8 GND Ground (0V) 9 VCOIN 10 DEMOUT 11 R1 Resistor R1 Connection 12 R2 Resistor R2 Connection 13 PC2OUT 14 SIGIN 15 PC3OUT 16 VCC VCO Input Demodulator Output Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage 2 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A C1 7 4 C1A C1B 3 14 SIGIN COMPIN + VREF VCOOUT 6 12 R2 SD - R2 PC1OUT 2 PC3OUT 15 Q VCO Q RD 11 R1 R1 + VCC VCC - D 10 R5 DEMOUT - Q UP p CP Q RD + 13 PC2OUT R3 C2 n VCC D Q CP Q RD INH VCOIN 5 9 GND DOWN 1 PCPOUT FIGURE 1. LOGIC DIAGRAM General Description VCO Phase Comparators The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. See logic diagram, Figure 1. The signal input (SIGIN) can be directly coupled to the selfbiasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. Phase Comparator 1 (PC1) This is an Exclusive-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequencydivider. The VCO output signal has a specified duty factor of 50%. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. VDEMOUT = (VCC/π) (φSIGIN - φCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Figure 2. The average of VDEM is equal to 1/2 VCC when there is no signal or noise at SIGIN, and with this input the VCO oscillates at the center frequency (fo). Typical waveforms for the PC1 loop locked at fo are shown in Figure 3. 3 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A VDEMOUT = (VCC/4π) (φSIGIN - φCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter). The frequency capture range (2fC) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. The average output voltage from PC2, fed to the VCO via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 4. Typical waveforms for the PC2 loop locked at fo are shown in Figure 5. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock behavior even with very noisy input signals. Typical of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO center frequency. VCC VDEMOUT (AV) VCC 1/2 VCC VDEMOUT (AV) 1/2 VCC 0 -360o 90o φDEMOUT φDEMOUT 360o FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC2OUT = (VCC/4π) (φSIGIN - φCOMPIN); φDEMOUT = (φSIGIN - φCOMPIN) 0 0o 0o 180o FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN φCOMPIN); φDEMOUT = (φSIGIN - φCOMPIN) SIGIN COMPIN VCOOUT VCC PC2OUT SIGIN GND HIGH IMPEDANCE OFF - STATE COMPIN VCOIN VCOOUT PCPOUT PC1OUT FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 2, LOOP LOCKED AT fo VCC VCOIN GND Phase Comparator 2 (PC2) When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control-gating and a threestate output stage. The circuit functions as an up-down counter (Figure 1) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is: When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n- and p-type drivers are “OFF” (three-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the n-type driver that is held “ON” for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 1, LOOP LOCKED AT fo 4 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in three-state and the VCO input at pin 9 is a high impedance. Also in this condition, the signal at the phase comparator pulse output (PCPOUT) is a HIGH level and so can be used for indicating a locked condition. VCC VDEMOUT (AV) Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p- and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIGIN, the VCO adjusts, via PC2, to its lowest frequency. 1/2 VCC 0 0o 180o φDEMOUT 360o FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC3OUT = (VCC/2π) (φSIGIN - φCOMPIN); φDEMOUT = (φSIGIN - φCOMPIN) Phase Comparator 3 (PC3) This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The transfer characteristic of PC3, assuming ripple (fr = fi) is suppressed, is: VDEMOUT = (VCC/2p) (fSIGIN - fCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC3OUT (via low-pass filter). SIGIN COMPIN VCOOUT The average output from PC3, fed to the VCO via the lowpass filter and seen at the demodulator at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 6. Typical waveforms for the PC3 loop locked at fo are shown in Figure 7. PC3OUT VCOIN VCC GND The phase-to-output response characteristic of PC3 (Figure 6) differs from that of PC2 in that the phase angle between SIGIN and COMPIN varies between 0o and 360o and is 180o at the center frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences but as aconsequence the ripple content of the VCO input signal is higher. With no signal present at SIGIN, the VCO adjusts, via PC3, to its highest frequency. FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 3, LOOP LOCKED AT fo The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The comparator’s sections are identical, so that there is no difference in the SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and the HCT versions. 5 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 3 2.1 - - 2.1 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 2.1 - V HC TYPES VCO SECTION INH High Level Input Voltage INH Low Level Input Voltage VIL VCOOUT High Level Output Voltage CMOS Loads VOH - VIH or VIL VCOOUT High Level Output Voltage TTL Loads VCOOUT Low Level Output Voltage CMOS Loads VOL VIH or VIL VCOOUT Low Level Output Voltage TTL Loads C1A, C1B Low Level Output Voltage (Test Purposes Only) VOL VIL or VIH - 3 - - 0.9 - 0.9 - 0.9 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 3 2.9 - - 2.9 - 2.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V 4 4.5 - - 0.40 - 0.47 - 0.54 V 5.2 6 - - 0.40 - 0.47 - 0.54 V 6 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) INH VCOIN Input Leakage Current II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ C1 Capacitance Range - - - 3 - - - - - pF - - No Limit - 4.5 - - - - pF VCOIN Operating Voltage Range - PARAMETER MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - - - - - pF 3 1.1 - 1.9 - - - - V 4.5 1.1 - 3.2 - - - - V 6 1.1 - 4.6 - - - - V 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 2 1.9 - - 1.9 - 1.9 - V 4.5 4.4 - - 4.4 - 4.4 - V 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 2 - - ±3 - ±4 - ±5 µA Over the range specified for R1 for Linearity See Figure 10, and 34 - 37 (Note 3) PHASE COMPARATOR SECTION SIGIN, COMPIN DC Coupled High-Level Input Voltage VIH SIGIN, COMPIN DC Coupled Low-Level Input Voltage VIL PCPOUT, PCn OUT High-Level Output Voltage CMOS Loads VOH PCPOUT, PCn OUT High-Level Output Voltage TTL Loads VOH PCPOUT, PCn OUT Low-Level Output Voltage CMOS Loads VOL PCPOUT, PCn OUT Low-Level Output Voltage TTL Loads VOL SIGIN, COMPIN Input Leakage Current II PC2OUT Three-State Off-State Current IOZ SIGIN, COMPIN Input Resistance RI - - VIL or VIH VIL or VIH VIL or VIH VIL or VIH VCC or GND VIL or VIH - - -0.02 - 3 - - ±7 - ±9 - ±11 µA 4.5 - - ±18 - ±23 - ±29 µA 6 - - ±30 - ±38 - ±45 µA 6 - - ±0.5 - ±5 - ±10 µA VI at Self-Bias Operation Point: ∆VI = 0.5V, See Figure 10 3 - 800 - - - - - kΩ 4.5 - 250 - - - - - kΩ 6 - 150 - - - - - kΩ at RS > 300kΩ Leakage Current Can Influence VDEMOUT 3 50 - 300 - - - - kΩ 4.5 50 - 300 - - - - kΩ 6 50 - 300 - - - - kΩ DEMODULATOR SECTION Resistor Range RS 7 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL Offset Voltage VCOIN to VDEM VOFF Dynamic Output Resistance at DEMOUT RD Quiescent Device Current ICC VI (V) IO (mA) VI = VVCO IN = VCC 2 Values Taken Over RS Range See Figure 23 VDEMOUT = VCC 2 Pins 3, 5 and 14 at VCC Pin 9 at GND, I1 at Pins 3 and 14 to be excluded VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 3 - ±30 - - - - - mV 4.5 - ±20 - - - - - mV 6 - ±10 - - - - - mV 3 - 25 - - - - - Ω 4.5 - 25 - - - - - Ω 6 - 25 - - - - - Ω 6 - - 8 - 80 - 160 µA HCT TYPES VCO SECTION INH High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V INH Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VCOOUT High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 4 4.5 - - 0.40 - 0.47 - 0.54 V 5.5 - ±0.1 - ±1 - ±1 µA VCOOUT High Level Output Voltage TTL Loads VCOOUT Low Level Output Voltage CMOS Loads VOL VIH or VIL VCOOUT Low Level Output Voltage TTL Loads C1A, C1B Low Level Output Voltage (Test Purposes Only) VOL VIH or VIL INH VCOIN Input Leakage Current II Any Voltage Between VCC and GND R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ C1 Capacitance Range - - - 4.5 0 - No Limit - - - - pF VCOIN Operating Voltage Range - 4.5 1.1 - 3.2 - - - - V 4.5 to 5.5 2 - - 2 - 2 - V Over the range specified for R1 for Linearity See Figure 10, and 34 - 37 (Note 3) PHASE COMPARATOR SECTION SIGIN, COMPIN DC Coupled High-Level Input Voltage VIH - - 8 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) SIGIN, COMPIN DC Coupled Low-Level Input Voltage VIL - - PCPOUT, PCn OUT High-Level Output Voltage CMOS Loads VOH VIL or VIH PCPOUT, PCn OUT High-Level Output Voltage TTL Loads VOH PCPOUT, PCn OUT Low-Level Output Voltage CMOS Loads PCPOUT, PCn OUT Low-Level Output Voltage TTL Loads VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V - 4.5 4.4 - - 4.4 - 4.4 - V VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V SIGIN, COMPIN Input Leakage Current II Any Voltage Between VCC and GND - 5.5 - - ±30 ±45 µA PC2OUT Three-State Off-State Current IOZ VIL or VIH - 5.5 - - ±0.5 ±5 - - ±10 µA SIGIN, COMPIN Input Resistance RI VI at Self-Bias Operation Point: ∆VI = 0.5V, See Figure 10 4.5 - 250 - - - - - kΩ at RS > 300kΩ Leakage Current Can Influence VDEM OUT 4.5 5 - 300 - - - - kΩ VI = VVCO IN = VCC 2 Values taken over RS Range See Figure 23 4.5 - ±20 - - - - - mV VDEM OUT = VCC 2 4.5 - 25 - - - - - Ω ±38 DEMODULATOR SECTION Resistor Range Offset Voltage VCOIN to VDEM RS VOFF Dynamic Output Resistance at DEMOUT RD Quiescent Device Current ICC VCC or GND - 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 4) VCC -2.1 Excluding Pin 5 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: 2. The value for R1 and R2 in parallel should exceed 2.7kΩ. 3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage. 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 9 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A HCT Input Loading Table INPUT UNIT LOADS INH 1 NOTE: Unit load is ∆ICC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25oC. Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns 6 - - 34 - 43 - 51 ns 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns 6 - - 51 - 64 - 77 ns 2 - - 245 - 305 - 307 ns 4.5 - - 49 - 61 - 74 ns 6 - - 42 - 52 - 63 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 2 - - 265 - 330 - 400 ns 4.5 - - 53 - 66 - 80 ns 6 - - 45 - 56 - 68 ns 2 - - 315 - 395 - 475 ns 4.5 - - 63 - 79 - 95 ns 6 - - 54 - 67 - 81 ns HC TYPES PHASE COMPARATOR SECTION Propagation Delay SIGIN, COMPIN to PCIOUT tPLH, tPHL SIGIN, COMPIN to PCPOUT SIGIN, COMPIN to PC3OUT Output Transition Time Output Enable Time, SIGIN, COMPIN to PC2OUT Output Disable Time, SIGIN, COMPIN to PC2OUT tTHL, tTLH tPZH, tPZL tPHZ, tPLZ AC Coupled Input Sensitivity (P-P) at SIGIN or COMPIN VI(P-P) 3 - 11 - - - - - mV 4.5 - 15 - - - - - mV 6 - 33 - - - - - mV 3 - 0.11 - - - - - %/oC 4.5 - 0.11 - - - - - %/oC 6 - 0.11 - - - - - %/oC 3 - 24 - - - - - MHz 4.5 - 24 - - - - - MHz 6 - 24 - - - - - MHz 3 - 38 - - - - - MHz 4.5 - 38 - - - - - MHz 6 - 38 - - - - - MHz VCO SECTION Frequency Stability with Temperature Change Maximum Frequency ∆f ∆T fMAX R1 = 100kΩ, R2 = ∞ C1 = 50pF R1 = 3.5kΩ R2 = ∞ C1 = 0pF R1 = 9.1kΩ R2 = ∞ 10 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns (Continued) SYMBOL Center Frequency Frequency Linearity TEST CONDITIONS C1 = 40pF R1 = 3kΩ R2 = ∞ VCOIN = VCC/2 ∆fVCO Offset Frequency R1 = 100kΩ R2 = ∞ C1 = 100pF R2 = 220kΩ C1 = 1nF -40oC TO 85oC 25oC VCC (V) MIN TYP MAX MIN MAX -55oC TO 125oC MIN MAX UNITS 3 7 10 - - - - - MHz 4.5 12 17 - - - - - MHz 6 14 21 - - - - - MHz 3 - 0.4 - - - - - % 4.5 - 0.4 - - - - - % 6 - 0.4 - - - - - % 3 - 400 - - - - - kHz 4.5 - 400 - - - - - kHz 6 - 400 - - - - - kHz DEMODULATOR SECTION VOUT VS fIN R1 = 100kΩ R2 = ∞ C1 = 100pF RS = 10kΩ R3 = 100kΩ C2 = 100pF 3 - - - - - - - mV/kHz 4.5 - 330 - - - - - mV/kHz 6 - - - - - - - mV/kHz CL = 50pF 4.5 - - 45 - 56 - 68 ns SIGIN, COMPIN to PCPOUT tPHL, tPLH CL = 50pF 4.5 - - 68 - 85 - 102 ns SIGIN, COMPIN to PC3OUT tPHL, tPLH CL = 50pF 4.5 - - 58 - 73 - 87 ns HCT TYPES PHASE COMPARATOR SECTION Propagation Delay SIGIN, COMPIN to PCIOUT tPHL, tPLH Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Output Enable Time, SIGIN, COMPIN to PC2OUT tPZH, tPZL CL = 50pF 4.5 - - 60 - 75 - 90 pF Output Disable Time, SIGIN, COMPIN to PCZOUT tPHZ, tPLZ CL = 50pF 4.5 - - 68 - 85 - 102 pF VI(P-P) 4.5 - 15 - - - - - mV ∆f ∆T R1 = 100kΩ, R2 = ∞ 4.5 - 0.11 - - - - - %/oC fMAX C1 = 50pF R1 = 3.5kΩ R2 = ∞ 4.5 - 24 - - - - - MHz C1 = 0pF R1 = 9.1kΩ R2 = ∞ 4.5 - 38 - - - - - MHz C1 = 40pF R1 = 3kΩ R2 = ∞ VCOIN = VCC/2 4.5 12 17 - - - - - MHz R1 = 100kΩ R2 = ∞ C1 = 100pF 4.5 - 0.4 - - - - - % AC Coupled Input Sensitivity (P-P) at SIGIN or COMPI VCO SECTION Frequency Stability with Temperature Change Maximum Frequency Center Frequency Frequency Linearity ∆fVCO 11 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns (Continued) SYMBOL Offset Frequency TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS R2 = 220kΩ C1 = 1nF 4.5 - 400 - - - - - kHz R1 = 100kΩ R2 = ∞ C1 = 100pF RS = 10kΩ R3 = 100kΩ C2 = 100pF 4.5 - 330 - - - - - mV/kHz DEMODULATOR SECTION VOUT VS fIN Test Circuits and Waveforms SIGIN INPUTS SIGIN COMPIN VS VS INPUTS tPHL tPHL COMPIN INPUTS PCPOUT PC1OUT tPZL tPZH VS PC3OUT OUTPUTS VS tPZH tTLH PC2OUT OUTPUT tTLH FIGURE 8. INPUT TO OUTPUT PROPAGATION DELAYS AND OUTPUT TRANSITION TIMES tPZL 90% VS 10% FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR PC2OUT Typical Performance Curves II ∆VI SELF-BIAS OPERATING POINT VI FIGURE 10. TYPICAL INPUT RESISTANCE CURVE AT SIGIN, COMPIN 12 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Typical Performance Curves (Continued) 108 106 105 104 103 102 VCOIN = 0.5 VCC 10 1 106 105 104 103 102 VCOIN = 0.5 VCC 10 VCC = 6.0V VCC = 4.5V 1 R1 =3K R1 = 30K R1 =330K R1 = 3M R1 = 15M 107 CENTER FREQUENCY (Hz) 107 CENTER FREQUENCY (Hz) 108 R1 = 2.2K R1 = 22K R1 = 220K R1 = 2.2M R1 = 11M 1 102 10 103 104 105 106 1 102 10 FIGURE 11. HC4046A TYPICAL CENTER FREQUENCY vs R1, C1 (VCC = 4.5V) 108 105 104 103 102 VCOIN = 0.5 VCC VCC = 3.0V 10 106 105 104 103 102 VCOIN = 0.5 VCC 10 VCC = 4.5V R2 = OPEN 1 1 1 102 10 103 104 105 106 1 102 10 CAPACITANCE, C1 (pF) 108 103 104 105 106 CAPACITANCE, C1 (pF) FIGURE 13. HC4046A TYPICAL CENTER FREQUENCY vs R1, C1 (VCC = 3V, R2 = OPEN) FIGURE 14. HCT4046A TYPICAL CENTER FREQUENCY vs R1, C1 (VCC = 4.5V) 140 R1 = 3K R1 = 30K R1 = 300K R1 = 3M R1 = 15M 107 106 105 104 103 102 VCC = 5.5V 10 100 VCC = 4.5V 80 VCC = 3V 60 20 1 1 VCC = 6V 40 VCOIN = 0.5 VCC 10 C1 = 50pF R1 = 1.5M 120 VCO FREQUENCY (kHz) CENTER FREQUENCY (Hz) 106 R1 = 2.2K R1 = 22K R1 = 220K R1 = 2.2M R1 = 11M 107 CENTER FREQUENCY (Hz) CENTER FREQUENCY (Hz) 106 105 FIGURE 12. HC4046A TYPICAL CENTER FREQUENCY vs R1, C1 (VCC = 6V) R1 = 1.5K R1 = 15K R1 = 150K R1 = 1.5M R1 = 7.5M 107 104 CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF) 108 103 102 103 104 105 0 106 1 2 3 4 5 6 VCOIN (V) CAPACITANCE, C1 (pF) FIGURE 16. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 1.5MΩ, C1 = 50pF) FIGURE 15. HCT4046A TYPICAL CENTER FREQUENCY vs R1, C1 (VCC = 5.5V) 13 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Typical Performance Curves (Continued) 90 800 C1 = 0.1µF R1 = 1.5M C1 = 0.1µF R1 = 150K 70 VCC = 4.5V 60 50 VCC = 3V 40 VCC = 6V 700 VCO FREQUENCY (Hz) VCO FREQUENCY (Hz) 80 VCC = 6V 30 600 VCC = 4.5V 500 400 VCC = 3V 300 200 20 10 100 0 1 2 3 4 5 6 0 1 2 VCOIN (V) 5 6 FIGURE 18. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 150kΩ, C1 = 0.1µF) 18 1400 VCC = 6V C1 = 0.1µF R1 = 5.6k VCC = 4.5V 14 VCC = 3V 12 10 8 6 VCC = 6V C1 = 50pF R1 = 150K 1200 VCO FREQUENCY (kHz) 16 VCO FREQUENCY (kHz) 4 VCOIN (V) FIGURE 17. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 1.5MΩ, C1 = 0.1µF) 1000 VCC = 4.5V 800 VCC = 3V 600 400 4 200 2 0 1 2 3 4 5 0 6 1 2 VCOIN (V) 3 4 5 6 VCOIN (V) FIGURE 19. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 5.6kΩ, C1 = 0.1µF) FIGURE 20. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 150kΩ, C1 = 50pF) 24 24 VCC = 6V C1 = 50pF R1 = 5.6K 20 VCO FREQUENCY CHANGE, ∆f (%) VCO FREQUENCY (MHz) 3 VCC = 4.5V 16 12 VCC = 3V 8 4 0 1 2 3 4 5 20 16 R1 = 1.5M 12 R1 = 150K 8 4 0 R1 = 3K -4 -8 R1 = 1.5K -12 -16 -75 6 VCOIN = 0.5 VCC C1 = 50pF, VCC = 3V R2 = OPEN -50 -25 0 25 50 75 100 125 150 AMBIENT TEMPERATURE, TA (oC) VCOIN (V) FIGURE 21. HC4046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 5.6kΩ, C1 = 50pF) FIGURE 22. HC4046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 (VCC = 3V) 14 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Typical Performance Curves VCOIN = 0.5 VCC C1 = 50pF, VCC = 4.5V R2 = OPEN 16 16 R1 = 2.2M VCO FREQUENCY CHANGE, ∆f (%) VCO FREQUENCY CHANGE, ∆f (%) 20 (Continued) 12 R1 = 220K 8 4 0 -4 R1 = 2.2K -8 -12 -75 12 VCOIN = 0.5 VCC C1 = 50pF, VCC = 6.0V R2 = OPEN 8 R1 = 300K 4 0 -4 R1 = 3K -8 -12 -50 -25 0 25 50 75 100 125 150 -75 -50 AMBIENT TEMPERATURE, TA (oC) VCO FREQUENCY CHANGE, ∆f (%) VCO FREQUENCY CHANGE, ∆f (%) 20 R1 = 3M 12 8 R1 = 300K 4 0 R1 = 3K -4 -8 -12 -75 -50 -25 0 25 50 75 100 0 25 50 75 100 125 150 FIGURE 24. HC4046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 (VCC = 6V) 20 VCOIN = 0.5 VCC C1 = 50pF, VCC = 5.5V R2 = OPEN -25 AMBIENT TEMPERATURE, TA (oC) FIGURE 23. HC4046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 (VCC = 4.5V) 16 R1 = 3M 125 16 AMBIENT TEMPERATURE, TA (oC) R1 = 2.2M 12 R1 = 220K 8 4 0 -4 R1 = 2.2K -8 -12 -75 150 VCOIN = 0.5 VCC C1 = 50pF, VCC = 4.5V R2 = OPEN -50 -25 0 25 50 75 100 125 150 AMBIENT TEMPERATURE, TA (oC) FIGURE 25. HCT4046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 FIGURE 26. HC4046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 (VCC = 4.5V) 15 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A (Continued) 108 108 107 107 106 OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) Typical Performance Curves R2 = 2.2K 105 R2 = 22K 104 103 R2 = 220K 102 R2 = 2.2M VCOIN = 0.5 VCC VCC = 4.5V 10 1 1 102 10 106 R2 = 1.5K 105 104 R2 = 15K 103 R2 = 150K 102 R2 = 1.5M VCOIN = 0.5 VCC VCC = 3V 10 R2 = 11M 1 103 104 105 106 1 102 10 CAPACITANCE, C1 (pF) 107 107 OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) 108 106 R2 = 2.2K 105 104 R2 = 22K 103 R2 = 220K 102 R2 = 2.2M VCOIN = 0.5 VCC VCC = 4.5V 1 102 10 R2 = 30K 104 R2 = 300K 103 R2 = 3M 102 VCOIN = 0.5 VCC HC VCC = 6V HCT VCC = 5.5V 103 104 105 106 1 102 10 104 105 106 FIGURE 30. HC4046A AND HCT4046A OFFSET FREQUENCY vs R2, C1 (VCC = 6V, VCC = 5.5V) 102 10 1 R2/R1 103 CAPACITANCE, C1 (pF) fMAX /fMIN fMAX /fMIN R2 = 15M 1 PIN 9 = 0.95 VCC FOR fMAX PIN 9 = 0V FOR fMIN VCC = 3V, 4.5V, 6V 10-1 106 R2 = 3K 105 10 R2 = 11M FIGURE 29. HCT4046A OFFSET FREQUENCY vs R2, C1 (VCC = 4.5V) 0 10-2 105 106 CAPACITANCE, C1 (pF) 102 104 FIGURE 28. HC4046A OFFSET FREQUENCY vs R2, C1 (VCC = 3V) 108 1 103 CAPACITANCE, C1 (pF) FIGURE 27. HC4046A OFFSET FREQUENCY vs R2, C1 (VCC = 4.5V) 10 R2 = 7.5M 10 PIN 9 = 0.95 VCC FOR fMAX PIN 9 = 0V FOR fMIN VCC = 4.5V TO 5.5V 10 0 10-2 102 FIGURE 31. HC4046A fMIN/fMAX vs R2/R1 (VCC = 3V, 4.5V, 6V) 10-1 1 R2/R1 10 102 FIGURE 32. HCT4046A fMAX/fMIN vs R2/R1 (VCC = 4.5V TO 5.5V) 16 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Typical Performance Curves (Continued) 8 C1 = 50pF VCC = 4.5V R2 = OPEN 6 4 LINEARITY (%) f f2 f0 ∆V = 0.5V OVER THE VCC RANGE: FOR VCO LINEARITY f’o = f1 + f2 2 f’o - fo x 100% LINEARITY = f’ f0 f1 VCOIN = 2.25V ± 1V 2 VCOIN = 2.25V ± 0.45V 0 -2 -4 o ∆V MIN ∆V -6 -8 1K MAX VVCOIN 1/2VCC FIGURE 33. DEFINITION OF VCO FREQUENCY LINEARITY LINEARITY (%) LINEARITY (%) 4 VCOIN = 1.50V ± 0.4V 0 VCOIN = 1.50V ± 0.3V -2 0 -2 -4 -6 -6 10K 100K R1 (OHMS) 1M DEMODULATOR POWER DISSIPATION, PD (µW) 2 0 -4 -6 10K 100K R1 (OHMS) C1 = 50pF R2 = OPEN 1M 10K 100K R1 (OHMS) 1M 10M FIGURE 36. HC4046A VCO LINEARITY vs R1 (VCC = 6V) VCC = 5.5V, VCOIN = 2.75V ±1.3V 6 VCC = 4.5V, VCOIN = 2.25V ±1.0V 4 VCC = 5.5V, VCOIN = 2.75V ±0.55V VCC = 4.5V, VCOIN = 2.25V ±0.45V VCOIN = 3V ± 0.6V -8 1K 10M 8 -2 VCOIN = 3V ± 1.5V 2 -4 FIGURE 35. HC4046A VCO LINEARITY vs R1 (VCC = 3V) LINEARITY (%) 10M C1 = 50pF VCC = 6V R2 = OPEN 6 2 -8 1K 1M 8 C1 = 50pF VCC = 3V R2 = OPEN 4 -8 1K 100K R1 (OHMS) FIGURE 34. HC4046A VCO LINEARITY vs R1 (VCC = 4.5V) 8 6 10K 10M 104 VCOIN = 0.5 VCC 103 VCC = 6V 102 VCC = 3V VCC = 4.5V 10 1 1K 10K 100K 1M RS (OHMS) FIGURE 37. HCT4046A VCO LINEARITY vs R1 (VCC = 4.5V, VCC = 5.5V) FIGURE 38. HC4046A DEMODULATOR POWER DISSIPATION vs RS (TYP) (VCC = 3V, 4.5V, 6V) 17 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A (Continued) 106 104 VCO POWER DISSIPATION, PD (µW) DEMODULATOR POWER DISSIPATION, PD (µW) Typical Performance Curves VCOIN = 0.5 VCC R1 = R2 = OPEN 103 VCC = 6V 102 VCC = 3V VCC = 4.5V 10 VCOIN = 0.5VCC R2 = RS = OPEN CL = 50pF VCC = 6V C1 = 50pF 105 VCC = 6V C1 = 1µF 104 VCC = 3V C1 = 1µF 103 VCC = 3V C1 = 50pF VCC = 4.5V C1 = 1µF 102 1 1K 1K 10K 100K 10K 1M FIGURE 39. HCT4046A DEMODULATOR POWER DISSIPATION vs RS (TYP) (VCC = 3V, 4.5V, 6V) VCO POWER DISSIPATION, PD (µW) VCO POWER DISSIPATION, PD (µW) 106 105 VCC = 4.5V C1 = 50pF 104 VCC = 4.5V C1 = 1µF VCC = 6V C1 = 1µF 103 1M FIGURE 40. HC4046A VCO POWER DISSIPATION vs R1 (C1 = 50pF, 1µF) VCOIN = 0V (AT fMIN) R1 = RS = OPEN CL = 50pF VCC = 6V C1 = 50pF 100K R1 (OHMS) RS (OHMS) 106 VCC = 4.5V C1 = 50pF 102 VCC = 5.5V C1 = 50pF 105 VCOIN = 0.5V R2 = RS = OPEN VCC = 4.5V C1 = 50pF 104 VCC = 5.5V C1 = 1µF 103 VCC = 4.5V C1 = 1µF 102 1K 10K 100K 1K 1M 10K R2 (OHMS) FIGURE 41. HCT4046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF) FIGURE 42. HCT4046A VCO POWER DISSIPATION vs R1 (C1 = 50pF, 1µF) 106 VCO POWER DISSIPATION, PD (µW) 100K R1 (OHMS) VCC = 6V C1 = 50pF 105 VCOIN = 0V (AT fMIN) R1 = RS = OPEN CL = 50pF VCC = 4.5V C1 = 50pF VCC = 6V C1 = 1µF 104 VCC = 3V C1 = 1µF VCC = 3V C1 = 50pF 103 VCC = 4.5V C1 = 1µF 102 1K 10K 100K 1M R2 (OHMS) FIGURE 43. HC4046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF) 18 1M CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A References should be made to Figures 11 through 15 and Figures 27 through 32 as indicated in the table. HC/HCT4046A CPD CHIP SECTION HC HCT UNIT Comparator 1 48 50 pF Comparators 2 and 3 39 48 pF VCO 61 53 pF Values of the selected components should be within the following ranges: Application Information This information is a guide for the approximation of values of external components to be used with the ’HC4046A and ’HCT4046A in a phase-lock-loop system. SUBJECT VCO Frequency Without Extra Offset R1 Between 3kΩ and 300kΩ R2 Between 3kΩ and 300kΩ R1 + R2 Parallel Value > 2.7kΩ C1 Greater Than 40pF PHASE COMPARATOR PC1, PC2 or PC3 DESIGN CONSIDERATIONS VCO Frequency Characteristic With R2 = ∞ and R1 within the range 3kΩ < R1 < 300kΩ, the characteristics of the VCO operation will be as shown in Figures 11 - 15. (Due to R1, C1 time constant a small offset remains when R2 = ∞.) fMAX fVCO fo 2fL fMIN MIN 1/2 VCC VVCOIN MAX FIGURE 44. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE VCO Frequency with Extra Offset PC1 Selection of R1 and C1 Given fo, determine the values of R1 and C1 using Figures 11 - 15 PC2 or PC3 Given fMAX calculate fo as fMAX/2 and determine the values of R1 and C1 using Figures 11 15. To obtain 2fL: 2fL ≈ 1.2 (VCC - 1.8V)/(R1C1) where valid range of VCOIN is 1.1V < VCOIN < VCC - 0.9V PC1, PC2 or PC3 VCO Frequency Characteristic With R1 and R2 within the ranges 3kΩ < R1 < 300kΩ, 3kΩ, < R2 < 300kΩ, the characteristics of the VCO operation will be as shown in Figures 27 - 32. fMAX fVCO 2fL fo fMIN MIN 1/2 VCC VVCOIN MAX FIGURE 45. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE PC1, PC2 or PC3 Selection of R1, R2 and C1 Given fo and fL, offset frequency, fMIN, may be calculated from fMIN ≈ fo - 1.6 fL. Obtain the values of C1 and R2 by using Figures 27 - 30. Calculate the values of R1 from Figures 31 - 32. 19 CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A SUBJECT PLL Conditions with No Signal at the SIGIN Input PLL Frequency Capture Range PHASE COMPARATOR DESIGN CONSIDERATIONS PC1 VCO adjusts to fo with φDEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2) PC2 VCO adjusts to fMIN with φDEMOUT = -360o and VVCOIN = 0V (see Figure 4) PC3 VCO adjusts to fMAX with φDEMOUT = 360o and VVCOIN = VCC (see Figure 6) PC1, PC2 or PC3 Loop Filter Component Selection |F(jω)| R3 INPUT (A) C2 -1/τ OUTPUT ω τ = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM 1/π (2πfL/τ.)1/2 A small capture range (2fc) is obtained if τ > 2fc ≈ FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET R3 |F(jω)| R4 INPUT m= R4 R3 + R4 OUTPUT m C2 (A) τ1 = R3 x C2; τ2 = R4 x C2; τ3 = (R3 + R4) x C2 1/τ3 1/τ2 ω (B) AMPLITUDE CHARACTERISTIC -1/τ2 -1/τ3 (C) POLE-ZERO DIAGRAM FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET PLL Locks on Harmonics at Center Frequency PC1 or PC3 Yes PC2 No Noise Rejection at Signal Input PC1 High PC2 or PC3 Low AC Ripple Content when PLL is Locked PC1 fr = 2fi, large ripple content at φDEMOUT = 90o PC2 fr = fi, small ripple content at φDEMOUT = 0o PC3 fr = fSIGIN, large ripple content at φDEMOUT = 180o 20 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8875701EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 5962-8960901EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) CD54HC4046AF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC4046AF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT4046AF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC4046AE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4046AEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4046AM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AM96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AMT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4046APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4046AE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4046AEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT4046AM ACTIVE SOIC D 16 CD74HCT4046AM96 ACTIVE SOIC D CD74HCT4046AM96E4 ACTIVE SOIC CD74HCT4046AM96G4 ACTIVE CD74HCT4046AME4 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4046AMT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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