TI CDCE925 Programmable 2-pll vcxo clock synthesizer with 1.8-v, 2.5-v and 3.3-v lvcmos output Datasheet

CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-V and 3.3-V
LVCMOS OUTPUTS
Check for Samples: CDCE925, CDCEL925
FEATURES
•
1
• Member of Programmable Clock Generator
Family
– CDCE913/CDCEL913: 1-PLL, 3 Outputs
– CDCE925/CDCEL925: 2-PLL, 5 Outputs
– CDCE937/CDCEL937: 3-PLL, 7 Outputs
– CDCE949/CDCEL949: 4-PLL, 9 Outputs
• Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2] e.g., SSC Selection, Frequency
Switching, Output Enable or Power Down
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
– Generates Common Clock Frequencies
Used With Texas Instruments DaVinci™,
OMAP™, DSPs
– Generates Highly Accurate Clocks for
Video, Audio, USB, IEEE1394, RFID,
Bluetooth™, WLAN, Ethernet™, and GPS
• In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Setting
234
VDD
•
•
•
•
•
•
•
APPLICATIONS
•
D-TV, STB, IP-STB, DVD-Player, DVD-Recorder,
Printer
VDDOUT
GND
Vctr
Crystal or
Clock Input
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typ 60 ps)
1.8-V Device Power Supply
Separate Output Supply Pins
– CDCE925: 3.3 V and 2.5 V
– CDCEL925: 1.8 V
Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy
PLL Design and Programming (TI Pro-Clock™)
VCXO
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
LV
CMOS
Y4
LV
CMOS
Y5
XO
LVCMOS
PLL1
S2/S1/S0 or
SDA/SCL
3
EEPROM
Programming
and
Control Register
With SSC
Divider
and
Output
Control
PLL2
Xin/Clk
S0
Vdd
Vctr
GND
Vddout
Y4
Y5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Xout
S1/SDA
S2/SCL
Y1
GND
Y2
Y3
Vddout
With SSC
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG.
Ethernet is a trademark of Xerox Corporattion.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock
synthesizers, multipliers, and dividers. They generate up to five output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to two independent
configurable PLLs.
The CDCx925 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL925 and 2.5 V to 3.3 V for
CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth,
Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from a 27 MHz reference input frequency, for
example.
All PLLs supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is
a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be re-programmed to a different application configuration
before it goes onto the PCB or re-programmed by in-system programming. All device settings are programmable
through SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change
SSC setting for lowering EMI, or other control features like outputs disable to low, outputs 3-state, power down,
PLL bypass, etc.).
The CDCx925 operates in a 1.8 V environment. It operates in a temperature range of –40 °C to 85 °C.
Terminal Functions for CDCE925, CDCEL925
TERMINAL
NAME
Y1, Y2, ... Y5
I/O
NO.
DESCRIPTION
7, 8, 10, 11, 13
O
LVCMOS outputs
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus)
Xout
16
O
Crystal oscillator output (leave open or pullup when not used)
VCtrl
4
I
VCXO control voltage (leave open or pullup when not used)
VDD
3
Power
VDDOUT
6, 9
Power
GND
5, 12
Ground
S0
2
I
SDA/S1
15
I/O or I
SCL/S2
14
I
2
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1.8-V power supply for the device
CDCEL925: 1.8-V supply for all outputs
CDCE925: 3.3-V or 2.5-V supply for all outputs
Ground
User-programmable control input S0; LVCMOS inputs; internal pullup
SDA: bidirectional serial data input/output (default configuration), LVCMOS; internal
pullup; or
S1: user-programmable control input; LVCMOS inputs; internal pullup
SCL: serial clock input (default configuration), LVCMOS; internal pullup or
S2: user-programmable control input; LVCMOS inputs; internal pullup
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
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SCAS847F – JULY 2007 – REVISED MARCH 2010
FUNCTIONAL BLOCK DIAGRAM for CDCE925, CDCEL925
V DD
V DDOUT
GND
Input Clock
LV
CMOS
Y1
M2
LV
CMOS
Y2
M3
LV
CMOS
Y3
M4
Xin/CLK
LV
CMOS
Y4
M5
Pdiv1
M1
Vctr
LV
CMOS
Y5
10-Bit
VCXO
XO
Pdiv2
With SSC
Xout
MUX1
PLL 1
LVCMOS
7-Bit
Pdiv3
S0
S1/SDA
S2/SCL
Programming
and
SDA/SCL
Register
PLL Bypass
7-Bit
PLL 2
Pdiv4
With SSC
MUX2
EEPROM
PLL Bypass
7-Bit
Pdiv5
7-Bit
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage range
VI
Input voltage range (2)
VO
Output voltage range (2)
II
Input current (VI < 0, VI > VDD)
IO
Tstg
TJ
Maximum junction temperature
(1)
(2)
(3)
(3)
VALUE
UNIT
–0.5 to 2.5
V
–0.5 to VDD + 0.5
V
–0.5 to VDD + 0.5
V
20
mA
Continuous output current
50
mA
Storage temperature range
–65 to 150
°C
125
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.
PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TJA
Thermal Resistance Junction to Ambient
AIRFLOW
(lfm)
TSSOP16
°C/W
0
101
150
85
200
84
250
82
500
74
42
TJC
Thermal Resistance Junction to Case
—
TJB
Thermal Resistance Junction to Board
—
64
RqJT
Thermal Resistance Junction to Top
—
1.0
RqJB
Thermal Resistance Junction to Bottom
—
58
(1)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS
VDD
VDDOUT
MIN
NOM
MAX
Device supply voltage
1.7
1.8
1.9
Output Yx supply voltage for CDCE925
2.3
Output Yx supply voltage for CDCEL925
1.7
VIL
Low-level input voltage LVCMOS
VIH
High-level input voltage LVCMOS
VI(thresh)
Input voltage threshold LVCMOS
VI(S)
VI(CLK)
IOH /IOL
1.9
V
0.3 VDD
V
0.7 VDD
V
0.5 VDD
V
0
1.9
Input voltage range S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD
0
3.6
Input voltage range CLK
0
1.9
Output current (VDDOUT = 3.3 V)
±12
Output current (VDDOUT = 2.5 V)
±10
Output current (VDDOUT = 1.8 V)
±8
Output load LVCMOS
TA
Operating free-air temperature
V
3.6
Input voltage range S0
CL
UNIT
–40
V
V
mA
15
pF
85
°C
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ VCtrl ≤ 1.8 V) (2)
VCtrl
Frequency control voltage
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
MIN
NOM
MAX
UNIT
8
27
32
MHz
±120
±150
100
0
Ω
ppm
VDD
V
220
0
20
pF
For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm
applies for crystal listed in the application report (SCAA085).
EEPROM SPECIFICATION
EEcyc
Programming cycles of EEPROM
EEret
Data retention
4
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MIN
TYP
100
1000
10
MAX
UNIT
cycles
years
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
UNIT
CLK_IN REQUIREMENTS
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD / 2
3
STANDARD
MODE
FAST
MODE
MHz
ns
UNIT
MIN
MAX
MIN
MAX
0
100
0
400
SDA/SCL TIMING REQUIREMENTS (see Figure 12)
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
4
th(SDA)
SDA hold time (SDA valid after SCL low)
0
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
1000
300
tf
SCL/SDA input fall time
300
300
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
4.7
0.6
ms
4
0.6
ms
4.7
1.3
ms
0.6
3.45
250
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
kHz
0
ms
0.9
100
ms
ns
ns
ns
4
0.6
ms
4.7
1.3
ms
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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
OVERALL PARAMETER
Supply current (see Figure 3)
All outputs off, fCLK=27 MHz,
fVCO = 135 MHz; fOUT = 27
MHz
All PLLS on
IDD
20
Per PLL
9
IDDOUT
Supply current (see Figure 4 and Figure 5)
No load, all outputs on,
fOUT = 27 MHz
CDCE925 VDDOUT = 3.3 V
2
CDCEL925 VDDOUT = 1.8 V
1
IDDPD
Power-down current. Every circuit powered
down except SDA/SCL
fIN = 0 MHz,
VDD = 1.9 V
VPUC
Supply voltage VDD threshold for power-up
control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
mA
mA
30
CDCE(L)925 VDDOUT = 1.8 V
mA
0.85
1.45
V
80
230
MHz
230
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V; Is = –18 mA
II
LVCMOS Input current
VI = 0 V or VDD; VDD = 1.9 V
IIH
LVCMOS Input current for S0/S1/S2
IIL
LVCMOS Input current for S0/S1/S2
Input capacitance at Xin/Clk
VIClk = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
–1.2
V
±5
mA
VI = VDD; VDD = 1.9 V
5
mA
VI = 0 V; VDD = 1.9 V
–4
mA
pF
CDCE925 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
tPLH, tPHL
Propagation delay
tr/tf
Rise and fall time
(2) (3)
tjit(cc)
Cycle-to-cycle jitter
tjit(per)
Peak-to-peak period jitter (3)
tsk(o)
Output skew
odc
Output duty cycle
(4)
(5)
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
V
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
All PLL bypass
3.2
VDDOUT = 3.3 V (20%–80%)
0.6
1 PLL switching, Y2-to-Y3
50
70
2 PLL switching, Y2-to-Y5
90
130
1 PLL switching, Y2-to-Y3
60
100
2 PLL switching, Y2-to-Y5
100
160
ns
ns
fOUT = 50 MHz; Y1-to-Y3
70
fOUT = 50 MHz; Y2-to-Y5
150
fVCO = 100 MHz; Pdiv = 1
45%
V
ps
ps
ps
55%
CDCE925 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VDDOUT = 2.3 V, IOL = 10 mA
0.7
V
tPLH, tPHL
Propagation delay
All PLL bypass
3.6
ns
tr/tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
ns
(1)
(2)
(3)
(4)
(5)
6
All typical values are at respective nominal VDD.
10000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
odc depends on output rise- and fall time (tr/tf);
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TYP (1)
MAX
1 PLL switching, Y2-to-Y3
50
70
2 PLL switching, Y2-to-Y5
90
130
1 PLL switching, Y2-to-Y3
60
100
2 PLL switching, Y2-to-Y5
100
160
PARAMETER
TEST CONDITIONS
(6) (7)
tjit(cc)
Cycle-to-cycle jitter
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew
odc
Output duty cycle
(7)
(8)
(9)
MIN
fOUT = 50 MHz; Y1-to-Y3
70
fOUT = 50 MHz; Y2-to-Y5
150
fVCO = 100 MHz; Pdiv = 1
45%
UNIT
ps
ps
ps
55%
CDCEL925 — LVCMOS PARAMETER for VDDOUT = 1.8 V – Mode
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VDDOUT = 1.7 V, IOH = –4 mA
1.4
VDDOUT = 1.7 V, IOH = –8 mA
1.1
V
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VDDOUT = 1.7 V, IOL = 4 mA
0.3
VDDOUT = 1.7 V, IOL = 8 mA
0.6
tPLH, tPHL
Propagation delay
All PLL bypass
2.6
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
1 PLL switching, Y2-to-Y3
80
110
2 PLL switching, Y2-to-Y5
130
200
1 PLL switching, Y2-to-Y3
100
130
2 PLL switching, Y2-to-Y5
150
220
(6) (7)
tjit(cc)
Cycle-to-cycle jitter
tjit(per)
Peak-to-peak period jitter
tsk(o)
Output skew
odc
(10)
(11)
Output duty cycle
(12)
ns
ns
fOUT = 50 MHz; Y1-to-Y3
50
fOUT = 50 MHz; Y2-to-Y5
110
fVCO = 100 MHz; Pdiv = 1
45%
V
ps
ps
ps
55%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
mA
VIH
SDA/SCL input high voltage (13)
VIL
SDA/SCL input low voltage (13)
VOL
SDA low-level output voltage
IOL = 3 mA VDD = 1.7 V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
0.7 VDD
V
0.3 VDD
3
V
0.2 VDD
V
10
pF
10000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
odc depends on output rise- and fall time (tr/tf);
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input
frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,
data sampled on rising edge (tr).
odc depends on output rise- and fall time (tr/tf);
SDA and SCL pins are 3.3 V tolerant.
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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
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PARAMETER MEASUREMENT INFORMATION
CDCE925
CDEL925
1 kW
LVCMOS
1 kW
10 pF
Figure 1. Test Load
CDCE925
CDCEL925
LVCMOS
LVCMOS
Typical Driver
Impedance
~ 32 W
Series
Termination
~ 18 W
Line Impedance
Zo = 50 W
Figure 2. Test Load for 50-Ω Board Environment
8
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Product Folder Link(s): CDCE925 CDCEL925
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CDCEL925
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SCAS847F – JULY 2007 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS
CDCE925 AND CDCEL925 SUPPLY CURRENT
vs
PLL FREQUENCY
CDCE925 OUTPUT CURRENT
vs
OUTPUT FREQUENCY
25
60
VDD = 1.8 V
IDDOUT - Output Current - mA
IDD - Supply Current - mA
50
40
2 PLL on
30
1 PLL on
20
10
0
10
20
VDD = 1.8 V,
VDDOUT = 3.3 V,
No Load
5 outputs on
3 outputs on
15
1 output on
all outputs off
10
5
all PLL off
60
110
160
f - Frequency - MHz
0
10
210
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3.
Figure 4.
CDCEL925 OUTPUT CURRENT
vs
OUTPUT FREQUENCY
8
IDDOUT - Output Current - mA
7
VDD = 1.8 V,
VDDOUT = 1.8 V,
No Load
5 outputs on
6
3 outputs on
5
1 output on
4
all outputs off
3
2
1
0
10 30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 5.
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CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
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APPLICATION INFORMATION
CONTROL TERMINAL SETTING
The CDCE925/CDCEL925 has three user-definable control terminals (S0, S1, and S2) which allow external
control of device settings. They can be programmed to any of the following setting:
• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
External
Control Bits
Control
Function
PLL1 Setting
PLL Frequency
Selection
SSC
Selection
PLL2 Setting
Output Y2/Y3
Selection
PLL Frequency
Selection
SSC
Selection
Y1 Setting
Output Y4/Y5
Selection
Output Y1 and
Power-Down Selection
Table 2. PLL Setting (Can Be Selected for Each PLL Individual) (1)
SSC SELECTION (CENTER/DOWN)
SSCx [3-Bits]
Center
Down
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y5)
(1)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
10
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
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SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In default configuration, they are
predefined as SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by
setting the relevant bits in the EEPROM. Note that the changes of the bits in the Control Register (bit [6] of byte
02h) have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi use pin; it is a control pin only.
DEFAULT DEVICE SETTING
The internal EEPROM of CDCE925/CDCEL925 is preconfigured as shown in Figure 6 The input frequency is
passed through the output as a default. This allows the device to operate in default mode without the extra
production step of programming it. The default setting appears after power is supplied or after power-down/up
sequence until it is reprogrammed by the user to a different application configuration. A new register setting is
programmed via the serial SDA/SCL interface.
V DD
V DDOUT
GND
SDA
Programming Bus
SCL
PLL 2
Power Down
M2
S0
“0” = Outputs 3-State
Pdiv3 = 1
PLL Bypass
EEPROM
Programming
and
SDA/SCL
Register
LV
CMOS
Y3 = 27 MHz
Pdiv4 = 1
LV
CMOS
Y4 = 27 MHz
LV
CMOS
Y5 = 27 MHz
MUX2
“1” = Outputs Enabled
Pdiv2 = 1
MUX1
Xout
Y2 = 27 MHz
M3
PLL 1
LV
CMOS
Pdiv1 =1
Xtal
Power Down
Y1 = 27 MHz
M4
27-MHz
Crystal
LV
CMOS
M5
M1
Input Clock
Xin
Pdiv5 = 1
PLL Bypass
Figure 6. Preconfiguration of CDCE925/CDCEL925 Internal EEPROM
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). Note that even
though eight different register settings are possible, in default configuration, only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 are configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register (1)
Y1
External Control Pins
PLL1 Settings
PLL2 Settings
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
S2
S1
S0
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
off
3-state
fVCO2_0
off
3-state
SCL (I2C)
SDA (I2C)
1
enabled
fVCO1_0
off
enabled
fVCO2_0
off
enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
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SDA/SCL SERIAL INTERFACE
This section describes the SDA/SCL interface of the CDCE925/CDCEL925 device. The CDCE925/CDCEL925
operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C
specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s)
and supports 7-bit addressing.
The SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In the default configuration
they are used as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control
pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].
DATA PROTOCOL
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
bytes read out are defined by byte count in the Generic Configuration Register. At Block Read instruction all
bytes defined in the byte count has to be read out to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write
Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read
out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCE913/CDCEL913
1
1
0
0
1
0
1
1/0
CDCE925/CDCEL925
1
1
0
0
1
0
0
1/0
CDCE937/CDCEL937
1
1
0
1
1
0
1
1/0
CDCE949/CDCEL949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
12
Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices connected
to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
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COMMAND CODE DEFINITION
Table 6. Command Code Definition
BIT
7
(6:0)
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
S
7
Slave Address
1
R/W
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
R/W
1
A
8
Data Byte
1
A
MSB
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 7. Generic Programming Sequence
Byte Write Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 8. Byte Write Protocol
Byte Read Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
S
Figure 9. Byte Read Protocol
Block Write Programming Sequence
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
…
8
Data Byte N-1
1
A
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 10. Block Write Protocol
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Block Read Programming Sequence
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 11. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 12. Timing Diagram for SDA/SCL Serial Control Interface
SDA/SCL HARDWARE INTERFACE
Figure 13 shows how the CDCE925/CDCEL925 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the
maximum) if many devices are connected.
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax =
0.4 V for the output stages (for more details see SMBus or I2C Bus specification).
CDCE925
CDCEL925
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Figure 13. SDA / SCL Hardware Interface
14
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SDA/SCL CONFIGURATION REGISTERS
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE925/CDCEL925. All settings can be manually
written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI
Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for
optimized performance at lowest jitter.
Table 7. SDA/SCL Registers
Address Offset
Register Description
Table
00h
Generic Configuration Register
Table 9
10h
PLL1 Configuration Register
Table 10
20h
PLL2 Configuration Register
Table 11
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2. Table 8 explains the corresponding bit assignment
between the Control Terminal Register and the Configuration Registers.
Table 8. Configuration Register, External Control Terminals
Y1
External Control Pins
PLL1 Settings
Frequency
Selection
SSC
Selection
PLL2 Settings
Output
Selection
Frequency
Selection
SSC
Selection
Output
Selection
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
FS2_0
SSC2_0
Y4Y5_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
FS2_1
SSC2_1
Y4Y5_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
FS2_2
SSC2_2
Y4Y5_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
FS2_3
SSC2_3
Y4Y5_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
FS2_4
SSC2_4
Y4Y5_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
FS2_5
SSC2_5
Y4Y5_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
FS2_6
SSC2_6
Y4Y5_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
FS2_7
SSC2_7
Y4Y5_7
04h
13h
10h–12h
15h
23h
20h–22h
25h
Address Offset (1)
(1)
Output
Selection
Address Offset refers to the byte address in the Configuration Register in Table 9, Table 10, and Table 11.
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Table 9. Generic Configuration Register
Offset
00h
01h
(1)
Bit
(2)
Acronym
Default
(3)
Description
7
E_EL
Xb
Device identification (read-only): 1 is CDCE925 (3.3 V out), 0 is CDCEL925 (1.8 V out)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
5
EELOCK
0b
4
PWDN
0b
EEPROM Programming Status4: (4) (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
Permanently Lock EEPROM Data (5)
0 – EEPROM is not locked
1 – EEPROM will be permanently locked
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-state)
3:2
INCLK
00b
Input clock selection:
1:0
SLAVE_ADR
00b
Address Bits A0 and A1 of the Slave Receiver Address
00 – Xtal
01 – VCXO
7
M1
1b
Clock source selection for output Y1:
10 – LVCMOS
0 – input clock
11 – reserved
1 – PLL1 clock
Operation mode selection for pin 14/15 (6)
02h
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
03h
7:0
Pdiv1 [7:0]
04h
7
Y1_7
0b
6
Y1_6
0b
5
Y1_6
0b
4
Y1_6
0b
3
Y1_6
0b
2
Y1_6
0b
1
Y1_6
0b
0
Y1_6
0b
0 – serial programming interface SDA (pin 15) and SCL (pin 14)
1 – control pins S1 (pin 15) and S2 (pin 14)
Y1-State0/1 Definition
00 – device power down (all PLLs in power down and all
outputs in 3-State)
01 – Y1 disabled to 3-state
10-Bit Y1-Output-Divider Pdiv1:
0 – divider reset and stand-by
1-to-1023 – divider value
001h
7:3
XCSEL
2:0
06h
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
16
Y1_ST0/Y1_ST1 State Selection (7)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
Crystal Load Capacitor Selection (8)
05h
10 – Y1 disabled to low
11 – Y1 enabled
0Ah
0b
Reserved – do not write other than 0
00h → 0 pF
01h → 1 pF
02h → 2 pF
:
14h-to-1Fh → 20 pF
Vctr
Xin
20pF
i.e.
XCSEL = 10pF
VCXO
XO
Xout
20pF
7:1
BCOUNT
30h
7-Bit Byte Count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes
have to be read out to correctly finish the read cycle.)
0
EEWRITE
0b
Initiate EEPROM Write Cycle (9)
0– no EEPROM write cycle
1 – start EEPROM write cycle (internal register are saved to the EEPROM)
Writing data beyond ‘30h’ may affect device function.
All data transferred with the MSB first.
Unless customer-specific setting.
During EEPROM programming, no data is allowed to be sent to the device via the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.
Data, however can still be written via SDA/SCL bus to the internal register to change device function on the fly. But new data can no
longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM.
Selection of “control pins” is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are
no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0=”0” and A1=“0”.
These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then
can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors should be used only to
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20
pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which
always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see
application report SCAA085.
Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
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Table 9. Generic Configuration Register (continued)
Offset (1)
Bit (2)
07h-0Fh
Acronym
Default (3)
—
0h
Description
Reserved – do not write other than 0
Table 10. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
14h
15h
16h
17h
(1)
(2)
(3)
(4)
(1)
Acronym
Default (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
6
M2
1b
5:4
M3
10b
3:2
Y2Y3_ST1
11b
1:0
Y2Y3_ST0
01b
7
Y2Y3_7
0b
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
7
SSC1DC
0b
6:0
Pdiv2
01h
7
—
0b
6:0
Pdiv3
01h
Bit
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 Frequency Selection(4)
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
11 – Y2/Y3 enabled (normal operation, PLL1 on)
Y2Y3_x Output State Selection(4)
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
PLL1 SSC down/center selection:
0 – down
1 – center
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y3-Output-Divider Pdiv3:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 30h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
18h
7:0
PLL1_0N [11:4
19h
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
1Ch
7:0
PLL1_1N [11:4]
1Dh
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
1Ah
1Bh
Default (3)
004h
DESCRIPTION
PLL1_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see paragraph PLL Multiplier/Divider Definition).
000h
10h
fVCO1_0 range selection:
1Eh
1Fh
004h
18
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
PLL1_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO1_1 range selection:
(5)
00 –
01 –
10 –
11 –
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
Table 11. PLL2 Configuration Register
OFFSET (1)
Bit (2)
Acronym
Default (3)
20h
7:5
SSC2_7 [2:0]
000b
4:2
SSC2_6 [2:0]
000b
1:0
SSC2_5 [2:1]
7
SSC2_5 [0]
6:4
SSC2_4 [2:0]
000b
3:1
SSC2_3 [2:0]
000b
0
SSC2_2 [2]
7:6
SSC2_2 [1:0]
5:3
SSC2_1 [2:0]
000b
2:0
SSC2_0 [2:0]
000b
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
7
MUX2
1b
6
M4
1b
5:4
M5
10b
3:2
Y4Y5_ST1
11b
1:0
Y4Y5_ST0
01b
7
Y4Y5_7
0b
6
Y4Y5_6
0b
5
Y4Y5_5
0b
4
Y4Y5_4
0b
3
Y4Y5_3
0b
2
Y4Y5_2
0b
1
Y4Y5_1
1b
0
Y4Y5_0
0b
7
SSC2DC
0b
6:0
Pdiv4
01h
7
—
0b
6:0
Pdiv5
01h
21h
22h
23h
24h
25h
26h
27h
(1)
(2)
(3)
(4)
000b
000b
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS2_x: PLL2 Frequency Selection(4)
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
PLL2 Multiplexer:
0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
Output Y4 Multiplexer:
0 – Pdiv2
1 – Pdiv4
Output Y5 Multiplexer:
00 –
01 –
10 –
11 –
Y4,
Y5-State0/1definition:
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
11 – Y4/Y5 enabled (normal operation, PLL2 on)
Pdiv2-Divider
Pdiv4-Divider
Pdiv5-Divider
reserved
Y4Y5_x Output State Selection(4)
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
PLL2 SSC down/center selection:
0 – down
1 – center
7-Bit Y4-Output-Divider Pdiv4:
0 – reset and stand-by
1-to-127 – divider value
Reserved – do not write others than 0
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
1-to-127 – divider value
Writing data beyond 30h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
Submit Documentation Feedback
19
CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
Table 11. PLL2 Configuration Register (continued)
OFFSET (1)
Bit (2)
Acronym
28h
7:0
PLL2_0N [11:4
29h
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
2Ch
7:0
PLL2_1N [11:4]
2Dh
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
2Ah
2Bh
Default (3)
004h
DESCRIPTION
PLL2_0 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO2_0 range selection:
2Eh
2Fh
004h
20
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1 (5): 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information see paragraph PLL Multiplier/Divider Definition)
000h
10h
fVCO2_1 range selection:
(5)
00 –
01 –
10 –
11 –
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096.
Submit Documentation Feedback
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
CDCE925
CDCEL925
www.ti.com
SCAS847F – JULY 2007 – REVISED MARCH 2010
PLL Multiplier/Divider Definition
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE925/CDCEL925 can be calculated:
ƒ
N
ƒ OUT + IN
Pdiv M
(1)
where
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output
divider.
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
ƒ VCO + ƒIN
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
NP = 4 – int
ǒlog MN Ǔ [if P t 0 then P + 0] Q = int ǒNȀM Ǔ R = N′ – M × Q
2
where
N′ = N × 2PN ≥ M100 MHz < ƒVCO > 200 MHz
16 ≤ q ≤63
0≤p≤7
0 ≤ r ≤ 511
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N′’ = 4 × 2 = 16
→ N′’ = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ is automatically calculated when using TI Pro-Clock™ software.
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
Submit Documentation Feedback
21
CDCE925
CDCEL925
SCAS847F – JULY 2007 – REVISED MARCH 2010
www.ti.com
REVISION HISTORY
Changes from Original (July 2007) to Revision A
•
Page
Changed the data sheet status From: Product Preview To: Production data. ..................................................................... 1
Changes from Revision A (August 2007) to Revision B
Page
•
Changed IDDPD Power-down current Typ value From: 20 To: 30 .......................................................................................... 6
•
Changed II LVCMOS Input current value From: ±5 Typ To: ±5 Max .................................................................................... 6
•
Changed IIH LVCMOS Input current for S0/S1/S2 value From: 5 Typ To: 5 Max ................................................................ 6
•
Changed IIL LVCMOS Input current for S0/S1/S2 value From: -4 Typ To: -4 Max .............................................................. 6
•
Changed text of Note 4 in the DEVICE CHARACTERISTIC table ....................................................................................... 7
•
Changed Figure 2, Test Load for 50-Ω Board Environment ................................................................................................. 8
•
Changed Table 2 header From: OUTPUT SELECTION (Y2 ... Y9) To: OUTPUT SELECTION (Y2 ... Y5) ...................... 10
•
Changed Table 9 - 01h Bit 7 From: For interla use – always write To: Reserved – always write ..................................... 16
•
Changed Table 9 - PLL2_1N [11:4] description From: fVCO1_1 To: fVCO2_1 .......................................................................... 20
Changes from Revision B (August 2007) to Revision C
Page
•
Changed the PACKAGE THERMAL RESISTANCE for TSSOP table ................................................................................. 3
•
Changed Table 9 - RID From: 0h To: Xb ........................................................................................................................... 16
•
Added note to the PWDN description, Table 9 ................................................................................................................... 16
Changes from Revision C (December 2007) to Revision D
•
Page
Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. .................. 3
Changes from Revision D (September 2009) to Revision E
•
Page
Deleted sectence - A different default setting can be programmed on customer request. Contact Texas Instruments
sales or marketing representative for more information. .................................................................................................... 11
Changes from Revision E (October 2009) to Revision F
Page
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 to PLL1 and PLL2 Configure Register tables ............. 18
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<511 to PLL Multiplier/Divder Definition Section .................... 21
22
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE925 CDCEL925
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCE925PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCE925PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCE925PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCE925PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCEL925PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCEL925PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCEL925PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCEL925PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE925PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CDCEL925PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE925PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
CDCEL925PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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