Intersil LMH6611 Powerwiseâ® single supply 345 mhz rail-to-rail output amplifier Datasheet

LMH6611/LMH6612
PowerWise® Single Supply 345 MHz Rail-to-Rail Output
Amplifiers
General Description
Features
The LMH6611 (single, with shutdown) and LMH6612 (dual)
are 345 MHz rail-to-rail output amplifiers consuming just 3.2
mA of quiescent current per channel and designed to deliver
high performance in power conscious single supply systems.
The LMH6611 and LMH6612 have precision trimmed input
offset voltages with low noise and low distortion performance
as required for high accuracy video, test and measurement,
and communication applications. The LMH6611 and
LMH6612 are members of the PowerWise family and have an
exceptional power-to-performance ratio.
With a trimmed input offset voltage of 0.022 mV and a high
open loop gain of 103 dB the LMH6611 and LMH6612 meet
the requirements of DC sensitive high speed applications
such as low pass filtering in baseband I and Q radio channels.
These specifications combined with a 0.01% settling time of
and better than 102 dBc
100 ns, a low noise of 10 nV/
SFDR at 100 kHz make these amplifiers particularly suited to
driving 10, 12 and 14-bit high speed ADCs. The 45 MHz 0.1
dB bandwidth (AV = 2) driving 2 VPP into 150Ω allows the amplifiers to be used as output drivers in 1080i and 720p HDTV
applications.
The input common mode range extends from 200 mV below
the negative supply rail up to 1.2V from the positive rail. On a
single 5V supply with a ground terminated 150Ω load the output swings to within 55 mV of the ground, while a mid-rail
terminated 1 kΩ load will swing to 77 mV of either rail.
The amplifiers will operate on a 2.7V to 11V single supply or
±1.35V to ±5.5V split supply. The LMH6611 single is available
in 6-Pin TSOT23 and has an independent active low disable
pin which reduces the supply current to 120 µA. The
LMH6612 is available in 8-Pin SOIC. Both the LMH6611 and
LMH6612 are available in −40°C to +125°C extended industrial temperature grade.
VS = 5V, RL = 1 kΩ, TA = 25°C and AV = +1, unless otherwise
specified.
2.7V to 11V
■ Operating voltage range
3.2 mA
■ Supply current per channel
345 MHz
■ Small signal bandwidth
103 dB
■ Open loop gain
0.022 mV
■ Input offset voltage
460 V/µs
■ Slew rate
45 MHz
■ 0.1 dB bandwidth
67 ns
■ Settling time to 0.1%
100 ns
■ Settling time to 0.01%
102 dBc
■ SFDR (f = 100 kHz, AV = 2, VOUT = 2 VPP)
10 nV/√Hz
■ Low voltage noise
±100 mA
■ Output current
−0.2V to 3.8V
■ CMVR
■ Rail-to-Rail output
■ −40°C to +125°C temperature range
Applications
■
■
■
■
■
■
■
■
ADC driver
DAC buffer
Active filters
High speed sensor amplifier
Current sense amplifier
1080i and 720p analog video amplifier
STB, TV video amplifier
Video switching and muxing
Typical Application
30033629
PowerWise® is a registered trademark of National Semiconductor.
WEBENCH® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
300336
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LMH6611/LMH6612 PowerWise Single Supply 345 MHz Rail-to-Rail Output Amplifiers
December 18, 2007
LMH6611/LMH6612
Supply Voltage (VS = V+ – V−)
Junction Temperature (Note 3)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings
V+
12V
150°C max
(Note 1)
Supply Voltage (VS =
–
Ambient Temperature Range (Note 3)
ESD Tolerance (Note 2)
Human Body Model
For input pins only
For all other pins
Machine Model
Charge Device Model
2000V
2000V
200V
1000V
V−)
2.7V to 11V
−40°C to +125°C
Package Thermal Resistance (θJA)
6-Pin TSOT23
8-Pin SOIC
231°C/W
160°C/W
+3V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO = V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ.
Boldface limits apply at temperature extremes. (Note 4)
Symbol
Parameter
Condition
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
305
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
115
GBW
Gain Bandwidth
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 1.5 VPP
90
AV = −1, RL = 150Ω, VOUT = 2 VPP
85
115
MHz
135
Peak
Peaking
AV = 1
1.0
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
33
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
65
MHz
MHz
dB
RF = RG = 560Ω
MHz
AV = 2, VOUT = 1.5 VPP, RL = 150Ω,
47
RF = RG = 510Ω
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to
DP
Differential Phase
0.03
%
0.06
deg
V+/2
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
1.5V Step, AV = 1
2.8
ns
SR
Slew Rate
2V Step, AV = 1
330
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
74
ts_0.01
0.01% Settling Time
2V Step, AV = −1
116
fC = 100 kHz, AV = −1, VOUT= 2 VPP
109
fC = 1 MHz, AV = −1, VOUT = 2 VPP
97
ns
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
dBc
fC = 5 MHz, AV = −1, VOUT = 2 VPP
80
en
Input Voltage Noise
f = 100 kHz
10
nV/
in
Input Current Noise
f = 100 kHz
2
pA/
CT
Crosstalk
(LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input, DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = 0.5V
0.022
±0.600
±1.0
Input Offset Voltage
(LMH6612)
VCM = 0.5V
0.015
±0.600
±1.2
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2
mV
Parameter
Condition
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
μV/°C
TCVOS
Input Offset Voltage Average Drift (Note 5)
0.1
IB
Input Bias Current
−5.9
−10.1
−11.1
μA
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
pF
RIN
Input Resistance
6
MΩ
CMVR
Input Voltage Range
DC, CMRR ≥ 76 dB
CMRR
Common Mode Rejection Ratio
VCM Stepped from −0.1V to 1.7V
79
98
AOL
Open Loop Gain
RL = 1 kΩ, VOUT = 2.7V to 0.3V
89
101
RL = 150Ω, VOUT = 2.5V to 0.5V
78
85
VCM = 0.5V
−0.2
1.8
V
dB
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
RL = 1 kΩ to V+/2
59
72
76
RL =150Ω to V+/2
133
169
182
RL = 1 kΩ to V+/2
58
68
73
RL =150Ω to V+/2
131
157
172
RL = 1 kΩ to V+/2
59
74
80
RL =150Ω to V+/2
133
171
188
RL = 150Ω to V−
42
52
56
RL = 1 kΩ to V+/2
61
71
79
RL =150Ω to V+/2
139
168
187
RL = 150Ω to V−
45
V+/2
IOUT
Linear Output Current
VOUT =
RO
Output Resistance
f = 1 MHz
(Note 6)
mV
±70
mA
0.07
Ω
0.001
µA
Enable Pin Operation
Enable High Voltage Threshold
Enabled (Note 9)
Enable Pin High Current
VDISABLE = 3V
Enable Low Voltage Threshold
Disabled (Note 9)
Enable Pin Low Current
VDISABLE = 0V
2.0
V
1.0
V
0.8
µA
ton
Turn-On Time
18
ns
toff
Turn-Off Time
50
ns
96
dB
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
RL = ∞
3.0
3.4
3.8
Supply Current (LMH6612)
(per channel)
RL = ∞
2.95
3.45
3.9
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
101
132
ISD
3
81
mA
μA
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LMH6611/LMH6612
Symbol
LMH6611/LMH6612
+5V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO = V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ.
Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
345
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
112
GBW
Gain Bandwidth
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
−3 dB Bandwidth Large Signal
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
77
AV = 2, RL = 150Ω, VOUT = 2 VPP
85
115
MHz
135
Peak
Peaking
AV = 1
0.3
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
45
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
68
MHz
MHz
dB
RF = RG = 680Ω
MHz
AV = 2, VOUT = 2 VPP, RL = 150Ω,
45
RF = RG = 665Ω
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
0.05
%
0.06
deg
RL = 150Ω to V+/2
DP
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
2V Step, AV = 1
3.6
ns
SR
Slew Rate
2V Step, AV = 1
460
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
67
ts_0.01
0.01% Settling Time
2V Step, AV = −1
100
fC = 100 kHz, AV = 2, VOUT = 2 VPP
102
fC = 1 MHz, AV = 2, VOUT = 2 VPP
96
fC = 5 MHz, AV = 2, VO = 2 VPP
82
ns
Distortion and Noise Performance
SFDR
Spurious Free Dynamic Range
dBc
en
Input Voltage Noise
f = 100 kHz
10
nV/
in
Input Current Noise
f = 100 kHz
2
pA/
CT
Crosstalk
(LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input, DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = 0.5V
0.013
±0.600
±1.0
Input Offset Voltage
(LMH6612)
VCM = 0.5V
0.022
±0.600
±1.2
TCVOS
Input Offset Voltage Average
Drift
(Note 5)
0.1
IB
Input Bias Current
VCM = 0.5V
−6.3
−10.1
−11.1
μA
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
RIN
Input Resistance
CMVR
Input Voltage Range
DC, CMRR ≥ 78 dB
CMRR
Common Mode Rejection Ratio
VCM Stepped from −0.1V to 3.7V
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µV/°C
pF
6
−0.2
4
81
MΩ
3.8
98
mV
V
dB
AOL
Parameter
Open Loop Gain
Condition
Min
(Note 8)
Typ
(Note 7)
RL = 1 kΩ, VOUT = 4.6V to 0.4V
92
103
RL = 150Ω, VOUT = 4.4V to 0.6V
80
86
Max
(Note 8)
Units
dB
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
RL = 1 kΩ to V+/2
76
90
93
RL =150Ω to V+/2
195
239
256
RL = 1 kΩ to V+/2
75
86
91
RL =150Ω to V+/2
195
223
241
RL = 1 kΩ to V+/2
74
92
98
RL =150Ω to V+/2
193
243
265
RL = 150Ω to V−
48
60
64
RL = 1 kΩ to V+/2
77
88
98
RL =150Ω to V+/2
202
234
261
RL = 150Ω to V−
55
V+/2
IOUT
Linear Output Current
VOUT =
RO
Output Resistance
f = 1 MHz
(Note 6)
mV
±100
mA
0.07
Ω
1.2
µA
Enable Pin Operation
Enable High Voltage Threshold
Enabled (Note 9)
Enable Pin High Current
VDISABLE = 5V
Enable Low Voltage Threshold
Disabled (Note 9)
Enable Pin Low Current
VDISABLE = 0V
3.0
V
2.0
V
2.8
µA
ton
Turn-On Time
20
ns
toff
Turn-Off Time
60
ns
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
ISD
81
96
dB
RL = ∞
3.2
3.6
4.0
Supply Current (LMH6612)
(per channel)
RL = ∞
3.2
3.7
4.25
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
120
162
mA
μA
±5V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO = 0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ.
Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
Units
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
Gain Bandwidth
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
365
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
110
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
5
115
135
MHz
MHz
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LMH6611/LMH6612
Symbol
LMH6611/LMH6612
Symbol
LSBW
Parameter
−3 dB Bandwidth Large Signal
Condition
Min
(Note 8)
Typ
(Note 7)
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
85
AV = 2, RL = 150Ω, VOUT = 2 VPP
87
Peak
Peaking
AV = 1
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
92
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
65
Max
(Note 8)
Units
MHz
0.01
dB
RF = RG = 750Ω
MHz
AV = 2, VOUT = 2 VPP, RL = 150Ω,
45
RF = RG = 680Ω
DG
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to
DP
Differential Phase
0.05
%
0.05
deg
V+/2
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
2V Step, AV = 1
3.5
ns
SR
Slew Rate
2V Step, AV = 1
460
V/μs
ts_0.1
0.1% Settling Time
2V Step, AV = −1
60
ts_0.01
0.01% Settling Time
2V Step, AV = −1
100
fC = 100 kHz, AV = 2, VOUT = 2 VPP
102
fC = 1 MHz, AV = 2, VOUT = 2 VPP
100
ns
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
dBc
fC = 5 MHz, AV = 2, VOUT = 2 VPP
81
en
Input Voltage Noise
f = 100 kHz
10
nV/
in
Input Current Noise
f = 100 kHz
2
pA/
CT
Crosstalk
(LMH6612)
f = 5 MHz, VIN = 2 VPP
71
dB
Input DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = −4.5V
0.074
±0.600
±1.1
Input Offset Voltage
(LMH6612)
VCM = −4.5V
0.095
±0.600
±1.3
TCVOS
Input Offset Voltage Average
Drift
(Note 5)
0.4
IB
Input Bias Current
VCM = −4.5V
−6.5
−10.1
−11.1
μA
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
2.5
RIN
Input Resistance
CMVR
Input Voltage Range
DC, CMRR ≥ 81 dB
CMRR
Common Mode Rejection Ratio
VCM Stepped from −5.1V to 3.7V
81
98
AOL
Open Loop Gain
RL = 1 kΩ, VOUT = +4.6V to −4.6V
96
103
RL = 150Ω, VOUT = +4.3V to −4.3V
80
87
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µV/°C
pF
6
−5.2
6
mV
MΩ
3.8
V
dB
dB
Parameter
Condition
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
RL = 1 kΩ to GND
107
125
130
RL =150Ω to GND
339
402
433
RL = 1 kΩ to GND
107
118
125
RL =150Ω to GND
340
375
407
RL = 1 kΩ to GND
103
123
132
RL =150Ω to GND
332
404
445
RL = 150Ω to V−
54
70
74
RL = 1 kΩ to GND
108
120
135
RL =150Ω to GND
348
389
434
RL = 150Ω to V−
65
Units
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
mV
IOUT
Linear Output Current
VOUT = GND (Note 6)
±120
mA
RO
Output Resistance
f = 1 MHz
0.07
Ω
Enable Pin Operation
Enable High Voltage Threshold
Enabled (Note 9)
Enable Pin High Current
VDISABLE = +5V
Enable Low Voltage Threshold
Disabled (Note 9)
Enable Pin Low Current
VDISABLE = −5V
0.5
V
17.0
µA
−0.5
V
18.6
µA
ton
Turn-On Time
19
ns
toff
Turn-Off Time
60
ns
96
dB
Power Supply Performance
PSRR
Power Supply Rejection Ratio
DC, VCM = −4.5V, VS = 2.7V to 11V
IS
Supply Current (LMH6611)
RL = ∞
3.3
3.8
4.4
Supply Current (LMH6612)
(per channel)
RL = ∞
3.45
4.05
4.85
Disable Shutdown Current
(LMH6611)
DISABLE = −5V
160
212
ISD
81
mA
μA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Boldface limits apply to temperature range of −40°C to 125°C
Note 5: Voltage average drift is determined by dividing the change in VOS by temperature change.
Note 6: Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may damage the part.
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality
Control (SQC) method.
Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.
7
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LMH6611/LMH6612
Symbol
LMH6611/LMH6612
Connection Diagrams
6-Pin TSOT23
8-Pin SOIC
30033601
Top View
30033678
Top View
Ordering Information
Package
Part Number
Package Marking
LMH6611MK
6-Pin TSOT23
8-Pin SOIC
LMH6611MKE
AX4A
250 Units Tape and Reel
LMH6611MKX
3k Units Tape and Reel
LMH6612MA
95 Rail/Units
LMH6612MAE
LMH6612MAX
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Transport Media
NSC Drawing
Status
MK06A
Released
M08A
Preliminary
1k Units Tape and Reel
LMH6612MA
250 Units Tape and Reel
2.5k Units Tape and Reel
8
At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
30033624
30033625
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies (Gain = +2)
30033604
30033605
Closed Loop Gain vs. Frequency for
Various Temperatures
Closed Loop Gain vs. Frequency for
Various Temperatures
30033654
30033655
9
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LMH6611/LMH6612
Typical Performance Characteristics
AV ≠ +1, unless otherwise specified.
LMH6611/LMH6612
Closed Loop Gain vs. Frequency for
Various Gains
Large Signal Frequency Response
30033630
30033623
Large Signal Frequency Response
±0.1 dB Gain Flatness for Various Supplies
30033626
30033631
±0.1 dB Gain Flatness for Various Supplies
±0.1 dB Gain Flatness for Various Supplies
30033606
30033627
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10
±0.1 dB Gain Flatness for Various Supplies (Gain = +2)
30033675
30033607
Small Signal Frequency Response with
Various Capacitive Load
Small Signal Frequency Response with
Capacitive Load and Various RISO
30033608
30033609
HD2 and HD3 vs. Frequency and Supply Voltage
HD2 and HD3 vs. Frequency and Load
30033653
30033650
11
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LMH6611/LMH6612
±0.1 dB Gain Flatness for Various Supplies
LMH6611/LMH6612
HD2 and HD3 vs. Common Mode Voltage
HD2 and HD3 vs. Common Mode Voltage
30033677
30033681
HD2 vs. Frequency and Gain
HD3 vs. Frequency and Gain
30033651
30033652
Open Loop Gain and Phase
HD2 vs. Output Swing
30033676
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30033682
12
LMH6611/LMH6612
HD3 vs. Output Swing
HD2 vs. Output Swing
30033683
30033693
HD2 vs. Output Swing
HD3 vs. Output Swing
30033694
30033684
HD3 vs. Output Swing
Settling Time vs. Input Step Amplitude
30033686
30033685
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LMH6611/LMH6612
Settling Time vs. Input Step Amplitude
Input Noise vs. Frequency
30033687
30033674
VOS vs. VOUT
VOS vs. VOUT
30033661
30033668
VOS vs. VCM
VOS vs. VS
30033660
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30033658
14
LMH6611/LMH6612
VOS vs. IOUT
VOS Distribution
30033669
30033672
IB vs. VS
IS vs. VS
30033657
30033659
VOUT vs. VS
VOUT vs. VS
30033690
30033691
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LMH6611/LMH6612
VOUT vs. VS
Closed Loop Output Impedance vs. Frequency AV = +1
30033696
30033671
Circuit for Positive (+) PSRR Measurement
+PSRR vs. Frequency
30033688
30033633
Circuit for Negative (−) PSRR Measurement
−PSRR vs. Frequency
30033689
30033634
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LMH6611/LMH6612
CMRR vs. Frequency
Crosstalk vs. Frequency
30033632
30033697
Small Signal Step Response
Small Signal Step Response
30033610
30033611
Small Signal Step Response
Small Signal Step Response
30033612
30033614
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LMH6611/LMH6612
Small Signal Step Response
Small Signal Step Response
30033615
30033616
Small Signal Step Response
Small Signal Step Response
30033617
30033618
Small Signal Step Response
Large Signal Step Response
30033619
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30033613
18
LMH6611/LMH6612
Large Signal Step Response
Overload Recovery Response
30033620
30033621
IS vs. VDISABLE
30033656
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LMH6611/LMH6612
Application Information
The LMH6611 and LMH6612 are based on National
Semiconductor’s proprietary VIP10 dielectrically isolated
bipolar process. This device family architecture features the
following:
• Complimentary bipolar devices with exceptionally high ft
(∼8 GHz) even under low supply voltage (2.7V) and low
bias current.
• Common emitter push-push output stage. This
architecture allows the output to reach within millivolts of
either supply rail.
• Consistent performance with little variation from any
supply voltage (2.7V - 11V) for the most important
specifications (e.g. BW, SR, IOUT.)
• Significant power saving compared to competitive devices
on the market with similar performance.
With 3V supplies and a common mode input voltage range
that extends beyond either supply rail, the LMH6611 is well
suited to many low voltage/low power applications. Even with
3V supplies, the −3 dB BW (at AV = +1) is typically 305 MHz.
The LMH6611 and LMH6612 are designed to avoid output
phase reversal. With input overdrive, the output is kept near
the supply rail (or as close to it as mandated by the closed
loop gain setting and the input voltage). Figure 1 shows the
input and output voltage when the input voltage significantly
exceeds the supply voltages.
30033639
FIGURE 2. Input Equivalent Circuit During Shutdown
When the LMH6611 is shutdown, there may be current flow
through the internal diodes shown, caused by input potential,
if present. This current may flow through the external feedback resistor and result in an apparent output signal. In most
shutdown applications the presence of this output is inconsequential. However, if the output is “forced” by another device, the other device will need to conduct the current
described in order to maintain the output potential.
To keep the output at or near ground during shutdown when
there is no other device to hold the output low, a switch using
a transistor can be used to shunt the output to ground.
SELECTION OF RF AND EFFECT ON STABILITY AND
PEAKING
The peaking of the LMH6611 depends on the value of the
RF. From the graph shown in Figure 3, as the RF value increases, the peaking increases.
For AV = 2, at RF = 1 kΩ, the −3 dB bandwidth is 113 MHz
and peaking is about 0.6 dB whereas at RF = 665Ω, the −3
dB bandwidth is about 110 MHz and peaking is 0 dB. RF and
the input capacitance form a pole in the amplifier’s response.
If the time constant is too big, it will cause peaking and ringing.
Except for AV = 1 when RF should be 0Ω, across all other gain
settings it is recommended that RF remain between 500Ω and
1 kΩ to ensure optimum performance.
30033622
FIGURE 1. Input and Output Shown with CMVR Exceeded
If the input voltage range is exceeded by more than a diode
drop beyond either rail, the internal ESD protection diodes will
start to conduct. The current flow in these ESD diodes should
be externally limited.
SHUTDOWN CAPABILITY AND TURN ON/OFF
BEHAVIOR
The LMH6611 can be shutdown by connecting the
DISABLE pin to a voltage 0.5V below the supply midpoint
which will reduce the supply current to typically 120 µA. The
DISABLE pin is “active low” and can be connected through a
resistor to V+ or left floating for normal operation. Shutdown
is guaranteed when the DISABLE pin is 0.5V below the supply
midpoint at any operating supply voltage and temperature.
Typical turn on time is 20 ns and the turn off time is 60 ns.
In the shutdown mode, essentially all internal device biasing
is turned off in order to minimize supply current flow and the
output goes into high impedance mode. During shutdown, the
input stage has an equivalent circuit as shown in Figure 2.
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30033692
FIGURE 3. Closed Loop Gain vs. Frequency and RF = RG
20
f −3 dB (MHz)
665
110
0
1000
113
0.6
quired to drive the input of the ADC. To minimize the droop in
the input voltage, external shunt capacitance (CL) should be
about ten times larger than the internal input capacitance of
the ADC and external series resistance (RL) should be large
enough to maintain the phase delay at the output of the op
amp and hence maintain the stability (See Figure 4) . Most
applications benefit from the inclusion of a series isolation resistor connected between the op amp output and ADC input.
This series resistor helps to limit the output current of the op
amp. The value chosen for this series resistor is very important, as a higher value will increase the load impedance seen
by the op amp and improve the total harmonic distortion
(THD) performance of the op amp; however, the ADC prefers
a low impedance source driving it. Thus, the optimum value
for this series resistor must be found so that it will offer the
best performance in terms of THD, SNR and SFDR of the
combined op amp and ADC.
Peaking (dB)
MINIMIZING NOISE
and an input curWith a low input voltage noise of 10 nV/
rent noise of 2 pA
the LMH6611 and LMH6612 are suitable for high accuracy applications. Still being able to reduce
the frequency band of operation of the various noise sources
(i.e. op amp noise voltage, resistor thermal noise, input noise
current) can further improve the noise performance of a system. In a non-inverting amplifier configuration inserting a
capacitor, CG, in series with the gain setting resistor, RG, will
reduce the gain of the circuit below frequency, f =
1/2πRGCG. This can be set to reduce the contribution of noise
from the 1/f region. Alternatively applying a feedback capacitor, CF, in parallel with the feedback resistor, RF, will introduce
a pole into your system at f = 1/2πRFCF and create a low pass
filter. This filter can be set to reduce high frequency noise and
harmonics. Finally remember to keep resistor values as small
as possible for a given application in order to reduce resistor
thermal noise.
Important Specifications of Op Amp and ADC
When interfacing an ADC with an op amp it is imperative to
understand the specifications that are important to get the
expected performance results. Modern ADC AC specifications such as THD, SNR, settling time and SFDR are critical
for filtering, test and measurement, video and reconstruction
applications. The high performance op amp’s settling time,
THD, and noise performance must be better than that of the
ADC it is driving to maintain the proper system accuracy with
minimal or no error.
Some system applications require low THD, low SFDR and
wide dynamic range (SNR), whereas some system applications require high SNR and they may sacrifice THD and SFDR
to focus on the noise performance.
Noise is a very important specification for both the op amp
and the ADC. There are three main sources of noise that
contribute to the overall performance of the ADC: Quantization noise, noise generated by the ADC itself (particularly at
higher frequencies) and the noise generated by the application circuit. The impedance of the input source affects the
noise performance of the op amp. Theoretically, an ADC’s
signal to noise ratio (SNR) can be found from the equation:
POWER SUPPLY BYPASS
Since the LMH6611 and LMH6612 are wide bandwidth amplifiers, proper power supply bypassing is critical for optimum
performance. Improper power supply bypassing can result in
large overshoot, ringing or oscillation. 0.1 μF capacitors
should be connected from the supply pins, V+ and V−, to
ground, as close to the device as is practical. Additionally, a
10 μF electrolytic capacitor should be connected from both
supply pins to ground reasonably close to the device. Finally,
near the device a 0.1 μF ceramic capacitor between the supplies will provide the best harmonic distortion performance.
INTERFACING HIGH PERFORMANCE OP AMPS WITH
ADCs
These amplifiers are designed for ease of use in a wide range
of applications requiring high speed, low supply current, low
noise, and the ability to drive complex ADC and video loads.
The source that drives the modern high resolution analog-todigital converters (ADCs) sees a high frequency AC load and
a DC load of a few hundred ohms or more. Thus, a high performance op amp with high input impedance of a few mega
ohms and low output impedance would be an ideal choice as
an input ADC driver. The LMH6611/LMH6612 have the low
output impedance of 0.07Ω at f = 1 MHz. The ADC driver acts
as a buffer and a low pass filter to reduce the overall system
noise. To utilize the full dynamic range of the ADC, the ADC
input has to be driven to full scale input voltage.
As signals travel through the traces of a printed circuit board
(PCB) and long cables, system noise accumulates in the signals and a differential ADC rejects any signals noise that
appears as a common mode voltage. There are a couple of
advantages to using differential signals rather than singleended signals. First, differential signals double the dynamic
range of the ADC and second, they offer better harmonic distortion performance. There are several ways to produce differential signals from a dual op amp configuration. One
method is to utilize the single-ended to differential conversion
technique and the other is the differential to differential conversion technique. The first method requires a single input
source and the second method requires differential input
source.
A real world input source can have non-ideal impedance thus
the buffer amplifier, with very low output impedance, is re-
SNR (in dB) = 6.02*N+1.72
where N is the resolution of the ADC. For example, according
to this equation a 12-bit ADC has an SNR of 74 dB. However,
the practical SNR number would be about 72 dB. In order to
achieve better SNR, the ADC driver noise should be as small
as possible. The LMH6611/LMH6612 have the low voltage
noise of only 10 nV/
.
The combined settling time of the op amp and the ADC must
be within 1 LSB. The 0.01% settling time of the LMH6611/
LMH6612 is 100 ns.
The ADC driver’s THD should be inherently lower than that of
the ADC. The LMH6611/LMH6612 have an SFDR of 96 dBc
at 2 VPP output and 1 MHz input frequency.
Signal to Noise and Distortion (SINAD) is a parameter which
is the combination of the SNR and THD specifications. SINAD
is defined as the RMS value of the output signal to the RMS
value of all of the other spectral components below half the
clock frequency, including harmonics but excluding DC. It can
be calculated from SNR and THD according to the equation:
21
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LMH6611/LMH6612
RF = RG
LMH6611/LMH6612
uration is preferred over the non-inverting configuration, as it
offers more linear output response. Table 1 shows the performance data of the LMH6611 combined with the ADC121S101. The ADC driver’s cutoff frequency of 500 kHz is
found from the equation:
Because SINAD compares all undesired frequency components with the input frequency, it is an overall measure of an
ADC’s dynamic performance. The following sections will discuss the three different ADC driver architectures in detail.
SINGLE TO SINGLE ADC DRIVER
This architecture has a single-ended input source connected
to the input of the op amp and the single-ended output of the
op amp is then fed to the single-ended input of the ADC. The
low noise of only 10 nV/
and a wide bandwidth of 345 MHz
make the LMH6611 an excellent choice for driving the 12-bit
ADC121S101 500 KSPS to 1 MSPS ADC, which has a successive approximation architecture with internal sample and
hold circuits. Figure 2 shows the schematic of the LMH6611
in a 2nd order multiple-feedback with gain of −1 (inverting)
configuration, driving an ADC121S101. The inverting config-
The op amp’s gain is set by the equation:
30033629
FIGURE 4. Single to Single ADC Driver
TABLE 1. Performance of the LMH6611 Combined with the ADC121S101
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
4
70.2
(dB)
(dB)
(dBc)
71.6
−75.7
77.6
•
•
When the op amp and the ADC are using the same supply, it
is important that both devices are well bypassed. A 0.1 µF
ceramic capacitor and a 10 µF tantalum capacitor should be
located as close as possible to each supply pin. A sample
layout is shown in Figure 5. The 0.1 µF capacitors (C13 and
C6) and the 10 µF capacitors (C11 and C5) are located very
close to the supply pins of the LMH6611 and the ADC121S101.
The following are recommendations for the design of PCB
layout in order to obtain the optimum high frequency performance:
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•
•
•
22
ENOB
Notes
11.4
ADC121S101 @ f = 200 kHz
Place ADC and amplifier as close together as possible.
Put the supply bypassing capacitors as close as possible
to the device (<1”).
Utilize surface mount instead of through-hole components
and ground and power planes.
Keep the traces short where possible.
Use terminated transmission lines for long traces.
LMH6611/LMH6612
30033640
FIGURE 5. LMH6611 and ADC121S101 Layout
non-inverting inputs of both op amps U1 and U2. This configuration produces differential ±2.5 VPP output signals, when
the single-ended input signal of 0 to VREF is AC coupled into
the non-inverting terminal of the op amp and each non-inverting terminal of the op amp is biased at the mid-scale of
2.5V. The two output RC anti-aliasing filters are used between
both the outputs of U1 and U2 and the input of the ADC121S625 to minimize the effect of undesired high frequency
noise coming from the input source. Each RC filter has the
cutoff frequency of approximately 22 MHz.
SINGLE-ENDED TO DIFFERENTIAL ADC DRIVER
The single-ended to differential ADC driver in Figure 3 utilizes
an LMH6612 dual op amp to buffer a single-ended source to
drive an ADC with differential inputs. One of the op amps is
configured as a unity gain buffer that drives the inverting
(IN−) input of the op amp U2 and non-inverting (IN+) input of
the ADC121S625. U2 inverts the input signal and drives the
inverting input of the ADC121S625. U2 is configured for a gain
of +2 to reduce the noise without sacrificing THD performance. The common mode voltage of 2.5V is set up at the
30033680
FIGURE 6. Single-Ended to Differential ADC Driver
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LMH6611/LMH6612
The performance of the LMH6612 with the ADC121S625 is
shown in Table 2.
TABLE 2. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
(dB)
(dB)
(dBc)
2.5
68.8
69
−81.5
75.1
ENOB
Notes
11.2
ADC121S625 @ f = 20 kHz
single ADC drivers. Each output from these drivers goes to a
separate input of the differential ADC. Here, each single to
single ADC driver uses the same components and is configured for a gain of -1 (inverting).
DIFFERENTIAL TO DIFFERENTIAL ADC DRIVER
The LMH6612 dual op amp can be configured as a differential
to differential ADC driver to buffer a differential source to a
differential input ADC as shown in Figure 7. The differential
to differential ADC driver can be formed using two single to
30033642
FIGURE 7. Differential to Differential ADC Driver
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24
ADC, the maximum input of 2.5 VPP is applied to the ADC
input. Figure 8 shows the FFT plot of the LMH6612 and ADC121S625 combination tested at f = 20 kHz input frequency.
TABLE 3. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
SNR
THD
SFDR
(dB)
(dB)
(dB)
(dBc)
ENOB
Notes
2.5
72.2
72.3
−87.7
92.1
11.7
ADC121S625 @ f = 20 kHz
2.5
72.2
72.2
−87.8
90.8
11.7
ADC121S625 @ f = 200 kHz
30033673
FIGURE 8. The FFT Plot of Differential to Differential ADC Driver
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LMH6611/LMH6612
The following table summarizes the performance of the
LMH6612 combined with the ADC121S625 at two different
frequencies. In order to utilize the full dynamic range of the
LMH6611/LMH6612
DC LEVEL SHIFTING
Often a signal must be both amplified and level shifted while
using a single supply for the op amp. The circuit in Figure 9
can do both of these tasks. The procedure for specifying the
resistor values is as follows.
1. Determine the input voltage.
2. Calculate the input voltage midpoint, VINMID = VINMIN +
(VINMAX – VINMIN)/2.
3. Determine the output voltage needed.
4. Calculate the output voltage midpoint, VOUTMID =
VOUTMIN + (VOUTMAX – VOUTMIN)/2.
5. Calculate the gain needed, gain = (VOUTMAX – VOUTMIN)/
(VINMAX – VINMIN)
6. Calculate the amount the voltage needs to be shifted
from input to output, ΔVOUT = VOUTMID – gain x VINMID.
7. Set the supply voltage to be used.
8. Calculate the noise gain, noise gain = gain + ΔVOUT/VS.
9. Set RF.
10. Calculate R1, R1 = RF/gain.
11. Calculate R2, R2 = RF/(noise gain-gain).
12. Calculate RG, RG= RF/(noise gain – 1).
Check that both the VIN and VOUT are within the voltage
ranges of the LMH6611.
30033648
FIGURE 9. DC Level Shifting
The following example is for a VIN of 0V to 1V with a VOUT of
2V to 4V.
1. VIN = 0V to 1V
2. VINMID = 0V + (1V – 0V)/2 = 0.5V
3. VOUT = 2V to 4V
4. VOUTMID = 2V + (4V – 2V)/2 = 3V
5. Gain = (4V – 2V)/(1V – 0V) = 2
6. ΔVOUT = 3V – 2 x 0.5V = 2
7. For the example the supply voltage will be +5V.
8. Noise gain = 2 + 2/5V = 2.4
9. RF = 2 kΩ
10. R1 = 2 kΩ/2 = 1 kΩ
11. R2 = 2 kΩ/(2.4-2) = 5 kΩ
12. RG = 2 kΩ/(2.4 – 1) = 1.43 kΩ
of +1 and a −3 dB point of 1 MHz. Values can be determined
by using the WEBENCH® Active Filter Designer found at
www.amplifiers.national.com.
4th ORDER MULTIPLE FEEDBACK LOW-PASS FILTER
Figure 10 shows the LMH6612 used as the amplifier in a multiple feedback low pass filter. This filter is set up to have a gain
30033628
FIGURE 10. 4th Order Multiple Feedback Low-Pass Filter
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26
(1)
(2)
30033665
30033641
FIGURE 13. Bode Plot of Noise Gain Intersecting with Op
Amp Open Loop Gain
FIGURE 11. Current Sense Amplifier
TRANSIMPEDANCE AMPLIFIER
By definition, a photodiode produces either a current or voltage output from exposure to a light source. A Transimpedance Amplifier (TIA) is utilized to convert this low-level
current to a usable voltage signal. The TIA often will need to
be compensated to insure proper operation.
Figure 13 shows the bode plot of the noise gain intersecting
the op amp open loop gain. With larger values of gain, CT and
RF create a zero in the transfer function. At higher frequencies
the circuit can become unstable due to excess phase shift
around the loop.
A pole at fP in the noise gain function is created by placing a
feedback capacitor (CF) across RF. The noise gain slope is
flattened by choosing an appropriate value of CF for optimum
performance.
Theoretical expressions for calculating the optimum value of
CF and the expected −3 dB bandwidth are:
(3)
(4)
Equation 4 indicates that the −3 dB bandwidth of the TIA is
inversely proportional to the feedback resistor. Therefore, if
the bandwidth is important then the best approach would be
to have a moderate transimpedance gain stage followed by a
broadband voltage gain stage.
Table 4 shows the measurement results of the LMH6611 with
different photodiodes having various capacitances (CPD) and
a feedback resistance (RF) of 1 kΩ.
30033662
FIGURE 12. Photodiode Modeled with Capacitance
Elements
Figure 12 shows the LMH6611 modeled with photodiode and
the internal op amp capacitances. The LMH6611 allows circuit operation of a low intensity light due to its low input bias
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LMH6611/LMH6612
current by using larger values of gain (RF). The total capacitance (CT) on the inverting terminal of the op amp includes
the photodiode capacitance (C PD) and the input capacitance
of the op amp (CIN). This total capacitance (CT) plays an important role in the stability of the circuit. The noise gain of this
circuit determines the stability and is defined by:
CURRENT SENSE AMPLIFIER AND OPTIMIZING
ACCURACY IN PRECESION APPLICATIONS
With it’s rail-to-rail output capability, low VOS, and low IB the
LMH6611 is an ideal choice for a current sense amplifier application. Figure 11 shows the schematic of the LMH6611 set
up in a low-side sense configuration which provides a conversion gain of 2V/A. Voltage error due to VOS can be calculated to be VOS x (1 + RF/RG) or 0.6 mV x 21 = 12.6 mV.
Voltage error due to IO is I O x R F or 0.5 µA x 1 kΩ = 0.5 mV.
Hence worst case total voltage error is 12.6 mV + 0.5 mV or
13.1 mV which translates into a current error of 13.1 mV/(2 V/
A) = 6.55 mA.
This circuit employs DC source resistance matching at the
two input terminals in order to minimize the output DC error
caused by input bias current. Another technique to reduce
output offset in a non-inverting amplifier configuration is to introduce a DC offset current into the inverting input of the
amplifier. To ensure minimal impact on frequency response
be sure to inject the DC offset current through large resistors.
Conversely if optimizing an inverting amplifier configuration
simply apply offset adjustment to the non-inverting input.
LMH6611/LMH6612
TABLE 4. TIA (Figure 1) Compensation and Performance Results
CPD
CT
CF CAL
CF USED
f −3 dB CAL
f −3 dB MEAS
Peaking
(pF)
22
(pF)
(pF)
(pF)
(MHz)
(MHz)
(dB)
24
5.42
5.6
29.3
27.1
0.5
47
49
7.75
8
20.5
21
0.5
100
102
11.15
12
14.2
15.2
0.5
222
224
20.39
18
9.6
10.7
0.5
330
332
20.2
22
7.9
9
0.8
Note:
GBWP = 130 MHz
CT = CPD + CIN
CIN = 2 pF
VS = ±2.5V
Figure 14 shows the frequency response for the various photodiodes in Table 4.
When analyzing the noise at the output of the TIA, it is important to note that the various noise sources (i.e. op amp
noise voltage, feedback resistor thermal noise, input noise
current, photodiode noise current) do not all operate over the
same frequency band. Therefore, when the noise at the output is calculated, this should be taken into account. The op
amp noise voltage will be gained up in the region between the
noise gain’s zero and pole (fZ and fP in Figure 13). The higher
the values of RF and CT, the sooner the noise gain peaking
starts and therefore its contribution to the total output noise
will be larger. It is advantageous to minimize CIN by proper
choice of op amp or by applying a reverse bias across the
diode but this will be at the expense of excess dark current
and noise.
30033635
FIGURE 14. Frequency Response for Various Photodiode
and Feedback Capacitors
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28
LMH6611/LMH6612
Physical Dimensions inches (millimeters) unless otherwise noted
6-Pin TSOT23
NS Package Number MK06A
8-Pin SOIC
NS Package Number M08A
29
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LMH6611/LMH6612 PowerWise Single Supply 345 MHz Rail-to-Rail Output Amplifiers
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