ASAHI KASEI [AK5358] AK5358 96kHz 24-Bit ∆Σ ADC GENERAL DESCRIPTION The AK5358 is a stereo A/D Converter with wide sampling rate of 8kHz ∼ 96kHz and is suitable for consumer to professional audio system. The AK5358 achieves high accuracy and low cost by using Enhanced dual bit ∆Σ techniques. The AK5358 requires no external components because the analog inputs are single-ended. The audio interface has two formats (MSB justified, I2S) and can correspond to various systems like DTV, DVR and AV Receiver. FEATURES Linear Phase Digital Anti-Alias Filtering Single-ended Input Digital HPF for DC-Offset cancel S/(N+D): 92dB DR: 102dB S/N: 102dB Sampling Rate Ranging from 8kHz to 96kHz Master Clock: 256fs/384fs/512fs/768fs (8kHz ∼ 48kHz) 256fs/384fs (48kHz ∼ 96kHz) Input level: CMOS Master / Slave Mode Audio Interface: 24bit MSB justified / I2S selectable Power Supply: 4.5 ∼ 5.5V (Analog), 2.7 ∼ 3.6V (Digital) Ta = −20 ∼ 85°C Small 16pin TSSOP Package AK5357/59/81 Pin-compatible VA AGND MCLK VD DGND Clock Divider AINL AINR VCOM ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter LRCK SCLK Serial I/O Interface Voltage Reference CKS2 CKS1 CKS0 PDN MS0438-E-00 SDTO DIF 2005/11 -1- ASAHI KASEI [AK5358] Ordering Guide −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK5358 AK5358ET AKD5358 Pin Layout AINR 1 16 CKS0 AINL 2 15 CKS2 CKS1 3 14 DIF VCOM 4 13 PDN AGND 5 12 SCLK VA 6 11 MCLK VD 7 10 LRCK DGND 8 9 SDTO Top View Compatibility with AK5357, AK5359 and AK5381 fs S/(N+D) DR VIH@TTL Level Mode VA (Analog Supply) VD (Digital Supply) HPF Disable Operating Temperature AK5357 4kHz to 96kHz 88dB 102dB 2.2V 2.7 to 5.5V AK5358 8kHz to 96kHz 92dB 102dB 2.2V 4.5 to 5.5V 2.7 to 5.5V 2.7 to 3.6V Available ET: −20 ∼ +85°C VT: −40 ∼ +85°C Not Available ET: −20 ∼ +85°C MS0438-E-00 AK5381 4kHz to 96kHz 96dB 106dB 2.4V 4.5 to 5.5V 2.7 to 5.5V 3.0 to 5.5V @96kHz Available ET: −20 ∼ +85°C VT: −40 ∼ +85°C XT: −40 ∼ +85°C AK5359 8kHz to 216kHz 94dB 102dB Not Available 4.5 to 5.5V 3.0 to 5.5V Available ET: −20 ∼ +85°C VT: −40 ∼ +85°C 2005/11 -2- ASAHI KASEI [AK5358] PIN / FUNCTION No. Pin Name I/O 1 2 3 AINR AINL CKS1 I I I 4 VCOM O 5 6 7 8 AGND VA VD DGND - 9 SDTO O 10 LRCK I/O 11 MCLK I 12 SCLK I/O 13 PDN I 14 DIF I 15 16 CKS2 CKS0 I I Function Rch Analog Input Pin Lch Analog Input Pin Mode Select 1 Pin Common Voltage Output Pin, VA/2 Bias voltage of ADC input. Analog Ground Pin Analog Power Supply Pin, 4.5 ∼ 5.5V Digital Power Supply Pin, 2.7 ∼ 3.6V Digital Ground Pin Audio Serial Data Output Pin “L” Output at Power-down mode. Output Channel Clock Pin “L” Output in Master Mode at Power-down mode. Master Clock Input Pin Audio Serial Data Clock Pin “L” Output in Master Mode at Power-down mode. Power Down Mode & Reset Pin “H”: Power up, “L”: Power down & Reset The AK5358 must be reset once upon power-up. Audio Interface Format Pin “H”: 24bit I2S Compatible, “L”: 24bit MSB justified Mode Select 2 Pin Mode Select 0 Pin Note: All input pins except analog input pins (AINR, AINL) should not be left floating. Handling of Unused Pin The unused input pins should be processed appropriately as below. Classification Analog Pin Name AINL AINR MS0438-E-00 Setting This pin should be open. This pin should be open. 2005/11 -3- ASAHI KASEI [AK5358] ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note 1) Parameter Symbol VA Analog Power Supplies: VD Digital ∆GND |AGND – DGND| (Note 2) Input Current, Any Pin Except Supplies IIN Analog Input Voltage (AINL, AINR, CKS1 pins) VINA Digital Input Voltage (Note 3) VIND Ambient Temperature (powered applied) Ta Storage Temperature Tstg Note 1. All voltages with respect to ground. Note 2. AGND and DGND must be connected to the same analog ground plane. Note 3. . PDN, DIF, MCLK, SCLK, LRCK, CKS0, CKS2 pins min −0.3 −0.3 −0.3 −0.3 −20 −65 max 6.0 4.6 0.3 ±10 VA+0.3 VD+0.3 85 150 Units V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 4.5 5.0 (Note 4) Digital VD 2.7 3.3 Note 4. The power up sequence between VA and VD is not critical. max 5.5 3.6 Units V V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0438-E-00 2005/11 -4- ASAHI KASEI [AK5358] ANALOG CHARACTERISTICS (Ta=25°C; VA=5.0V, VD=3.3V; AGND=DGND=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Resolution 24 Bits Input Voltage (Note 5) 2.7 3.0 3.3 Vpp S/(N+D) fs=48kHz −1dBFS 82 92 dB BW=20kHz −60dBFS 39 dB −1dBFS 90 dB fs=96kHz BW=40kHz −60dBFS 38 dB DR (−60dBFS, A-weighted) 94 102 dB S/N (A-weighted) 94 102 dB Input Resistance fs=48kHz fs=96kHz Interchannel Isolation Interchannel Gain Mismatch Gain Drift Power Supply Rejection 13 9 90 (Note 6) - 20 14 110 0.1 100 50 0.5 - kΩ kΩ dB dB ppm/°C dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) VA 12 18 VD (fs=48kHz) 3 5 VD (fs=96kHz) 6 9 Power down mode (PDN pin = “L”) (Note 7) VA+VD 10 100 Note 5. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.6 x VA (Vpp). Note 6. PSR is applied to VA and VD with 1kHz, 50mVpp. Note 7. All digital input pins and CKS1 pin are held VD or DGND. MS0438-E-00 mA mA mA µA 2005/11 -5- ASAHI KASEI [AK5358] FILTER CHARACTERISTICS (fs=48kHz) (Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 8) ±0.1dB PB 0 −0.2dB 20.0 −3.0dB 23.0 Stopband SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion ∆GD 0 Group Delay (Note 9) GD 16 ADC Digital Filter (HPF): Frequency Response (Note 8) −3dB FR 1.0 −0.1dB 6.5 max Units 18.9 - kHz kHz kHz kHz dB dB µs 1/fs ±0.04 Hz Hz FILTER CHARACTERISTICS (fs=96kHz) (Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 8) ±0.1dB PB 0 37.8 kHz −0.2dB 40.0 kHz −3.0dB 46.0 kHz Stopband SB 56 kHz Passband Ripple PR ±0.04 dB Stopband Attenuation SA 68 dB Group Delay Distortion ∆GD 0 µs Group Delay (Note 9) GD 16 1/fs ADC Digital Filter (HPF): Frequency Response (Note 8) −3dB FR 2.0 Hz −0.1dB 13.0 Hz Note 8. The passband and stopband frequencies scale with fs. For example, PB=18.9kHz@±0.1dB is 0.39375 × fs. Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. MS0438-E-00 2005/11 -6- ASAHI KASEI [AK5358] DC CHARACTERISTICS (CMOS Level Mode) (Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V) Parameter Symbol min typ High-Level Input Voltage VIH 70%VD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−1mA) VOH VD−0.5 Low-Level Output Voltage (Iout=1mA) VOL Input Leakage Current Iin - MS0438-E-00 max 30%VD 0.5 ±10 Units V V V V µA 2005/11 -7- ASAHI KASEI [AK5358] SWITCHING CHARACTERISTICS (Ta=-20°C ∼ 85°C; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing 512fs, 256fs Frequency fCLK 2.048 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 768fs, 384fs Frequency fCLK 3.072 Pulse Width Low tCLKL 10.5 Pulse Width High tCLKH 10.5 LRCK Frequency Duty Cycle fs Slave mode Master mode Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “↑” (Note 10) SCLK “↑” to LRCK Edge (Note 10) LRCK to SDTO (MSB) (Except I2S mode) SCLK “↓” to SDTO Master mode SCLK Frequency SCLK Duty SCLK “↓” to LRCK SCLK “↓” to SDTO typ max Units 24.576 MHz ns ns MHz ns ns 36.864 8 45 96 55 50 tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD fSCK dSCK tMSLR tSSD 160 65 65 30 30 Reset Timing tPD PDN Pulse Width (Note 11) 150 tPDV PDN “↑” to SDTO valid at Slave Mode (Note 12) tPDV PDN “↑” to SDTO valid at Master Mode (Note 12) Note 10. SCLK rising edge must not occur at the same time as LRCK edge. Note 11. The AK5358 can be reset by bringing the PDN pin = “L”. Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”. MS0438-E-00 35 35 ns ns ns ns ns ns ns 20 35 Hz % ns ns 64fs 50 −20 −20 4132 4129 kHz % % ns 1/fs 1/fs 2005/11 -8- ASAHI KASEI [AK5358] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tSCK VIH SCLK VIL tSCKH tSCKL Clock Timing VIH LRCK VIL tSHLR tLRSH VIH SCLK VIL tSSD tLRS SDTO 50%VD Audio Interface Timing (Slave mode) MS0438-E-00 2005/11 -9- ASAHI KASEI [AK5358] LRCK 50%VD tMSLR dSCK SCLK 50%VD tSSD SDTO 50%VD Audio Interface Timing (Master mode) VIH PDN VIL tPDV SDTO 50%VD tPD PDN VIL Power Down & Reset Timing MS0438-E-00 2005/11 - 10 - ASAHI KASEI [AK5358] OPERATION OVERVIEW System Clock MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency, SCLK frequency and master/slave are selected by CKS2-0 pins as shown in Table 2. All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided, the AK5358 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5358 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”. fs 32kHz 44.1kHz 48kHz 96kHz MCLK 256fs 384fs 512fs 8.192MHz 12.288MHz 16.384MHz 11.2896MHz 16.9344MHz 22.5792MHz 12.288MHz 18.432MHz 24.576MHz 24.576MHz 36.864MHz N/A Table 1. System Clock Example Mode CKS2 CKS1 CKS0 0 L L L 1 2 3 4 5 6 7 L L L H H H H L H H L L H H H L H L H L H Input Level Master/Slave 768fs 24.576MHz 33.8688MHz 36.864MHz N/A MCLK 256/384fs (8k≤fs≤96k) CMOS Slave 512/768fs (8k≤fs≤48k) Reserved CMOS Master 256fs (8k≤fs≤96k) CMOS Master 512fs (8k≤fs≤48k) Reserved Reserved CMOS Master 384fs (8k≤fs≤96k) CMOS Master 768fs (8k≤fs≤48k) Table 2. Operation Mode Select SCLK ≥ 48fs or 32fs (Note 13) 64fs 64fs 64fs 64fs Note 13. SDTO outputs 16bit data at SCLK=32fs. MS0438-E-00 2005/11 - 11 - ASAHI KASEI [AK5358] Audio Interface Format Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK frequency fixed to 1fs. Mode 0 1 DIF pin L H SDTO LRCK SCLK 24bit, MSB justified H/L ≥ 48fs or 32fs 24bit, I2S Compatible L/H ≥ 48fs or 32fs Table 3. Audio Interface Format Figure Figure 1 Figure 2 LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTO(o) 23 22 4 3 2 1 0 23 22 4 3 2 1 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTO(o) 23 22 4 3 2 1 0 23 22 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz) and scales with sampling rate (fs). MS0438-E-00 2005/11 - 12 - ASAHI KASEI [AK5358] Power down The AK5358 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time). (1) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (2) GD A/D In (Analog) A/D Out (Digital) Clock In MCLK,LRCK,SCLK (3) “0”data Idle Noise “0”data Idle Noise (4) Notes: (1) 4132/fs in slave mode and 4129/fs in master mode. (2) Digital output corresponding to analog input has the group delay (GD). (3) A/D outputs “0” data at the power-down state. (4) When the external clocks (MCLK, SCLK and LRCK) are stopped, the AK5358 should be in the power-down state. Figure 3. Power-down/up sequence example System Reset The AK5358 should be reset once by bringing PDN pin “L” after power-up. In slave mode, the internal timing starts clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK. The AK5358 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input. MS0438-E-00 2005/11 - 13 - ASAHI KASEI [AK5358] SYSTEM DESIGN Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Rch In 10u + Lch In + 10u 2.2u 1 AINR CKS0 16 2 AINL CKS2 15 3 CKS1 DIF 14 4 VCOM PDN 13 5 Analog 5V Digital 3.3V + 10u 0.1u + 10u 0.1u AK5358 AGND Mode Control Reset SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO 9 Audio Controller Analog Ground System Ground Note: - AGND and DGND of the AK5358 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. - The CKS1 pin should be connected to VA or AGND. Figure 4. Typical Connection Diagram Digital Ground Analog Ground System Controller 1 AINR CKS0 16 2 AINL CKS2 15 3 CKS1 DIF 14 4 VCOM PDN 13 5 AGND SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO AK5358 9 Figure 5. Ground Layout Note: - AGND and DGND must be connected to the same analog ground plane. MS0438-E-00 2005/11 - 14 - ASAHI KASEI [AK5358] 1. Grounding and Power Supply Decoupling The AK5358 requires careful attention to power supply and grounding arrangements. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5358 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5358 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1µF ceramic capacitor. A capacitor 2.2µF is attached to VCOM pin. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5358. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 20kΩ (typ@fs=48kHz) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp (typ). The ADC output data format is 2’s complement. The internal HPF removes the DC offset. The AK5358 samples the analog inputs at 64fs (@fs=48kHz). The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5358 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. MS0438-E-00 2005/11 - 15 - ASAHI KASEI [AK5358] PACKAGE 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.65 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0438-E-00 2005/11 - 16 - ASAHI KASEI [AK5358] MARKING AKM 5358ET XXYYY 1) 2) 3) Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 5358ET Revision History Date (YY/MM/DD) 05/11/15 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0438-E-00 2005/11 - 17 -