WEDC EDI8L32128V20AC 128kx32 cmos high speed static ram Datasheet

White Electronic Designs
EDI8L32128V
128Kx32 CMOS High Speed Static RAM
FEATURES
DESCRIPTION
128Kx32 bit CMOS Static
Analog SHARC
TM
External Memory Solution
ADSP-21060L
ADSP-21062L
Random Access Memory Array
Fast Access Times: 12, 15 and 20ns
User Configurable Organization
with Minimal Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 (JEDEC MO-47AE)
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum
Noise Immunity
The EDI8L32128V is a high speed, 3.3V, four megabit
density Static RAM. The device is available with access
times of 12, 15 and 20ns, allowing the device to support
60MHZ DSPs with no wait states. The high speed, 3.3V
supply voltage and byte configurability make the device
ideal for interfacing with Analog Devices ADSP-21062L or
ADSP-21060L SHARC DSPs.
The device can be configured as a 128Kx32 and used to
create a single chip external data memory solution for the
SHARC (figure 1). Providing a 51% space savings when
compared to four 128Kx8, 400mil wide plastic SOJs. The
EDI8L32128V has a 10pf load on the data lines vs. 24pf for
four plastic SOJs. Memory upgrades in the same footprint
can be accomplished with the EDI8L32256V (256Kx32) or
the EDI8L32512V (512KX32). This is covered in detail in
the application report "The EDI's x32 MCM-L SRAM Family:
Integrated Memory Solution for the Analog SHARC DSP"
Alternatively the device's chip enables can configure it as a
256Kx16. A 256Kx48 program memory array for the SHARC
is created using three devices (figure 2). If this memory is
too deep, two 128Kx24's (EDI8L24128V) can be used to
create a 128Kx48 memory array.
Single 3.3V (±5%) Supply Operation
Note: Solder Reflow temperature should not exceed 260°C for 10 seconds
PIN CONFIGURATIONS AND
BLOCK DIAGRAM
PIN NAMES
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
DQ16
NC
NC
E3#
E2#
E1#
E0#
NC
VCC
NC
NC
G#
W#
A16
A15
A14
DQ15
AØ-A16
EØ#-E3#
W#
G#
DQØ-DQ31
VCC
VSS
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
A0-A16
G#
W#
E0#
E1#
E2#
E3#
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
DQ0
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
Address Inputs
Chip Enables (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (+3.3V±10%)
Ground
No Connection
17
128Kx32
Memory
Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Note: Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are
word select pins.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
1
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ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current.
Junction Temperature, TJ
EDI8L32128V
RECOMMENDED DC OPERATING CONDITIONS
-0.5V to 4.6V
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
0°C to + 70°C
-40°C to +85°C
-55°C to +125°C
3 Watts
20 mA
175°C
Sym
VCC
VSS
VIH
VIL
Min
3. 135V
0
2.2
-0.3
Typ
3.3
0
—
—
Max
3.465V
0
VCC+0.3
0.8
Units
V
V
V
V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
VSS to 3.0V
5ns
1.5V
Figure 1
(note: For tEHQZ,tGHQZ and tWLQZ, CL = 5pF) (see figure 2)
Figure 2
Figure 1
VCC
Z0 = 50 Ω
Q
319
65 pF
DOUT
RL = 50 Ω
353 Ω
5 pF
VL = 1.5V
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
Operating Power Supply Current
ICC1
Standby (TTL) Supply Current
ICC2
Full Standby CMOS
Supply Current
ICC3
Input Leakage Current
Output Leakage Current
Output High Volltage
Output Low Voltage
ILI
ILO
VOH
VOL
Conditions
W# = VIL, II/O = 0mA,
Min Cycle
E# VIH, VIN VIL or
VIN VIH, f=ØMHZ
E# VCC-0.2V
VIN VCC-0.2V or
VIN 0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
Min
Max
12
15
20
Units
ns
680
660
620
mA
120
120
120
mA
40
40
40
mA
±10
±10
µA
µA
V
V
2.4
0.4
Typical:TA=25°C, VCC=3.3V
TRUTH TABLE
G#
X
H
L
X
E#
H
L
L
L
W#
X
H
H
L
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
DOUT
DIN
CAPACITANCE
(f=1.0MHZ, VIN=VCC or VSS)
Power
ICC2, ICC3
ICC1
ICC1
ICC1
Parameter
Address Lines
Data Lines
Write & Output Enable Lines
Chip Enable Lines
Sym
CA
CD/Q
W#, G#
EØ# - E3#
Max
40
10
40
8
Unit
pF
pF
pF
pF
These parameters are sampled, not 100% tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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EDI8L32128V
AC CHARACTERISTICS READ CYCLE
Symbol
Parameter
JEDEC
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
12ns
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
tOE
tOLZ
tOHZ
Min
12
15ns
Max
Min
15
12
8
20ns
Max
Min
20
Max
15
10
2
3
7
20
20
3
8
3
3
5
10
3
6
2
2
4
8
2
5
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Parameter guaranteed, but not tested.
READ CYCLE 1 - W# HIGH, G#, E# LOW
tAVAV
ADDRESS 1
A
ADDRESS 2
tAVQX
tAVQV
Q
DATA 1
DATA 2
READ CYCLE 2 - W# HIGH
tAVAV
A
tAVQV
BSx#, E#
tELQV
tEHQZ
tGLQV
tGLQX
tGHQZ
tELQX
G#
Q
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July 2004
Rev. 6
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EDI8L32128V
AC CHARACTERISTICS WRITE CYCLE
Symbol
Parameter
JEDEC
tAVAV
tELWH
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tEHDX
tWLQZ
tDVWH
tDVEH
tWHQX
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Alt.
tWC
tCW
tCW
tAS
tAS
tAW
tAW
tWP
tWP
tWR
tWR
tDH
tDH
tWHZ
tDW
tDW
tWLZ
12ns
Min
12
8
8
0
0
9
9
9
9
0
0
0
0
0
5
5
2
15ns
Max
Min
15
9
9
0
0
10
10
10
10
0
0
0
0
0
6
6
2
5
20ns
Max
6
Min
20
15
15
0
0
15
15
15
15
0
0
0
0
0
8
8
2
Max
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Parameter guaranteed, but not tested.
WRITE CYCLE 1 - W# CONTROLLED
tAVAV
A
BSx#, E#
tELWH
tAVWH
tWHAX
tWLWH
W#
tAVWL
tDVWH
tWHDX
DATA VALID
D
tWLQZ
tWHQX
Q
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
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EDI8L32128V
WRITE CYCLE 2 - E# CONTROLLED
tAVAV
A
tELEH
tAVEL
BSx#, E#
tAVEH
tEHAX
tWLEH
W#
tEHDX
tDVEH
DATA VALID
D
HIGH Z
Q
ORDERING INFORMATION
Commercial (0°C to 70°C)
Part Number
EDI8L32128V12AC
EDI8L32128V15AC
EDI8L32128V20AC
Speed
(ns)
12
15
20
Industrial (-40°C to +85°C)
Package
No.
99
99
99
Part Number
Speed
(ns)
Package
No.
EDI8L32128V12AI
12
99
EDI8L32128V15AI
15
99
EDI8L32128V20AI
20
99
PACKAGE DESCRIPTION
Package No. 99
68 Lead PLCC
JEDEC MO-47AE
0.995
Max
0.956
Max
THETA JA=40°C/W
THETA JC=15°C/W
WEIGHT =4.2G
0.995 0.956
Max
Max
0.180
Max
0.040
Max
0.020
0.015
0.050
BSC
0.930
0.890
0.115
Max
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8L32128V
Figure 1
EDI8L32128V
Address Bus
A31 - A0
A16
A15
A14
A13
A12
Analog
ADSP - 2106XL
MS0#
E0#
E1#
E2#
E3#
WR#
W#
RD#
G#
D47 - D0
D
A
T
A
B
U
S
B
U
S
A4
A3
A2
A1
A0
Databus
A
D
D
R
E
S
S
DQ31
DQ30
DQ29
DQ28
DQ27
DQ4
DQ3
DQ2
DQ1
DQ0
D47 D46 .. D31 D30 .. D5 D4 D3 D2 D1 D0
Figure 2
EDI8L32128V
(Configured as 256Kx16)
D
A
T
A
B
U
S
A16-A0
E0#
E1#
E2#
E3#
W#
G#
Address Bus
A31 - A0
MS0#
MS1#
DQ31
DQ15
DQ16
DQ15
WORD1
DQ0
DQ0
WR#
EDI8L32128V
RD#
(Configured as 256Kx16)
D
A
T
A
B
U
S
A16-A0
E0#
E1#
E2#
E3#
W#
G#
Analog
ADSP - 2106XL
DQ31
DQ31
DQ16
DQ15
WORD2
DQ16
DQ0
EDI8L32128V
(Configured as 256Kx16)
D
A
T
A
B
U
S
A16-A0
E0#
E1#
E2#
E3#
W#
G#
Databus
D47 - D0
DQ31
DQ47
DQ16
DQ15
WORD3
DQ17
DQ0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8L32128V
Document Title
128Kx32 CMOS High Speed Static RAM
Revision History
Rev #
History
Release Date
Status
Rev 6
6.1 Corrected pin configuration and block diagram on page 1
7-2004
Final
6.2 Changed pin 64 from "NC" to "A16"
6.3 Added new title page
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 6
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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