IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE Integrated Device Technology, Inc. FEATURES DESCRIPTION • High-density 512K CMOS Dual-Port RAM module • Fast access times —Commercial: 30, 35ns —Military: 40, 45ns • Fully asynchronous read/write operation from either port • Easy to expand data bus width to 64 bits or more using the Master/Slave function • Separate byte read/write signals for byte control • On-chip port arbitration logic • INT flag for port-to-port communication • Full on-chip hardware support of semaphore signaling between ports • Surface mounted fine pitch (25 mil) LCC packages allow through-hole module to fit into 121 pin PGA footprint • Single 5V (±10%) power supply • Inputs/outputs directly TTL-compatible The IDT7M1002 is a 16K x 32 high-speed CMOS Dual-Port Static RAM Module constructed on a co-fired ceramic substrate using four 16K x 8 (IDT7006) Dual-Port Static RAMs in surface-mounted LCC packages. The IDT7M1002 module is designed to be used as stand-alone 512K Dual-Port RAM or as a combination Master/Slave Dual-Port RAM for 64-bit or more word width systems. Using the IDT Master/Slave approach in such system applications results in full-speed, errorfree operation without the need for additional discrete logic. The module provides two independent ports with separate control, address, and I/O pins that permit independent and asynchronous access for reads or writes to any location in memory. System performance is enhanced by facilitating port-to-port communication via additional control signals SEM and INT. The IDT7M1002 module is packaged in a ceramic 121 pin PGA (Pin Grid Array)1.35 inches on a side. Maximum access times as fast as 30ns are available over the commercial temperature range and 40ns over the military temperature range. All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest revision of MIL-STD-883, Class B making them ideally suited to applications demanding the highest level of performance and reliability. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 L_I/O(24) L_I/O(26) L_I/O(28) L_I/O(30) L_CS L_OE L_R/W(3) R_OE R_CS R_I/O(30) R_I/O(28) R_I/O(26) R_I/O(24) B L_I/O(23) L_I/O(25) L_I/O(27) L_I/O(29) L_I/O(31) L_A(0) L_R/W(4) R_A(0) R_I/O(31) R_I/O(29) R_I/O(27) R_I/O(25) R_I/O(23) C L_I/O(21) L_I/O(22) VCC L_A(3) L_A(2) L_A(1) GND R_A(1) R_A(2) R_A(3) GND R_I/O(22) R_I/O(21) D L_I/O(19) L_I/O(20) L_A(4) GND R_A(4) R_I/O(20) R_I/O(19) E L_I/O(17) L_I/O(18) L_A(5) R_A(5) R_I/O(18) R_I/O(17) F L_SEM L_I/O(16) L_A(6) R_A(6) R_I/O(16) R_SEM G L_BUSY L_INT GND GND R_INT R_BUSY H L_R/W (1) L_R/W(2) L_A(7) R_A(7) R_R/W (2) R_R/W (1) I L_I/O(15) L_I/O(14) L_A(8) R_A(8) R_I/O(14) A PGA TOP VIEW R_I/O(15) J L_I/O(13) L_I/O(12) L_A(9) R_A(9) R_I/O(12) R_I/O(13) K L_I/O(11) M/S GND L_A(10) L_A(11) L_A(12) GND R_A(12) R_A(11) R_A(10) VCC GND R_I/O(11) L L_I/O(10) L_I/O(8) L_I/O(6) L_I/O(4) L_I/O(2) L_A(13) R_R/W (4) R_A(13) R_I/O(2) R_I/O(4) R_I/O(6) R_I/O(8) R_I/O(10) M L_I/O(9) L_I/O(7) L_I/O(5) L_I/O(3) L_I/O(1) L_I/O(0) R_R/W (3) R_I/O(0) R_I/O(1) R_I/O(3) R_I/O(5) R_I/O(7) R_I/O(9) 2795 drw 01 The IDT logo is a registered trademark of Integrated Device Technology Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. DECEMBER 1995 DSC-2795/5 7.02 1 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE FUNCTIONAL BLOCK DIAGRAM MILITARY AND COMMERCIAL TEMPERATURE RANGES M/S R_A(0–13) L_A(0–13) L_I/O(0–7) R_I/O(0–7) L_ CS IDT7006 16K x 8 L_ OE L_ SEM L_ INT (ARBITRATION LOGIC) R_CS R_OE R_SEM R_INT R_BUSY R_R/W (0) L_ BUSY L_R/W (0) L_I/O(8–15) R_I/O(8–15) IDT7006 16K x 8 (ARBITRATION LOGIC) L_ R/W (1) R_ R/W (1) L_I/O(16–23) R_I/O(16–23) IDT7006 16K x 8 (ARBITRATION LOGIC) L_ R/W (2) R_R/W (2) R_I/O(24–31) L_I/O(24–31) IDT7006 16K x 8 (ARBITRATION LOGIC) L_R/W (3) R_ R/W (3) PIN NAMES 2795 drw 02 Left Port Right Port L_A (0–13) R_A (0–13) Address Inputs L_I/O (0–31) R_I/O (0–31) Data Inputs/Outputs L_R/W (1–4) R_R/W (1–4) Read/Write Enables L_CS R_CS Chip Select L_OE R_OE Output Enable L_BUSY R_BUSY Busy Flag L_INT R_INT Interrupt Flag R_SEM Semaphore Control L_SEM Description M/S VCC Master/Slave Control Power GND Ground 2795 tbl 01 7.02 2 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commerical Military Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 –0.5 to +7.0 V –55 to +125 °C Operating Temperature 0 to +70 TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C IOUT DC Output Current 50 50 mA TA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Ambient Temperature Military GND VCC –55°C to +125°C 0V 5.0V ± 10% 0°C to +70°C 0V 5.0V ± 10% Commercial 2795 tbl 03 RECOMMENDED DC OPERATING CONDITIONS Symbol 2795 tbl 02 NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage — 6.0 V — 0.8 VIL 2.2 (1) Input Low Voltage –0.5 V 2795 tbl 04 NOTE: 1. VIL ≥ –3.0V for pulse width less than 20ns DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = –55°C to +125°C or 0°C to +70°C) Symbol Parameter Test Conditions Min. Max. Units |ILI| Input Leakage (Address & Control) VCC = Max. VIN = GND to VCC — 40 µA |ILI| Input Leakage (Data) VCC = Max. VIN = GND to VCC — 10 µA |ILO| Output Leakage (Data) VCC = Max. CS ≥ VIH, VOUT = GND to V CC — 10 µA VOL Output Low VCC = Min. IOL = 4mA Voltage — 0.4 V VOH Output High Voltage VCC = Min, IOH = –4mA 2.4 — V 2795 tbl 05 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = –55°C to +125°C or 0°C to +70°C) Commercial Symbol Parameter Test Conditions Min. ICC2 Dynamic Operating Current (Both Ports Active) VCC = Max., CS ≤ VIL, SEM = Don’t Care Outputs Open, f = fMAX — ISB Standby Supply Current (Both Ports Inactive) VCC = Max., L_CS and R_CS ≥ VIH Outputs Open, f = fMAX ISB1 Standby Suppy Current (One Port Inactive) ISB2 Full Standby Supply Current (Both Ports Inactive) Max. Military Min. Max. Units 1360 — 1600 mA — 280 — 340 mA VCC = Max., L_CS or R_CS ≥ VIH Outputs Open, f = fMAX — 1000 — 1160 mA L_CS and R_CS ≥ VCC – 0.2V VIN > VCC – 0.2V or < 0.2V L_SEM and R_SEM ≥ VCC – 0.2V — 60 — 120 mA 2795 tbl 06 7.02 3 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES +5V CAPACITANCE(1) (TA = +25°C, f = 1.0MHz) Symbol Parameter Condition Max. Unit CIN (1) Input Capacitance (CS, OE, SEM, Address) VIN = 0V 40 pF CIN(2) Input Capacitance (R/W, I/O, INT) VIN = 0V 12 pF CIN(3) Input Capacitance (BUSY, M/S) VIN = 0V 45 pF COUT Output Capacitance (I/O) VOUT = 0V 12 pF 480Ω BUSY, INT 30pF* 255Ω *Including scope and jig capacitances. 2795 tbl 07 NOTE: Figure 1. Output Load 1. This parameter is guaranteed by design but not tested. 2795 drw 03 +5V AC TEST CONDITIONS Input Pulse Levels 480Ω GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels Output Load DATAOUT 1.5V 5pF* 255Ω See Figures 1 and 2 2795 tbl 08 *Including scope and jig capacitances. 2795 drw 04 Figure 2. Output Load (For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW) AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = –55°C to +125°C or 0°C to +70°C) 7M1002SxxG 30 –35 Symbol Parameter Min. Max. Min. 7M1002SxxGB –40 –45 Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 30 — 35 — 40 — 45 — ns tAA Address Access Time — 30 — 35 — 40 — 45 ns tACS(2) Chip Select Access Time — 30 — 35 — 40 — 45 ns tOE Output Enable Access Time — 17 — 20 — 22 — 25 ns tOH Output Hold from Address Change 3 — 3 — 3 — 3 — ns tLZ(1) Output to Low-Z 3 — 3 — 3 — 5 — ns tHZ Output to High-Z — 15 — 15 — 17 — 20 ns tPU(1) Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns tPD(1) Chip Deselect to Power Up Time — 50 — 50 — 50 — 50 ns tSOP Sem. Flag Update Pulse (OE or SEM) 15 — 15 — 15 — 15 — ns (1) Write Cycle tWC Write Cycle Time 30 — 35 — 40 — 45 — ns tCW(2) Chip Select to End-of-Write 25 — 30 — 35 — 40 — ns tAW Address Valid to End-of-Write 25 — 30 — 35 — 40 — ns tAS Address Set-Up Time 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 25 — 30 — 35 — 35 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — (Continued on next page) 7.02 ns 2795 tbl 09 4 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = 55°C to +125°C or 0°C to +70°C) 7M1002SxxG 30 Symbol Parameter 7M1002SxxGB –35 –40 –45 Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle (continued) tDW Data Valid to End-of-Write 22 — 25 — 25 — 25 — ns tDH Data Hold Time 0 — 0 — 0 — 0 — ns tHZ Output to High-Z — 15 — 15 — 17 — 20 ns tOW(1) Output Active from End-of-Write 0 — 0 — 0 — 0 — ns tSWRD SEM Flag Write to Read Time 10 — 10 — 10 — 10 — ns tSPS SEM Flag Contention Window 10 — 10 — 10 — 10 — ns (1) Busy Cycle-Master Mode (3) tBAA BUSY Access Time to Address — 30 — 35 — 35 — 35 ns tBDA BUSY Disable Time to Address — 25 — 30 — 30 — 30 ns tBAC BUSY Access Time to Chip Select — 25 — 30 — 30 — 30 ns tBDC BUSY Disable Time to Chip Deselect — 25 — 25 — 25 — 25 ns ns (5) tWDD Write Pulse to Data Delay — 55 — 60 — 65 — 70 tDDD Write Data Valid to Read Data Delay — 40 — 45 — 50 — 55 ns tAPS(6) Arbitration Priority Set-Up Time 5 — 5 — 5 — 5 — ns tBDD BUSY — NOTE 9 — NOTE 9 — NOTE 9 — NOTE 9 ns 0 — 0 — 0 — 0 — ns Write Hold after BUSY 25 — 25 — 25 — 25 — ns Write Pulse to Data Delay — 55 — 60 — 65 — 70 ns 0 — 0 — 0 — 0 — ns Disable to Valid Time Busy Cycle-Slave Mode tWB(7) tWH (8) (5) tWDD (4) Write to BUSY Input Interrupt Timing tAS Address Set-Up Time tWR Write Recovery Time 0 — 0 — 0 — 0 — ns tINS Interrupt Set Time — 25 — 30 — 32 — 35 ns tINR Interrupt Reset Time — 25 — 30 — 32 — 35 ns 2795 tbl 10 NOTES: 1. This parameter is guaranteed by design but not tested. 2. To access RAM, CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL. 3. When the module is being used in the Master Mode (M/S ≥ VIH). 4. When the module is being used in the Slave Mode (M/S ≤ VIL). 5. Port-to-Port delay through the RAM cells from the writing port to the reading port. 6. To ensure that the earlier of the two ports wins. 7. To ensure that the write cycle is inhibited during contention. 8. To ensure that a write cycle is completed after contention. 9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tWP (actual). 7.02 5 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1, 2, 4) tRC ADDRESS tOH tAA DATAOUT PREVIOUS DATA VALID DATA VALID tOH 2795 drw 05 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (1, 3, 5) tSOP tACE CS tSOP tCHZ (6) tAOE OE tOLZ (6) tOHZ (6) DATA VALID DATAOUT tCLZ (6) tPD (6) ICC CURRENT 50% 50% ISB tPU (6) 2795 drw 06 NOTES: 1. R/W is HIGH for Read Cycles 2. Device is continuously enabled CS ≤ VIL. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition LOW. 4. OE ≤ VIL 5. To access RAM, CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL. 6. This parameter is guaranteed by design but not tested. 7.02 6 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1, 2, 4) tWC ADDRESS tCHZ (9) OE tAW CS tAS (6) tWP (2) tWR (7) R/ W tWHZ (9) t OW (9) (4) DATAOUT (4) tDW DATAIN tDH DATA VALID 2795 drw 07 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 4) tWC ADDRESS tAW CS t AS (6) tWP (2) tWR (7) R/ W tDW DATAIN tDH DATA VALID 2795 drw 08 NOTES: 1. R/W must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW R/W. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must be applied. 5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 7.02 7 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE(1) tAW A0–A2 tWR tAA VALID ADDRESS tOH VALID ADDRESS tWP tSOP tACE SEM tDW DATAIN DATA0 tAS tWP DATAOUT VALID VALID tDH W R/ tSWRD tAOE OE tSOP WRITE CYCLE READ CYCLE 2795 drw 09 NOTE: 1. CS ≥ V IH for the duration of the above timing (both write and read cycle). TIMING WAVEFORM OF SEMAPHORE CONTENTION(1, 3, 4) A0A — A2A (2) SIDE "A" MATCH R/ WA SEMA tSPS A0B — A2B MATCH (2) SIDE "B" R/ WB SEMB 2795 drw 10 NOTES: 1. DOR = DOL ≤ VIL, (L_ CS = R_ CS) ≥ VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 7.02 8 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ WITH BUSY (M/S ≥ VIH)(2) tWC ADDR R MATCH tWP R/W R tDW tDH VALID DATAIN R tAPS (1) tBDA ADDR L MATCH tBDD BUSY L tDDD (3) DATAOUT L VALID tWDD 2795 drw 11 NOTES: 1. To ensure that the earlier of the two ports wins. 2. (L_ CS = R_ CS) ≤ VIL 3. OE ≤ VIL for the reading port. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (M/S ≤ VIH)(1, 2) tWC ADDR R MATCH tWP R/W R tDW tDH VALID DATAIN R MATCH ADDR L tDDD DATAOUT L VALID tWDD 2795 drw 12 NOTES: 1. BUSY input equals HIGH for the writing port. 2. (L_ CS = R_ CS) ≤ VIL 7.02 9 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE WITH BUSY INPUT (M/S ≤ VIL) tWP R/W tWB tWH DATAINR BUSY 2795 drw 13 TIMING WAVEFORM OF BUSY ARBITRATION (CS CONTROLLED TIMING)(1) ADDR "A" AND "B" CS ADDRESS MATCH "A" tAPS CS (2) tBDC "B" tBAC BUSY "B" 2795 drw 14 TIMING WAVEFORM OF BUSY ARBITRATION (CONTROLLED BY ADDRESS MATCH TIMING(1) ADDR "A" ADDRESS "N" tAPS ADDR"B" (2) MATCHING ADDRESS "N" tBAA BUSY tBDA "B" 2795 drw 15 NOTES: 1. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 7.02 10 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF INTERRUPT CYCLE(1) tWC ADDR "A" INTERRUPT SET ADDRESS tAS CE (2) (3) tWR (4) "A" R/W 1"A" tINS INT (3) "B" 2795 drw 16 tRC (2) ADDR "B" INTERRUPT CLEAR ADDRESS tAS CE OE (3) "B" "B" tINR (3) INT "B" 2795 drw 17 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. TRUTH TABLE I: Non-Contention Read/Write Control(1) Inputs Outputs Mode CS R/W OE SEM H X X H High-Z Deselected or Power Down L L X H Data_In Write L H L H Data_OUT Read X X H X High-Z I/O Description Outputs Disabled 2795 tbl 13 NOTE: 1. The conditions for non-contention are L_A (0–13) ≠ R_A (0–13). 2. denotes a LOW to HIGH waveform transition. TRUTH TABLE II: Semaphore Read/Write Control Inputs(2) Outputs CS R/W OE SEM I/O H H L L Data_OUT X L Data_IN X L — H L X Mode Description Read Data in Semaphore Flag Write Data_IN (0, 8, 16, 24) Not Allowed 2795 tbl 14 7.02 11 IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES INTERRUPT/BUSY FLAGS, DEPTH & WIDTH EXPANSION, MASTER/SLAVE CONTROL, SEMAPHORES For more details regarding Interrupt/Busy flags, depth and/or width expansion, master/slave control, or semaphore operations, please consult the IDT7006 data sheet. PACKAGE DIMENSIONS 1.325 1.355 0.025 0.060 1.325 1.355 0.235 MAX. TOP VIEW 0.125 0.200 0.100 BSC 0.016 0.020 0.040 0.060 0.175 MAX. 1.200 BSC 1.200 BSC BOTTOM VIEW Pin A1 2795 drw 18 ORDERING INFORMATION IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range BLANK B Commercial (0°C to +70°C) Military (–55°C to +125°C)Semiconductor Components compliant to MIL-STD-883, Class B G Ceramic PGA (Pin Grid Array) 30 35 40 45 (Commercial Only) (Commercial Only) (Military Only) (Military Only) S Standard Power 7M1002 16K x 32 CMOS Dual-Port Static RAM Module Speed in Nanoseconds 2795 drw 19 7.02 12