AIC AIC1573 5-bit dac, synchronous pwm power regulator with simple pwm power regulator, ldo and linear controller Datasheet

AIC1573
5-bit DAC, Synchronous PWM Power
Regulator with Simple PWM Power Regulator,
LDO And Linear Controller
n FEATURES
n DESCRIPTION
l
Compatible with HIP6020.
The AIC1573 combines two PWM voltage mode
l
Provides 4 Regulated Voltages for Microprocessor
controllers and two linear controllers as well as the
Core, AGP Bus, Memory and GTL Bus Power.
monitoring and protection functions in this chip. One
TTL Compatible 5-bit Digital-to-Analog Core Output
PWM controller regulates the microprocessor core
Voltage Selection. Range from 1.3V to 3.5V.
voltage with a synchronous rectified buck converter.
l
0.1V Steps from 2.1V to 3.5V.
The second PWM controller provides AGP bus 1.5V
0.05V Steps from 1.3V to 2.05V.
or 3.3V power with a standard buck converter. Two
l
±1.0% PWM Output Voltage for VCORE.
linear controllers regulate power for the 1.5V GTL
l
±3% PWM Output Voltage for AGP Bus.
bus and 1.8V power for the chip set core voltage
l
±3.0% Reference Voltage for Chipset and/or Ca-
and/or cache memory circuits.
che Memory and VGTL.
l
Simple Voltage-Mode PWM Control with Built in
microprocessor core voltage from 2.1V to 3.5V in
Internal Compensation Networks.
l
N-Channel MOSFET Driver for PWM buck con-
0.1V increments and from 1.3V to 2.05V in 0.05V
increments. The second PWM controller for AGP
verters.
l
An integrated 5 bit D/A converter that adjusts the
Linear Controller Drives Compatible with both N–
Chanel MOSFET and NPN Bipolar Series Pass
bus power is selectable by means of SELECT pin
status for 1.5V or 3.3V with 3% accuracy. Two linear
controllers drive with external N-channel MOSFETs
Transistor.
to provide 1.5V±3% and fixed output voltage
l
Operates from +3.3V, +5V and +12V Inputs.
l
Fast Transient Response.
l
Full 0% to 100% Duty Ratios.
This chip monitors all the output voltages. Power
l
Adjustable Current Limit without External Sense
Good signal is issued when the core voltage is
Resistor.
within ±10% of the DAC setting and the other levels
Microprocessor Core Voltage Protection against
are above their under-voltage levels. Over-voltage
Upper MOSFET shorted to +5V.
protection for the core output uses the lower N-
l
Power Good Output Voltage Monitor.
channel MOSFET to prevent output voltage above
l
Over-Voltage and Over-Current Fault Monitors.
116% of the DAC setting.
l
200KHz Free-Running Oscillator Programmable up
l
1.8V±3%.
The PWM over-current function monitors the output
to 700KHz.
current by using the voltage drop across the upper
MOSFET’s RDS(ON), eliminating the need for a cur-
n APPLICATIONS
l
rent sensing resistor.
Full Motherboard Power Regulation for Computers.
Analog Integrations Corporation
www.analog.com.tw
DS-1573-01 Sep 10, 01
4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC
TEL: 886-3-5772500
FAX: 886-3-5772510
1
AIC1573
n APPLICATION CIRCUIT
+12V IN
+
4.7µF
C5
VCC
C7
28
1nF
1nF
L3
OCSET2
Q3
V OUT2
3.3V or 1.5V
L2
+
7µH
UGATE2
9
23
27
1
PHASE2
26
OCSET1
+
R3
1000µF*3
25
PHASE1
V OUT1
L1
3µH +
Q2
LGATE1
R1
10K
VSEN2
24
SELECT
+3.3V IN
VAUX
DRIVE3
Q4
V OUT3
VSEN3
11
20
16
22
7
19
6
5
COUT3
4
3
VOUT4
DRIVE4
8
15
13
VESN4
FB1
R2
680K
NC
C6
0.22µF
VSEN1
VID0
VID1
VID2
VID3
VID4
PGOOD
FAULT/RT
14
1.8V
+
PGND
18
+
Q5
COUT1
1000µF*7
10
21
COUT4
GND
2
COUT2
1.5V
1 µH
CIN
10V
680µF*7
Q1
UGATE1
+5V IN
17
GND
12
SS
Css
2
AIC1573
n ORDERING INFORMATION
AIC1573-CX
PACKAGING TYPE
S: SMALL OUTLINE
ORDER NUMBER
AIC157 3CS
(SO28)
PIN CONFIGURATION
UGATE2
1
28 V C C
PHASE2 2
27 UGATE1
VID 4 3
26 PHASE1
VID 3 4
25 LGATE1
VID 2 5
24 PGND
VID 1 6
23 OCSET1
VID0 7
22 VSEN1
PGOOD 8
21 FB1
OCSET2 9
20 NC
VSEN2 10
19 VSEN3
SELECT 11
18 DRIVE3
S S 12
FAULT/RT 13
VSEN4 14
17 GND
16 VAUX
15 DRIVE4
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ...............… … … … … .....… … … … .........… ..… … ..................... +15V
PGOOD, FAULT and GATE Voltage .....… … … .....… … … ..… .... GND -0.3V to VCC +0.3V
Input, Output , or I/O Voltage ......… ...… … … … … … … … … ..… … ............ GND -0.3V to 7V
Recommended Operating Conditions
Supply Voltage; VCC… … ..… … … … ...........… ................... +12V±10%
Ambient Temperature Range … … ..… … ..… … … ................. 0°C~70°C
Junction Temperature Range … … ....… .… … … .................. 0°C~125°C
Thermal Information
Thermal Resistance, θJA
SOIC package … … … … … … … … … … … … … ..… ..… .............. 70°C/W
SOIC package (with 3in2 of copper) … ...… ..… … .......… ......... 50°C/W
Maximum Junction Temperature (Plastic Package)
Maximum Storage Temperature Range
… … … … … … … ..… … ...... 150°C
… … … … … … … … ..… … … .... -65°C ~ 150°C
Maximum Lead Temperature (Soldering 10 sec)
… … … … … … … … … … ..… ... 300°C
3
AIC1573
n ELECTRICAL CHARACTERISTICS
PARAMETER
(Vcc=12V, TA=25°C, Unless otherwise specified)
TEST CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC SUPPLY CURRENT
Supply Current
UGATE1, LGATE1, UGATE2,
DRIVE3 and DRIVE4 open
ICC
3
mA
POWER ON RESET
Rising VCC Threshold
VOCSET=4.5V
VCCTHR
Falling VCC Threshold
VOCSET=4.5V
VCCTHF
10.4
8.2
V
V
Rising VAUX Threshold
VAUXTHR
2.5
V
VAUX Threshold Hysteresis
VAUXHYS
500
mV
Rising VOCSET1 Threshold
VOCSETH
1.26
V
OSCILLATOR
Free Running Frequency
RT=Open
Total Variation
6kΩ<RT to GND<200kΩ
Ramp. Amplitude
RT=open
F
170
200
-15
∆VOSC
230
KHz
+15
%
1.5
VP-P
DAC AND STANDARD BUCK REGULATOR REFERENCE
DAC (VID0~VID4) Input Low
Voltage
VIDL
DAC (VID0~VID4) Input High
Voltage
VIDH
0.8
2.0
V
V
-1.0
+1.0
%
DACOUT Voltage Accuracy
VDAC=1.8V~3.5V
PWM2 Reference Voltage
Select < 0.8V
1.5
V
PWM2 Reference Voltage
Select > 2.0V
3.3
V
3
%
3
%
PWM2 Reference
Tolerance
Voltage
1.5V AND 1.8V LINEAR REGULATORS ( OUT3, OUT4)
Regulation
VSEN3 Regulation Voltage
VREG3
1.5
V
VSEN4 Regulation Voltage
VREG4
1.8
V
VSENUV
75
%
5
%
30
mA
Under-Voltage Level
( VSEN/VREG )
VSEN Rising
Under-Voltage Hysteresis
(V SEN/VREG )
VSEN Falling
Output Drive Current ( All
Linears )
VAUX -V DRIVE > 0.6V
20
4
AIC1573
n ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
(Continued)
SYMBOL
MIN.
TYP.
MAX.
UNIT
SYNCHRONOUS PWM CONTROLLER AMPLIFIER
DC Gain
(G.B.D.)
Gain-Bandwidth Product
(G.B.D.)
Slew Rate
(G.B.D.) note 1.
80
dB
GBWP
13
MHz
SR
6
V/µs
A
PWM CONTROLLER GATE DRIVERS
UGATE1,2 Upper Drive Source
VCC=12V, VUGATE = 6V
IUGH
0.9
UGATE1,2 Upper Drive Sink
VUGATE=1V
RUGL
2.8
Lower Drive Source
VCC=12V, VLGATE =1V
ILGH
1
Lower Drive Sink
VLGATE=1V
RLGL
2.2
3.0
Ω
VSEN1 Over-Voltage
( VSEN1 /DACOUT)
VSEN1 Rising
OVP
116
120
%
FAULT Sourcing Current
VCC-VFAULT/RT =2.0V
IOVP
20
OCSET1,2 Current Source
VOCSET =4.5VDC
3.5
Ω
A
PROTECTION
IOCSET
170
ISS
Soft-Start Current
200
mA
230
µA
µA
25
POWER GOOD
VSEN1 Upper Threshold
VSEN1 Rising
108
111
%
VSEN1 Falling
92
95
%
( VSEN1 /DACOUT )
VSEN1 Under-Voltage
( VSEN1/DACOUT )
VSEN1 Hysteresis
(VSEN1/DACOUT)
Upper and Lower Threshold
PGOOD Voltage Low
IPGOOD=-4mA
2
VPGOOD
0.4
%
0.8
V
Note 1. Without internal compensation network, the gain bandwidth product is 13MHz. Being associated with
internal compensation networks, the Bode Plot is shown in Fig. 3, “Internal Compensation Gain of
PWM Error Amplifier”.
5
AIC1573
n TYPICAL PERFORMANCE CHARACTERISTICS
PGOOD
SS
SS
VDAC=3.5V
VOUT4
VOUT3
VDAC=2V
VOUT2
VDAC=1.3V
VOUT1
Fig. 1 Soft Start Interval with 4 Outputs and P GOOD
Fig. 2
Soft Start Initiates PWM Output
10M
30
90 °C
25
RT Pull Up to 12V
1M
-40 °C
Resistance (Ω)
Gain (dB)
20
22°C
15
RT Pull Down to GND
100k
10
5
10k
0
-5 1k
10k
100k
1k
10k
1M
100k
1M
Switching Frequency (Hz)
Frequency (Hz)
Fig. 4
Fig 3. Internal Compensation Gain of PWM Error Amplifier
R T Resistance vs. Frequency
160
Over Load
140
VCC=12V
120
CUG1=CLG1=C UG2=C
C=4.7nF
Inductor
Applied
Current 5A/div
C=3.3nF
I CC (mA)
100
80
C=1.5nF
60
SS
C=650pF
40
20
Fault
C=0
0
200k
300k
400k
500k
600k
700k
80 0k
900k
1M
Switching Frequency (Hz)
Fig. 5
Supply Current vs. Frequency
Fig. 6
Over Current ON Inductor
6
AIC1573
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
4
FSW =200KHz
3
Switching Frequency Drift (%)
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-40
Fig. 7
20
40
60
80
100
120
Load Transient of Linear Controller
0.4
0.3
OCSET Current = 200 µA
5
0.2
4
VSEN2 Voltage Drift (%)
OCSET Current Drift (%)
0
Temperature (°C)
Fig. 8 Temperature vs. Switching Frequency Drift
6
3
2
1
0.1
0.0
-0.1
0
-0.2
-1
-0.3
-2
-0.4
-3
-4
-0.5
-5
-0.6
-6
VREG2=3.3V
-0.7
-7
-8-40
-20
Fig. 9
0
20
40
60
80
100
120
-0.8
-40
Temperature (°C)
Temperature vs. OCSET Current Drift
-20
Fig. 10
0.4
0.4
0.3
0.3
0. 2
0.2
VSEN4 Voltage Drift (%)
PWM Output Voltage Drift (%)
-20
0.1
0.0
-0. 1
0
20
40
60
80
100
120
Temperature (° C)
Temperature Drift of 9 Different Parts
0.1
0.0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
DACOUT=1.6V
-0.5
-0.5
-0.6
VREG4=1.8V
-0.6
-0.7-40
-20
Fig. 11
0
20
40
60
80
100
Temperature (° C)
Temperature Drift of 13 Different Parts
120
-0.7-40
-20
Fig. 12
0
20
40
60
80
100
Temperature (°C)
Temperature Drift of 9 Different Parts
120
7
AIC1573
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0 to 20A Load Step
V OUT1
0 to 20A Load Step
Fig. 13
VOUT1
Load Transient of PWM Output
Fig. 14
Stringent Load Transient of PWM Output
80
70
60
Mean= -0.006%
DACOUT=1.6V
3 std.=0.56%
Ta=25 °C
Mean = 0.16%
70
Ta = 25°C
3 std.=1%
Number of Parts
60
Number of Parts
50
40
30
20
50
40
30
20
10
10
0
-0.6
0
-0.4
Fig. 15
-0.2
0.0
0.2
Accuracy (%)
FB Voltage Accuracy
0.4
0.6
-1.0
-0.5
0.0
0.5
1.0
Accuracy (%)
Fig. 16
VSEN3 Voltage Accuracy
8
DRV2
VCC
GATE
POR
CONTROL
POWER ON
RESET
VAUX
INHB
COMP2
RAMP2
X 75%
ERROR
AMP2
VSEN2
x 75%
200uA
0.2V
SS
4V
SELECT
1.5V or 3.3V
200uA
PHASE1
OC1
UP
LUV
UGATE1
SS
DRV-L
VCC
FAULT
LATCH
LOGIC
GATE
CONTROL
SOFT START
POR
R
PGND
DRV-H
VCC
COUNTER
(3)
R
LGATE1
RESET
OC1
OVER
CURRENT
LATCH
R
VSEN1
UGATE2
PHASE2
VCC
OCSET1
OCSET2
VAUX
INHB
COMP1
INHB
OV
NC
x 115%
x 110%
X 90%
RAMP1
RAMP2
Comp.
3 P, 2 Z
ERROR
AMP1
DACOUT
VSEN1
FB1
OFF
VCC
CONVERTER
TTL D/A
OSCILLATOR
4.5V
25uA
VCC
PGOOD
GND
SS
VID4
VID3
VID2
VID1
VID0
FAULT /
RT
n BLOCK DIAGRAM
VSEN4
DRIVE4
DRIVE3
VAUX
VSEN3
AIC1573
9
AIC1573
n PIN DESCRIPTIONS
Pin 1:
UGATE2: External high-side N-MOSFET
gate drive pin. Connect UGATE2
Pin 2:
Table 1.
Pin 9:
OCSET2: Current limit sense pin. Connect
to gate of the external high-side
a resistor ROCSET from this pin to
N-MOSFET .
the drain of the external high-side
PHASE2:
N-MOSFET. ROCSET, an internal
200µA current source (IOCSET),
Over-current detection pin. Con-
and the upper N-MOSFET on-
nect the PHASE2 pin to source
resistance (RDS(ON)) set the over-
of
current trip point according to the
the
external
high-side
N-
MOSFET. This pin detects the
following equation:
IOCSET × ROCSET
IPEAK =
RDS(ON)
voltage drop across the high-side
N-MOSFET
RDS(ON)
for
over-
Pin 10: VSEN2: Connect this pin to the output of
current protection.
Pin 7:
VID4:
the standard buck PWM regula-
Pin 6:
VID3:
tor. The voltage at this pin is
Pin 5:
VID2:
regulated to the 1.5V/3.3V prede-
Pin 4:
VID1:
termined by the logic Low/High
Pin 3:
VID0:
5bit DAC voltage select pin. TTL-
level status of the SELECT pin.
compatible inputs used to set the
This pin is also monitored by the
internal voltage reference VDAC.
PGOOD comparator circuit.
When left open, these pins are
Pin 11: SELECT: This pin determines the output
internally pulled up to 5V and
voltage of the AGP bus switching
provide logic ones. The level of
regulator. A low TTL input sets
VDAC sets the converter output
the output voltage to 1.5V, while
voltage as well as the PGOOD
a high input sets the output volt-
and OVP thresholds.
age to 3.3V.
Table 1 specifies the VDAC volt-
Pin 8:
Pin 12: SS:
Soft-start pin. Connect a capaci-
age for the 32 combinations of
tor from this pin to ground. This
DAC inputs.
capacitor, along with an internal
pin.
25µA (typically) current source,
PGOOD is an open drain output.
sets the soft-start interval of the
This pin is pulled low when the
converter. Pulling this pin low will
converter output is ±10% out of
shut down the IC.
PGOOD: Power
good
indicator
the VDAC reference voltage or
Pin 13: FAULT/RT:
Frequency
adjustment
pin.
the other outputs are below their
Connecting a resistor (RT) from
under-voltage
The
this pin to GND, increasing the
PGOOD output is open for VID
frequency. Connecting a resistor
codes that inhibit operation. See
(RT) from this pin to VCC, de-
thresholds.
10
AIC1573
creasing the frequency by the
nected to FB1 in to compensate
following figure (Fig.3).
the voltage control feedback loop
This pin is 1.26V during normal
of the converter.
operation, but it is pulled to VCC
Pin 21: FB1:
The error amplifier inverting input
in the event of an over-voltage or
pin of the synchronous PWM
over-current condition.
converter.

25 .2K 
,
f = f0 1 +
RT 

COMP1 pin are used to compen-
RT pulled to GND
loop.
The
FB1
pin
and
sate the voltage-control feedback
 VCC − 1.26V
f = f0 1 −
5 × RT


,


Pin 22: VSEN1: Synchronous PWM converter’s
output voltage sense pin. Connect this pin to the converter out-
RT pulled to VCC,
where f0 is free run frequency.
Pin14: VSEN4: Connect this pin to the 1.8V
put. The PGOOD and OVP com-
linear regulator’s output. This pin
report output voltage status and
is monitored for under-voltage
for over-voltage protection func-
events.
tion.
parator circuits use this signal to
Pin15: DRIVE4: Connect this pin to the gate of
Pin 23: OCSET1: Current limit sense pin. Connect
the external N-MOS to supply
a resistor ROCSET from this pin to
1.8V power for Memorey re-
the drain of the external high-side
quirement.
N-MOSFET. ROCSET, an internal
The +3.3V input voltage at this
200µA current source (IOCSET ),
pin is monitored for power-on –
and the upper N-MOSFET on-
reset (POR) purpose. Connect to
resistance (RDS(ON)) set the over-
+5V provides boost current for
current trip point according to the
the linear regulator’s output.
levels are measured with respect
following equation:
IOCSET × ROCSET
IPEAK =
RDS(ON)
to this pin.
The voltage at this pin is also
Pin 16: VAUX:
Pin 17: GND:
Signal GND for IC. All voltage
moni tored for power-on reset
Pin 18: DRIVE3: Connect this pin to the Gate of
(POR) purpose.
the external N-MOS for providing
1.5V power to GTL bus.
Pin 24: PGND:
Driver power GND pin. PGND
Pin 19: VSEN3: Connect this pin to the 1.5V
should be connected to a low im-
linear regulator’s output. This pin
pedance ground plane in close to
is monitored for under-voltage
lower N-MOSFET source.
Pin 25: LGATE1: Lower N-MOSFET gate drive pin
events.
of the synchronous PWM con-
Pin 20: COMP1: External compensation pin of the
synchronous
PWM
verter.
converter.
This pin is connected to error
Pin 26: PHASE1:
amplifier output and PWM comparator. A RC network is con-
Over-current detection pin. Con-
11
AIC1573
nect the PHASE1 pin to source
verter’s gate of the external high-
of
side N-MOSFET .
the
external
high-side
N-
MOSFET. This pin detects the
Pin 28: VCC:
The chip power supply pin. It also
voltage drop across the high-side
provides the gate bias charge for
N-MOSFET
all the MOSFETs controlled by
RDS(ON)
for
over-
current protection.
Pin 27: UGATE1:External
high-side
the IC. Recommended supply
N-MOSFET
voltage is 12V. The voltage at this
gate drive pin. Connect UGATE1
pin is monitored for Power-On-
to the synchronous PWM con-
Reset purpose.
n APPLICATIONS INFORMATION
The AIC1573 is designed for microprocessor computer applications with 3.3V and 5V power, and
12V bias input. This IC has two PWM controller
and two linear controllers. The first PWM (PWM1)
controller is designed to regulate the microprocessor core voltage (VOUT1) by driving 2 MOSFETs
(Q1 and Q2) in a synchronous rectified buck converter configuration. The core voltage is regulated to
a level programmed by the 5 bit D/A converter. The
second PWM (PWM2) controller is designed to
regulate the advanced graphics port (AGP) bus
voltage (VOUT2). PWM2 One of the linear controllers is designed to regulate the advanced graphic
port (AGP) bus voltage (VOUT2). PWM2 controller
drives a MOSFET (Q3) in a standard buck converter
and regulates the output voltage to a digitallyprogrammable level of 1.5V or 3.3V.Selection of
either output voltage is achieved by applying the
Soft-Start
The POR function initiates the soft-start sequence.
An internal 25µA current source charges an external capacitor (CSS) on the SS pin to 4.5V. The
PWM error amplifier reference input (Non-inverting
terminal) and output (COMP1 pin) is clamped to a
level proportional to the SS pin voltage. As the SS
pin voltage slew from 1V to 4V, the output clamp
generates PHASE pulses of increasing width that
charge the output capacitors. After the output voltage increases to approximately 70% of the set
value, the reference-input clamp slows the output
voltage rate-of-rise and provides a smooth transition
to the final set voltage. Additionally, all linear regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method
provides a rapid and controlled output voltage rise.
proper logic level at the SELECT pin. The two linear
Fig.1 and Fig.2 show the soft-start sequence for the
controllers supply the 1.5V GTL bus power (VOUT3)
typical application. The internal oscillator’s triangu-
and 1.8V memory power (VOUT4).
lar waveform is compared to the clamped error am-
The Power-On-Reset (POR) function continually
monitors the input supply voltage +12V at VCC pin,
the 5V input voltage at OCSET pin, and the 3.3V
input at VAUX pin. The POR function initiates softstart operation after all three input supply voltage
plifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases.
The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp.
exceeds their POR thresholds.
12
AIC1573
Each linear output initially follows a ramp. When
Fault Protection
each output reaches sufficient voltage the input ref-
All four outputs are monitored and protected
erence clamp slows the rate of output voltage rise.
against extreme overload. A sustained overload on
The PGOOD signal toggles ‘high’ when all output
any output or over-voltage on PWM1 output dis-
voltage levels have exceeded their under-voltage
ables all outputs and drive the FAULT/RT pin to
levels.
VCC.
Over Current
Latch
LUV
S
OC1
OC2
R
0.15V
INHIBIT
Q
S
Counter
R
+
Fault Latch
VCC
S
SS
POR
+
R
Q
4.0V
Fault
OV
Fig. 17 Simplified Schematic of Fault Logic
A simplified schematic is shown in figure 17. An
over-voltage detected on VSEN1 immediately sets
the fault latch. A sequence of three over-current
fault signals also sets the fault latch. The overcurrent latch is set dependent on the status of the
over-current (OC1 and OC2), linear under-voltage
(LUV) and the soft-start signal. An under-voltage
event on either linear output (VSEN3, VSEN4) is
ignored until the soft-start interval. Cycling the bias
Over-Voltage Protection
During operation, a short on the upper PWM1
MOSFET (Q1) causes VOUT1 to increase. When
the output exceed the over-voltage threshold of
116% of DACOUT, the FAULT pin is set to fault
latch and turns Q2 on as required in order to regulate VOUT1 to 116% of DACOUT. The fault latch
raises the FAULT/RT pin close to VCC potential.
input voltage (+12V off then on) resets the counter
A separate over-voltage circuit provides protection
and the fault latch.
during the initial application of power. For voltage on
VCC pin below the power-on reset (and above ~4V),
Gate Drive Overlap Protection
The Overlap Protection circuit ensures that the Bottom MOSFET does not turn on until the Upper
Should VSEN1 exceed 1.0V, the lower MOSFET
(Q2) is driven on as needed to regulate VOUT1 to
1.0V.
MOSFET source has reached a voltage low enough
to ensure that shoot-through will not occur.
13
AIC1573
Over-Current Protection
(DACOUT) through a TTL compatible 5 bit digital to
All outputs are protected against excessive over-
analog converter. The VID pins can be left open for
current.
upper
a logic 1 input, because they are internally pulled
MOSFET’s on-resistance, RDS(ON) to monitor the
Both
PWM
controller
uses
up to 5V by a 70kΩ resistor. Changing the VID in-
current for protection against shorted outputs. All
puts during operation is not recommended. ‘11111’
linear controllers monitor VSEN for under-voltage to
VID pin combinations disable the IC and open the
protect against excessive current.
PGOOD pin.
When the voltage across Q1 (ID•RDS(ON)) exceeds
the level (200µA • ROCSET ), this signal inhibit all
outputs. Discharge soft-start capacitor (Css) with
28µA current sink, and increments the counter.
Css recharges and initiates a soft-start cycle again
until the counter increments to 3. This sets the fault
OUT2 Voltage Selection
The AGP regulator output voltage is internally set to
one of two discrete levels, based on the SELECT
pin status. Left SELECT pin open, internal pulled
high, the output voltage is 3.3V. Grounding SELECT pin will get the 1.5V output voltage.
latch to disable all outputs. Fig. 6 illustrates the
over-current protection until an over load on OUT1.
The status of the SELECT pin can not be changed
during operation of the IC without immediatelly
Should excessive current cause VSEN to fall below
causing a fault condition.
the linear under-voltage threshold, the LUV signal
sets the over-current latch if Css is fully charged.
Cycling the bias input power (off then on reset the
Shutdown
counter and the fault latch.
Neither PWM output switches until the soft-start
The over-current function for PWM controller will trip
voltage exceeds the oscillator’s vally voltage. Addi-
at a peak inductor current (IPEAK) determined by:
tional, the reference on each linear’s amplifier is
IPEAK
IOCSET × R OCSET
=
R DS(ON)
clamped to the soft-start voltage. Holding the SS
pin low turns of all four regulators.
The OC trip point varies with MOSFET’s tempera-
The VID codes resulting in an INHIBIT as shown in
ture. To avoid over-current tripping in the normal op-
Table 1 also shut down the IC.
erating load range, determine the ROCSET resistor
from the equation above with:
1. The maximum RDS(ON) at the highest junction.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK > IOUT(MAX) + (inductor ripple
current) /2.
Oscillator Synchronization
The AIC1573 avoids the problem of cross talk between the converters by way of phase control
method. Therefore, for both output voltage settings
less than 2.4V or both greater than 2.4V, PWM1
OUT1 Voltage Program
operates out of phase with PWM2. For one PWM
The output voltage of the PWM1 converter is pro-
output voltage setting below 2.4V and the other
grammed to discrete levels between 1.3V to 3.5V.
PWM output voltage setting of 2.4V and above,
The VID pins program an internal voltage reference
PWM1 operates in phase with PWM2.
14
AIC1573
@VOUT1=1.7V
UGATE1
UGATE2
@V OUT2=3.3V
Fig. 18
UGATE1
@VOUT1=1.7V
@VOUT2=1.5V
PWM1 operates in phase with PWM2
UGATE2
Fig. 19 PWM1 operates out of phase with PWM2
Table 1 VOUT1 Voltage Program ( 0=connected to GND, 1=open or connected to 5V )
For all package version
PIN NAME
DACOUT
PIN NAME
DACOUT
VID4
VID3
VID2
VID1
VID0
VOLTAGE
VID4
VID3
VID2
VID1
VID0
VOLTAGE
0
1
1
1
1
1.30V
1
1
1
1
1
INHIBIT
0
1
1
1
0
1.35V
1
1
1
1
0
2.1 V
0
1
1
0
1
1.40V
1
1
1
0
1
2.2 V
0
1
1
0
0
1.45V
1
1
1
0
0
2.3 V
0
1
0
1
1
1.50V
1
1
0
1
1
2.4 V
0
1
0
1
0
1.55V
1
1
0
1
0
2.5 V
0
1
0
0
1
1.60V
1
1
0
0
1
2.6 V
0
1
0
0
0
1.65V
1
1
0
0
0
2.7 V
0
0
1
1
1
1.70V
1
0
1
1
1
2.8 V
0
0
1
1
0
1.75V
1
0
1
1
0
2.9 V
0
0
1
0
1
1.80 V
1
0
1
0
1
3.0 V
0
0
1
0
0
1.85 V
1
0
1
0
0
3.1 V
0
0
0
1
1
1.90 V
1
0
0
1
1
3.2 V
0
0
0
1
0
1.95 V
1
0
0
1
0
3.3 V
0
0
0
0
1
2.00 V
1
0
0
0
1
3.4 V
0
0
0
0
0
2.05 V
1
0
0
0
0
3.5 V
15
AIC1573
Layout Considerations
A multi-layer-printed circuit board is recommended.
Any inductance in the switched current path gener-
Figure 11 shows the connections of the critical
ates a large voltage spike during the switching in-
components in the converter. The CIN and COUT
terval. The voltage spikes can degrade efficiency,
could each represent numerous physical capacitors.
radiate noise into the circuit, and lead to device
Dedicate one solid layer for a ground plane and
over-voltage stress. Careful component selection
make all critical component ground connections
and tight layout of critical components, and short,
with vias to this layer.
wide metal trace minimize the voltage spike.
A ground plane should be used. Locate the input
PWM Output Capacitors
capacitors (CIN) close to the power switches.
The load transient for the microprocessor core re-
Minimize the loop formed by CIN, the upper
quires high quality capacitors to supply the high
MOSFET (Q1) and the lower MOSFET (Q2) as
slew rate (di/dt) current demand.
possible. Connections should be as wide as short
The ESR (equivalent series resistance) and ESL
as possible to minimize loop inductance.
(equivalent series inductance) parameters rather
The connection between Q1, Q2 and output induc-
than actual capacitance determine the buck ca-
tor should be as wide as short as practical. Since
pacitor values. For a given transient load magnitude,
this connection has fast voltage transitions will ea-
the output voltage transient change due to the out-
sily induce EMI.
put capacitor can be note by the following equation:
The output capacitor (COUT ) should be located as
∆VOUT = ESR × ∆IOUT + ESL ×
close the load as possible. Because minimize the
∆IOUT
∆T ,
where
transient load magnitude for high slew rate requires
∆IOUT is transient load current step.
low inductance and resistance in circuit board
After the initial transient, the ESL dependent term
The AIC1573 is best placed over a quiet ground
plane area. The GND pin should be connected to
the groundside of the output capacitors. Under no
circumstances should GND be returned to a ground
inside the CIN, Q1, Q2 loop. The GND and PGND
pins should be shorted right at the IC. This help to
drops off. Because the strong relationship between
output capacitor ESR and output load transient, the
output capacitor is usually chosen for ESR, not for
capacitance value. A capacitor with suitable ESR
will usually have a larger capacitance value than is
needed for energy storage.
minimize internal ground disturbances in the IC and
A common way to lower ESR and raise ripple cur-
prevents differences in ground potential from dis-
rent capability is to parallel several capacitors. In
rupting internal circuit operation.
most case, multiple electrolytic capacitors of small
The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 1A
case size are better than a single large case capacitor.
current. The traces for OUT2 need only be sized
for 0.5A. Locate COUT2 close to the AIC1573.
The Vcc pin should be decoupled directly to GND
by a 2.2µF ceramic capacitor, trace lengths
should be as short as possible.
16
AIC1573
Output Inductor Selection
of input bulk capacitors to control the voltage over-
Inductor value and type should be chosen based on
shoot across the upper MOSFET. The ceramic ca-
output slew rate requirement, output ripple require-
pacitance for the high frequency decoupling should
ment and expected peak current. Inductor value is
be placed very close to the upper MOSFET to sup-
primarily controlled by the required current respon-
press the voltage induced in the parasitic circuit
se time. The AIC1573 will provide either 0% or
impedance. The buck capacitors to supply the
100% duty cycle in response to a load transient.
RMS current is approximate equal to:
The response time to a transient is different for the
application of load and remove of load.
L × ∆IOUT
VIN − VOUT ,
L × ∆IOUT
tFALL =
VOUT .
IRMS = (1− D) × D × I2 OUT +
tRISE =
D=
Where ∆IOUT is transient
load current step.
, where
1  VIN × D
×

12  f × L 
2
VOUT
VIN
The capacitor voltage rating should be at least 1.25
times greater than the maximum input voltage.
In a typical 5V input, 2V output application, a 3µH
PWM MOSFET Selection
inductor has a 1A/µS rise time, resulting in a 5µS
In high current PWM application, the MOSFET
delay in responding to a 5A load current step. To
power dissipation, package type and heatsink are
optimize performance, different combinations of in-
the dominant design factors. The conduction loss is
put and output voltage and expected loads may re-
the only component of power dissipation for the
quire different inductor value. A smaller value of in-
lower MOSFET, since it turns on into near zero
ductor will improve the transient response at the
voltage. The upper MOSFET has conduction loss
expense of increase output ripple voltage and n
i-
and switching loss. The gate charge losses are
ductor core saturation rating.
proportional to the switching frequency and are dis-
Peak current in the inductor will be equal to the
sipated by the AIC1573. However, the gate charge
maximum output load current plus half of inductor
increases the switching interval, tSW, which increase
ripple current. The ripple current is approximately
the upper MOSFET switching losses. Ensure that
equal to:
both MOSFETs are within their maximum junction
(V IN − VOUT) × VOUT
I RIPPLE =
f × L × VIN
;
temperature at high ambient temperature by calculating the temperature rise according to package
thermal resistance specifications.
f = AIC1573 oscillator frequency.
The inductor must be able to withstand peak cur-
PUPPER = IOUT 2 × RDS(ON) × D +
rent without saturation, and the copper resistance
IOUT × VIN × tSW × f
2
in the winding should be kept as low as possible to
PLOWER = IOUT 2 × RDS(ON) × (1 − D)
minimize resistive power loss
The equations above do not model power loss due
Input Capacitor Selection
Most of the input supply current is supplied by the
to the reverse recovery of the lower MOSFET’s body diode.
input bypass capacitor, the resulting RMS current
The RDS(ON) is different for the two previous equa-
flow in the input capacitor will heat it up. Use a mix
tions even if the type devices is used for both. This
17
AIC1573
is because the gate drive applied to the upper
Linear Controller MOSFET Selection
MOSFET is different than the lower MOSFET.
The power dissipated in a linear regulator is:
Logic level MOSFETs should be selected based on
PLINEAR = IOUT × (V IN − VOUT )
on-resistance considerations, RDS(ON)
should be
Select a package and heatsink that maintains junc-
chosen base on input and output voltage, allowable
tion temperature below the maximum rating while
power dissipation and maximum required output
operation at the highest expected ambient tempera-
current. Power dissipation should be calculated
ture.
based primarily on required efficiency or allowable
thermal dissipation.
Linear Output Capacitor
The output capacitors for the linear regulator and
Rectifier Schottky diode is a clamp that prevent the
linear controller provide dynamic load current. The
loss parasitic MOSFET body diode from conducting
linear controller uses dominant pole compensation
during the dead time between the turn off of the
integrated in the error amplifier and is insensitive to
lower MOSFET and the turn on of the upper
output capacitor selection. COUT3 and COUT4
MOSFET. The diode’s rated reverse breakdown
should be selected for transient load regulation. The
voltage must be greater than twice the maximum
output capacitor for the linear regulator provides
input voltage.
loop stability.
PWM Feedback Analysis
VIN
∆VOSC
Q1
VDAC
VEA
VOUT
LO
+
CO
PWM COMP.
ERROR AMP.
Q2
RESR
Compensation
Networks
Modulation
Gain
Fig 20.
Control Loop
The compensation network consists of the error
Closed Loop Gain(dB) = Modulation Gain(dB) +
amplifier and built in compensation networks. The
Compensation Gain (dB)
goal of the compensation network is to provide for
fast response and adequate phase margin. Phase
Modulation Gain(dB)
Margin is the difference between the closed loop
 VIN
≈ 20 log
 ∆VOSC
phase at 0dB and 180 degree.
2
 

F  
 + 10 log 1 + 


  F
 

  ESR  
18
AIC1573
FESR =
1
=
Q




2
2


F
 +



FLC × Q 


FZ1



F Z2
FP1
40
Compensation Gain
20
F P2
FOdB
20log(VIN/δVOSC)
0
2π × RESR × CO
LO
60
;
1
CO
2 
Gain (dB)


 F
− 10 log  1 − 
   FLC

where
1
FLC =
2π LO CO
LO
× R ESR +
Modulation
Gain
FLC
F
;
CO
×
-20
100
1
1k
Closed Loop
Gain
F ESR
10k
100k
1M
10M
Frequency (KHz)
R LOAD
Fig. 21
Bode Plot of Converter Gain
The break frequency of Internal Compensation Gain
Bode Plot of Converter Gain
are given by
Sampling theory shows that F0dB must be less that
FZ 1 = 2.6KHz ;
half the switching frequency for the loop stables.
FZ 2 = 24 KHz ;
But it must be considerably less than that, or there
FP1 = 30 KHz ;
will be large amplitude switching frequency ripple at
FP 2 = 400 KHz
the output. Thus, the usual practices is to fix F0dB
at 1/4 to 1/5 the switching frequency.
n PHYSICAL DIMENSIONS
28 LEAD PLASTIC SO (unit: mm)
D
SYMBOL
MIN
MAX
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
17.70
18.10
E
7.40
7.60
E
H
e
B
e
A
A1
l
C
L
1.27 (TYP)
H
10.00
10.65
L
0.40
1.27
19
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