The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
1. Go to www.cypress.com/pcn.
2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK
MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK
MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK
MB91580M/S Series, FR81S
32-bit Microcontroller Datasheet
This series is a Cypress 32-bit microcontroller for automobile motor control. They use the FR81S CPU that is
compatible with the FR family.
Features
FR81S CPU Core
Peripheral functions
32-bit RISC, load/store architecture, pipeline 5-stage
structure
Clock generation (SSCG function is available)
Main oscillation (4 MHz to 20 MHz)
PLL multiplication rate:1 to 32 times
Maximum operating frequency: 128MHz (Source
oscillation= 4.0MHz, 32 multiplied ( PLL clock
multiplication system) )
General-purpose register: 32 bits × 16 sets
16-bit fixed length instructions (basic instructions), 1
instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instructions
Bit manipulation instructions
Barrel shift instructions
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
CR oscillation
Oscillation frequency: 100kHz, with frequency
accuracy ± 50% (pre-trimming)
Trimming is enabled
To be used as a count clock of hardware
watchdog
Oscillation stop feature during standby is not
available
MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F
584AMK/F585AMK
MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F5
84ASK/F585ASK
Bit search instructions
Logical 1 detection, 0 detection, and change-point
detection
Branch instructions with delay slot
Overhead decrement during branch process
Register interlock function
Easy assembler writing
Built-in multiplier and instruction level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous
execution of program and data access.
Instruction compatibility with the FR family
Built-in memory protection function (MPU)
Eight protection areas can be specified
commonly for instructions and data.
Control access privilege in both privilege mode
and user mode
Built-in FPU (floating-point operation)
IEEE754 compliant
Floating-point register: 32 bits × 16 sets
Cypress Semiconductor Corporation
Document Number: 002-04665 Rev *A
•
198 Champion Court
Oscillation stop feature during standby is
available
MB91F583AMG/F584AMG/F585AMG/F583AMH
/F584AMH/F585AMH
MB91F583ASG/F584ASG/F585ASG/F583ASH/
F584ASH/F585ASH
Built-in program flash memory capacity
MB91F583: 256+64 Kbytes
MB91F584: 384+64 Kbytes
MB91F585: 512+64 Kbytes
Built-in data flash (WorkFlash) 64 Kbytes
Built-in RAM capacity
Main RAM
MB91F583: 32 Kbytes
MB91F584: 48 Kbytes
MB91F585: 48 Kbytes
Backup RAM 8 Kbytes
General-purpose port:
MB91F583AM/F584AM/F585AM
76 ports
2
Including eight I C pseudo open drain
corresponding ports
MB91F583AS/F584AS/F585AS
44ports
2
Including two I C pseudo open drain
corresponding ports
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 29, 2016
MB91580M/S Series
DMA controller
Up to 8 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and
software)
External interrupt input
MB91F583AM/F584AM/F585AM: 8 channels
MB91F583AS/F584AS/F585AS: 7 channels
Level ("H" / "L") or edge detection (rising or falling)
enabled
Multi-function serial communication (built-in
transmission/reception FIFO memory)
MB91F583AM/F584AM/F585AM: 4 channels
MB91F583AS/F584AS/F585AS: 2 channels
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
UART (Asynchronous serial interface)
Full-duplex double buffering system, 64-byte
transmission FIFO memory, 64-byte reception
FIFO memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer
clock
Parity, frame, and overrun error detection
functions provided
DMA transfer supported
CSIO (Synchronous serial interface)
Full-duplex double buffering system, 64-byte
transmission FIFO memory, 64-byte reception
FIFO memory
SPI supported; master and slave systems
supported; 5 to 16, 20, 24, 32-bit data length
can be set.
Built-in dedicated baud rate generator (Master
operation)
An external clock can be entered. (Slave
operation)
Overrun error detection function is provided.
Built-in chip selection function
DMA transfer supported
LIN interface (v2.1)
Full-duplex double buffering system, 64-byte
transmission FIFO memory, 64-byte reception
FIFO memory
LIN protocol revision2.1 supported.
Master and slave systems supported
Framing error and overrun error detection
LIN sync break generation and detection; LIN
sync delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the
reload counter.
DMA transfer supported
2
IC
MB91F583AM/F584AM/F585AM: Supported
for 3 channels: ch.0,ch.2,and ch.3
Document Number: 002-04665 Rev *A
•
•
•
MB91F583AS/F584AS/F585AS: Supported for
1 channel: ch.0
Full-duplex double buffering system, 64-byte
transmission FIFO memory, 64-byte reception
FIFO memory
Standard mode (Max. 100 kbps) / high-speed
mode (Max. 400 kbps) supported
DMA transfer supported (for transmission only)
CAN controller (CAN)
MB91F583AM/F584AM/F585AM:
MB91F583AS/F584AS/F585AS:
2 channels
1 channel
Transfer speed: Up to 1Mbps
64-transmission/reception message buffering
FlexRay controller
MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584A
MJ/F585AMJ/
F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F58
5ASJ: 1 unit (ch.A/ch.B)
FlexRay Specifications Version 2.1 supported
Up to 128 message buffers
8K bytes of message RAM
Variable length of message buffers
Each message buffer can be allocated as a part
of reception buffer, transmission buffer or
reception FIFO memory
Host access to the message buffer via input and
output buffers
Filtering for slot counter, cycle counter and
channels
Maskable interrupts are supported
PPG: 16 bits × 6 channels
Reload timer: 16 bits × 4 channels
A/D converter (successive approximation type)
12-bit resolution
MB91F583AM/F584AM/F585AM: 3 units (23
channels)
MB91F583AS/F584AS/F585AS:
3
units (17 channels)
Conversion time: 1 µs
Free-run timer
16 bits × 6 channels (1 channel can be selected for
input capture, and 1 channel for output compare.)
Input capture: 16 bits × 4 channels (linked to the
free-run timer)
Output compare: 16 bits × 7 channels (linked to the
free-run timer)
Waveform generator: 2 units (7 channels)
10-bit D/A converter: 1 channel
Calibration: The hardware watchdog for CR
oscillation drive
The CR oscillation frequency can be trimmed.
Page 2 of 175
MB91580M/S Series
Clock Supervisor
Anomaly supervisory feature (by damaged
quartz, etc.) of external main oscillation (4MHz)
When anomaly is detected, clock is switched to
CR.
Up/ down counter: 2 channels
8/16-bit Up/ down counter
Base timer: 2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer
functions can be selected and used.
As for the functions of PWC and reload timer, 2
channels of cascade mode can be used as 32-bit
timer.
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog
NMI
Interrupt controller
I/O relocation (MB91F583AM/F584AM/F585AM)
Change of pin position of peripheral functions
Low-power consumption mode
Sleep/Stop/Watch
Stop (Power shutdown)/Watch (Power shutdown)
Power-on reset
Low-voltage detection reset (external low-voltage
detection)
Low-voltage detection reset (internal low-voltage
detection)
Package
MB91F583AM/F584AM/F585AM:
MB91F583AS/F584AS/F585AS:
LQFP-100
LQFP-64
CMOS 90 nm technology
Power supplies
Single 5V power supply
The voltage step-down circuit brings the 5.0V
down to generate 1.2V internally
I/O 5.0V
Interrupt request batch read
Multiple interrupts from peripherals can be read by a
series of registers.
Document Number: 002-04665 Rev *A
Page 3 of 175
MB91580M/S Series
Contents
1.
Product Lineup ............................................................................................................................................. 5
2.
Pin Assignment........................................................................................................................................... 11
3.
Pin Description ........................................................................................................................................... 13
4.
I/O Circuit Type ........................................................................................................................................... 25
5.
Handling Precautions ................................................................................................................................. 31
6.
Handling Devices ........................................................................................................................................ 34
7.
Block Diagram............................................................................................................................................. 37
8.
Memory Map ................................................................................................................................................ 39
9.
I/O Map......................................................................................................................................................... 40
10.
Interrupt Vector Table ........................................................................................................................... 117
11.
Electrical Characteristics ..................................................................................................................... 124
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
11.4
11.4.1
11.4.2
11.4.3
11.5
11.6
11.6.1
11.6.2
12.
Absolute Maximum Ratings .................................................................................................................... 124
DC Characteristics .................................................................................................................................. 127
AC Characteristics .................................................................................................................................. 134
Main Clock Timing .............................................................................................................................. 134
Reset input.......................................................................................................................................... 137
Power-on Conditions .......................................................................................................................... 138
Multi-function Serial ............................................................................................................................ 139
Timer Input Timing .............................................................................................................................. 157
Trigger Input Timing ............................................................................................................................ 157
NMI Input Timing................................................................................................................................. 158
Low-voltage Detection (External Low-voltage Detection).................................................................... 159
Low-voltage Detection (Internal Low-voltage Detection) ..................................................................... 159
A/D Converter ......................................................................................................................................... 160
Electrical Characteristics .................................................................................................................... 160
Definition of Terms .............................................................................................................................. 161
Notes on Using A/D Converter ............................................................................................................ 161
D/A Converter ......................................................................................................................................... 163
Flash memory ......................................................................................................................................... 163
Electrical Characteristics .................................................................................................................... 163
Notes .................................................................................................................................................. 164
Example Characteristics ...................................................................................................................... 165
13.
Ordering Information ............................................................................................................................ 169
14.
Package Dimensions ............................................................................................................................ 170
15.
Major Changes ...................................................................................................................................... 172
Document Number: 002-04665 Rev *A
Page 4 of 175
MB91580M/S Series
1.
Product Lineup
MB91580AM Series Product Lineup Comparison
Memory size
Items
MB91F583AMG
MB91F584AMG
MB91F585AMG
MB91F583AMH
MB91F584AMH
MB91F585AMH
MB91F583AMJ
MB91F584AMJ
MB91F584AMK
MB91F585AMK
MB91F583AMK
Flash memory capacity (program)
256+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
32 Kbytes
RAM capacity (backup)
8 Kbytes
MB91F585AMJ
384+64 Kbytes
512+64 Kbytes
48 Kbytes
48 Kbytes
Function
MB91F583AMG
Items
System clock
CR oscillation
Oscillation stop feature
during standby
MB91F583AMH
MB91F583AMJ
MB91F583AMK
MB91F584AMG
MB91F584AMH
MB91F584AMJ
MB91F584AMK
MB91F585AMG
MB91F585AMH
MB91F585AMJ
MB91F585AMK
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
Provided
Provided
Provided
External bus interface
Not provided
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
4 channels
Output compare
7 channels
Waveform generator
2 units (7 channels)
16-bit reload timer
4 channels
PPG
6 channels
External interrupt
8 channels
A/D converter
3 units (23 channels)
R/D converter
Not provided
D/A converter
Provided
Up/ down counter
2 channels
Multi-function serial interface
4 channels
CAN
64msb × 2 channels (ch.0/ch.1)
FlexRay
128msb ×
1 unit
(ch.A / ch.B)
Software watchdog
Provided
Hardware watchdog
Provided
Document Number: 002-04665 Rev *A
Not provided
Not provided
Not provided
128msb ×
1 unit
(ch.A / ch.B)
Not provided
Page 5 of 175
MB91580M/S Series
Items
MB91F583AMG
MB91F583AMH
MB91F583AMJ
MB91F583AMK
MB91F584AMG
MB91F584AMH
MB91F584AMJ
MB91F584AMK
MB91F585AMG
MB91F585AMH
MB91F585AMJ
MB91F585AMK
CRC generation
2 channels
Low-voltage detection reset
(internal low-voltage detection)
Provided
Low-voltage detection reset
(external low-voltage
detection)
Provided
Device package
LQFP-100
Debug interface
Built-in OCD (On Chip Debug Unit)
Document Number: 002-04665 Rev *A
Page 6 of 175
MB91580M/S Series
MB91580AS Series Product Lineup Comparison
Memory size
Items
MB91F583ASG
MB91F584ASG
MB91F585ASG
MB91F583ASH
MB91F584ASH
MB91F585ASH
MB91F583ASJ
MB91F584ASJ
MB91F585ASJ
MB91F583ASK
Flash memory capacity (program)
256+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
32 Kbytes
RAM capacity (backup)
8 Kbytes
MB91F584ASK
MB91F585ASK
384+64 Kbytes
512+64 Kbytes
48 Kbytes
48 Kbytes
Function
Items
MB91F583ASG
MB91F583ASH
MB91F583ASJ
MB91F583ASK
MB91F584ASG
MB91F584ASH
MB91F584ASJ
MB91F584ASK
MB91F585ASG
MB91F585ASH
MB91F585ASJ
MB91F585ASK
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
System clock
CR oscillation
Oscillation stop feature
during standby
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
Provided
Provided
Provided
External bus interface
Not provided
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
4 channels
Output compare
7 channels
Waveform generator
2 units (7 channels)
16-bit reload timer
4 channels
PPG
6 channels
External interrupt
7 channels
A/D converter
3 units (17 channels)
R/D converter
Not provided
D/A converter
Provided
Up/ down counter
2 channels
Multi-function serial interface
2 channels
CAN
64msb × 1 channel (ch.0)
FlexRay
128msb ×
1unit
(ch.A / ch.B)
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
2 channels
Document Number: 002-04665 Rev *A
Not provided
Not provided
Not provided
128msb ×
1unit
(ch.A / ch.B)
Not provided
Page 7 of 175
MB91580M/S Series
Items
MB91F583ASG
MB91F583ASH
MB91F583ASJ
MB91F583ASK
MB91F584ASG
MB91F584ASH
MB91F584ASJ
MB91F584ASK
MB91F585ASG
MB91F585ASH
MB91F585ASJ
MB91F585ASK
Low-voltage detection reset
(internal low-voltage detection)
Provided
Low-voltage detection reset
(external low-voltage
detection)
Provided
Device package
LQFP-64
Debug interface
Built-in OCD (On Chip Debug Unit)
Document Number: 002-04665 Rev *A
Page 8 of 175
MB91580M/S Series
MB91580L Series Product Lineup Comparison
Memory size
Items
MB91F585LA
MB91F586LA
MB91F587LA
MB91F585LB
MB91F586LB
MB91F587LB
MB91F585LC
MB91F586LC
MB91F587LC
MB91F585LD
Flash memory capacity (program)
512+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
48 Kbytes
RAM capacity (backup)
8 Kbytes
MB91F586LD
MB91F587LD
768+64 Kbytes
1024+64 Kbytes
64 Kbytes
96 Kbytes
Function
Items
MB91F585LA
MB91F585LB
MB91F585LC
MB91F585LD
MB91F586LA
MB91F586LB
MB91F586LC
MB91F586LD
MB91F587LA
MB91F587LB
MB91F587LC
MB91F587LD
On-chip PLL clock multiplication system
System clock
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
CR oscillation
Oscillation stop feature
during standby
Provided
Provided
External bus interface
Not provided
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
8 channels
Output compare
12 channels
Waveform generator
2 units (12 channels)
16-bit reload timer
4 channels
PPG
24 channels
External interrupt
8 channels
Provided
Address: 22 bits
Data: 16 bits
Not provided
Not provided
Not provided
Address: 22 bits
Data: 16 bits
A/D converter
3 units (24 channels)
R/D converter
Provided
Not provided
Provided
Not provided
D/A converter
Not provided
Provided
Not provided
Provided
Up/ down counter
2 channels
Multi-function serial interface
5 channels
CAN
64 msb × 3 channels (ch.0/ch.1/ch.2)
FlexRay
128 msb × 1 unit (ch.A / ch.B)
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
1 channel
Document Number: 002-04665 Rev *A
Page 9 of 175
MB91580M/S Series
Items
MB91F585LA
MB91F585LB
MB91F585LC
MB91F585LD
MB91F586LA
MB91F586LB
MB91F586LC
MB91F586LD
MB91F587LA
MB91F587LB
MB91F587LC
MB91F587LD
Low-voltage detection reset
(internal low-voltage detection)
Provided
Low-voltage detection reset
(external low-voltage detection)
Provided
Device package
LQFP-144
Debug interface
Built-in OCD (On Chip Debug Unit)
Note: For details on the MB91580L series, see the "MB91580L Series HARDWARE MANUAL".
Document Number: 002-04665 Rev *A
Page 10 of 175
MB91580M/S Series
2.
Pin Assignment
LQFP-100 Pin Assignment MB91F583AM/F584AM/F585AM
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC5
P070/TIN0/INT3
P047/TOT0/INT2/ADTG2
P046/ADTG0/MM
P087
P086
P085/SCS3
C
VSS
P084/SCK3
P083/SOT3
P082/SIN3
RSTX
P045/RX0/INT1
P044/TX0
VSS
X1
X0
MD1
MD0
P081/SCK0_1
P080/SOT0_1
P043/SIN0_1/ADTG1/MONCLK
DEBUGIF
VCC5
(TOP VIEW)
VSS
P000
P071/TIN1/AIN0/INT4
P001
P072/TOT1/BIN0/RTO6
P050/RTO5/ZIN0
P002
P051/RTO4/AIN1/FRCK5
P003
P052/RTO3/BIN1/FRCK4
P004
P053/RTO2/ZIN1/FRCK3
P005
P054/RTO1/FRCK2
P006
P055/RTO0/FRCK1
P007
P056/DTTI0/FRCK0
P010/AN0/IN0
P011/AN1/IN1
P012/AN2/IN2
P013/AN3/IN3
P014/AN4/TRG1
P015/AN5
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP-100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
P042/SIN0_0
P066
P041/SCK0_0
P040/SOT0_0
P065/SCS2
P064/SCK2
P037/AN8
NMIX
P063/SOT2
P062/SIN2
P036/AN9/TIOA0/TIN2
P035/AN10/TIOB0/TOT2
P034/AN11/TIOA1/TIN3
P033/AN12/TIOB1/TOT3
P061/TX1
P060/RX1/INT7
AVCC1
AVRH1
AVSS1/AVRL1
P032/AN13
P031/AN14
P030/DAOUT
P097/AN23
VSS
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC5
P102
P101
P100
P096/AN22
P095/AN21
P094/AN20/PPG5
P093/AN19/PPG4
P027/PPG3/TXDA
P026/PPG2/RXDA
P025/PPG1/TXENA
P024/PPG0/STOPWT
P023/SCS1/TXDB
P022/SOT1/RXDB
P021/SIN1/TXENB/INT0
P020/SCK1/TRG0
P092/AN18
P091/AN17
P090/AN16
AVSS0/AVRL0
AVRH0
P017/AN7/INT5
AVCC0
P016/AN6/INT6
VSS
(FPT-100P-M20)
Document Number: 002-04665 Rev *A
Page 11 of 175
MB91580M/S Series
LQFP-64 Pin Assignment MB91F583AS/F584AS/F585AS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC5
P070/TIN0/INT3
P047/TOT0/INT2/ADTG2
P046/ADTG0/MM
C
VSS
RSTX
P045/RX0/INT1
P044/TX0
VSS
X1
X0
MD1
MD0
P043/ADTG1/MONCLK
DEBUGIF
(TOP VIEW)
VSS
P071/TIN1/AIN0/INT4
P072/TOT1/BIN0/RTO6
P050/RTO5/ZIN0
P051/RTO4/AIN1/FRCK5
P052/RTO3/BIN1/FRCK4
P053/RTO2/ZIN1/FRCK3
P054/RTO1/FRCK2
P055/RTO0/FRCK1
P056/DTTI0/FRCK0
P010/AN0/IN0
P011/AN1/IN1
P012/AN2/IN2
P013/AN3/IN3
P014/AN4/TRG1
P015/AN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP-64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P042/SIN0_0
P041/SCK0_0
P040/SOT0_0
P037/AN8
NMIX
P036/AN9/TIOA0/TIN2
P035/AN10/TIOB0/TOT2
P034/AN11/TIOA1/TIN3
P033/AN12/TIOB1/TOT3
AVCC1
AVRH1
AVSS1/AVRL1
P032/AN13
P031/AN14
P030/DAOUT
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P016/AN6/INT6
VCC5
P094/AN20/PPG5
P093/AN19/PPG4
P027/PPG3/TXDA
P026/PPG2/RXDA
P025/PPG1/TXENA
P024/PPG0/STOPWT
P023/SCS1/TXDB
P022/SOT1/RXDB
P021/SIN1/TXENB/INT0
P020/SCK1/TRG0
AVSS0/AVRL0
AVRH0
P017/AN7/INT5
AVCC0
(FPT-64P-M24)
Document Number: 002-04665 Rev *A
Page 12 of 175
MB91580M/S Series
3.
Pin Description
MB91F583AM/F584AM/F585AM
Pin No.
83
I/O circuit
type*
Pin name
X0
Function
Main clock oscillation input pin
A
84
X1
Main clock oscillation output pin
67
NMIX
B
Interrupt input pin without mask
88
RSTX
B
External reset input pin
81
MD0
C
Mode pin 0 (with high-voltage control)
82
MD1
C
Mode pin 1 (with high-voltage control)
2
P000
D
General-purpose I/O port
4
P001
D
General-purpose I/O port
7
P002
D
General-purpose I/O port
9
P003
D
General-purpose I/O port
11
P004
D
General-purpose I/O port
13
P005
D
General-purpose I/O port
15
P006
D
General-purpose I/O port
17
P007
D
General-purpose I/O port
P010
19
20
21
IN0
General-purpose I/O port
F
AN0
ADC analog 0 input pin
P011
General-purpose I/O port
IN1
F
ADC analog 1 input pin
P012
General-purpose I/O port
IN2
F
IN3
General-purpose I/O port
F
16-bit input capture ch.3 external pulse input pin
AN3
ADC analog 3 input pin
P014
General-purpose I/O port
TRG1
F
AN4
PPG ch.4, ch.5 external trigger
ADC analog 4 input pin
P015
24
27
16-bit input capture ch.2 external pulse input pin
ADC analog 2 input pin
P013
23
16-bit input capture ch.1 external pulse input pin
AN1
AN2
22
16-bit input capture ch.0 external pulse input pin
General-purpose I/O port
F
AN5
ADC analog 5 input pin
P016
General-purpose I/O port
AN6
G
INT6
Document Number: 002-04665 Rev *A
ADC analog 6 input pin
INT6 external interrupt input pin
Page 13 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P017
29
35
AN7
General-purpose I/O port
G
INT5 external interrupt input pin
P020
General-purpose I/O port
SCK1
D
PPG ch.0 to ch.3 external trigger
P021
General-purpose I/O port
Multi-function serial ch.1 serial data input pin
L
TXENB
FlexRay ch.B operation enable output pin
INT0
INT0 external interrupt input pin
P022
General-purpose I/O port
SOT1
K
RXDB
SCS1
General-purpose I/O port
K
FlexRay ch.A operation enable output pin
P024
General-purpose I/O port
PPG0
D
42
PPG1
PPG ch.0 output pin
FlexRay Stopwatch input pin
P025
41
Multi-function serial ch.1 serial chip select I/O pin
TXDB
STOPWT
40
Multi-function serial ch.1 serial data output pin
FlexRay ch.B data input pin
P023
39
Multi-function serial ch.1 clock I/O pin
TRG0
36
38
ADC analog 7 input pin
INT5
SIN1
37
Function
General-purpose I/O port
K
PPG ch.1 output pin
TXENA
FlexRay ch.A operation enable output pin
P026
General-purpose I/O port
PPG2
K
PPG ch.2 output pin
RXDA
FlexRay ch.A data input pin
P027
General-purpose I/O port
PPG3
K
TXDA
FlexRay ch.A data output pin
P030
53
PPG ch.3 output pin
General-purpose I/O port
M
DAOUT
DAC analog output pin
P031
54
General-purpose I/O port
F
AN14
Document Number: 002-04665 Rev *A
ADC analog 14 input pin
Page 14 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P032
55
Function
General-purpose I/O port
F
AN13
ADC analog 13 input pin
P033
General-purpose I/O port
TIOB1
Base timer ch.1 TIOB input pin
61
F
TOT3
Reload timer ch.3 output pin
AN12
ADC analog 12 input pin
P034
General-purpose I/O port
TIOA1
62
Base timer ch.1 TIOA I/O pin
F
TIN3
Reload timer ch.3 event input pin
AN11
ADC analog 11 input pin
P035
General-purpose I/O port
TIOB0
63
Base timer ch.0 TIOB input pin
F
TOT2
Reload timer ch.2 output pin
AN10
ADC analog 10 input pin
P036
General-purpose I/O port
TIOA0
64
Base timer ch.0 TIOA output pin
F
TIN2
Reload timer ch.2 event input pin
AN9
ADC analog 9 input pin
P037
68
General-purpose I/O port
F
AN8
ADC analog 8 input pin
P040
71
General-purpose I/O port
H
SOT0_0
P041
72
General-purpose I/O port
H
SCK0_0
Multi-function serial ch.0 clock I/O pin (0)/
I2C ch.0 clock I/O pin (SCL)
P042
74
Multi-function serial ch.0 serial data output pin (0)/
I2C ch.0 serial data I/O pin (SDA)
General-purpose I/O port
D
SIN0_0
Multi-function serial ch.0 serial data input pin (0)
P043
General-purpose I/O port
SIN0_1
78
Multi-function serial ch.0 serial data input pin (1)
D
ADTG1
A/D converter ch.8 to ch.14 external trigger input pin
MONCLK
Clock monitor output pin
P044
86
General-purpose I/O port
D
TX0
Document Number: 002-04665 Rev *A
CAN transmission data 0 output pin
Page 15 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P045
87
97
RX0
General-purpose I/O port
E
INT1 external interrupt input pin
P046
General-purpose I/O port
ADTG0
D
Clock supervisor main clock stop detection output pin
P047
General-purpose I/O port
Reload timer ch.0 output pin
E
INT2
INT2 external interrupt input pin
ADTG2
A/D converter ch.16-ch.23 external trigger input pin
P050
General-purpose I/O port
RTO5
D
Up/down counter ch.0 ZIN input pin
P051
General-purpose I/O port
RTO4
Waveform generator ch.4 output pin
D
AIN1
Up/down counter ch.1 AIN input pin
FRCK5
Free-run timer ch.5 external clock input pin
P052
General-purpose I/O port
RTO3
10
Waveform generator ch.3 output pin
D
BIN1
Up/down counter ch.1 BIN input pin
FRCK4
Free-run timer ch.4 external clock input pin
P053
General-purpose I/O port
RTO2
12
Waveform generator ch.2 output pin
D
ZIN1
Up/down counter ch.1 ZIN input pin
FRCK3
Free-run timer ch.3 external clock input pin
P054
General-purpose I/O port
RTO1
D
FRCK2
RTO0
General-purpose I/O port
D
Waveform generator ch.0 output pin
FRCK1
Free-run timer ch.1 external clock input pin
P056
General-purpose I/O port
DTTI0
D
FRCK0
RX1
Waveform generator output stop signal input pin 0
Free-run timer ch.0 external clock input pin
P060
59
Waveform generator ch.1 output pin
Free-run timer ch.2 external clock input pin
P055
18
Waveform generator ch.5 output pin
ZIN0
8
16
A/D converter ch.0 to ch.7 external trigger input pin
MM
TOT0
14
CAN reception data 0 input pin
INT1
98
6
Function
General-purpose I/O port
E
INT7
Document Number: 002-04665 Rev *A
CAN reception data 1 input pin
INT7 external interrupt input pin
Page 16 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P061
60
General-purpose I/O port
D
TX1
CAN transmission data 1 output pin
P062
65
General-purpose I/O port
D
SIN2
Multi-function serial ch.2 serial data input pin
P063
General-purpose I/O port
66
H
SOT2
69
General-purpose I/O port
H
SCK2
General-purpose I/O port
D
SCS2
P066
Multi-function serial ch.2 serial chip select I/O pin
D
P070
99
Multi-function serial ch.2 clock I/O pin/
I2C ch.2 clock I/O pin (SCL)
P065
70
Multi-function serial ch.2 serial data output pin/
I2C ch.2 serial data I/O pin (SDA)
P064
73
Function
TIN0
General-purpose I/O port
General-purpose I/O port
E
Reload timer ch.0 event input pin
INT3
INT3 external interrupt input pin
P071
General-purpose I/O port
TIN1
3
Reload timer ch.1 event input pin
E
AIN0
Up/down counter ch.0 AIN input pin
INT4
INT4 external interrupt input pin
P072
General-purpose I/O port
TOT1
5
Reload timer ch.1 output pin
D
BIN0
Up/down counter ch.0 BIN input pin
RTO6
Waveform generator ch.6 output pin
P080
General-purpose I/O port
79
H
SOT0_1
P081
80
General-purpose I/O port
H
SCK0_1
Multi-function serial ch.0 clock I/O pin (1)/
I2C ch.0 clock I/O pin (1) (SCL)
P082
89
Multi-function serial ch.0 serial data output pin (1)/
I2C ch.0 serial data I/O pin (1) (SDA)
General-purpose I/O port
D
SIN3
Multi-function serial ch.3 serial data input pin
P083
90
General-purpose I/O port
H
SOT3
I2C ch.3 serial data I/O pin (SDA)
P084
91
Multi-function serial ch.3 serial data output pin/
General-purpose I/O port
H
SCK3
Document Number: 002-04665 Rev *A
Multi-function serial ch.3 clock I/O pin/
I2C ch.3 clock I/O pin (SCL)
Page 17 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P085
94
Function
General-purpose I/O port
D
SCS3
Multi-function serial ch.3 serial chip select I/O pin
95
P086
D
General-purpose I/O port
96
P087
D
General-purpose I/O port
P090
32
General-purpose I/O port
F
AN16
ADC analog 16 input pin
P091
33
General-purpose I/O port
F
AN17
ADC analog 17 input pin
P092
34
43
44
General-purpose I/O port
F
AN18
ADC analog 18 input pin
P093
General-purpose I/O port
PPG4
F
PPG ch.4 output pin
AN19
ADC analog 19 input pin
P094
General-purpose I/O port
PPG5
F
AN20
ADC analog 20 input pin
P095
45
PPG ch.5 output pin
General-purpose I/O port
F
AN21
ADC analog 21 input pin
P096
46
General-purpose I/O port
F
AN22
ADC analog 22 input pin
P097
52
General-purpose I/O port
F
AN23
ADC analog 23 input pin
47
P100
D
General-purpose I/O port
48
P101
D
General-purpose I/O port
49
P102
D
General-purpose I/O port
77
DEBUGIF
I
DEBUG I/F pin
28
AVCC0
-
A/D converter analog power supply
58
AVCC1
-
A/D converter analog power supply
30
AVRH0
-
A/D converter upper limit reference voltage
57
AVRH1
-
A/D converter upper limit reference voltage
AVSS0
31
A/D converter GND
-
AVRL0
A/D converter lower limit reference voltage
AVSS1
56
A/D converter GND
-
AVRL1
A/D converter lower limit reference voltage
93
C
-
External capacity connection output pin
25, 50, 76,
100
VCC5
-
+5.0V power supply
Document Number: 002-04665 Rev *A
Page 18 of 175
MB91580M/S Series
Pin No.
1, 26, 51,
75, 85, 92
I/O circuit
type*
Pin name
VSS
-
Function
GND
* For I/O circuit types, see 4 I/O Circuit Type
Document Number: 002-04665 Rev *A
Page 19 of 175
MB91580M/S Series
MB91F583AS/F584AS/F585AS
Pin No.
I/O circuit
type*
Pin name
Function
53
X0
54
X1
Main clock oscillation input pin
44
NMIX
B
Interrupt input pin without mask
58
RSTX
B
External reset input pin
51
MD0
C
Mode pin 0 (with high-voltage control)
52
MD1
C
Mode pin 1 (with high-voltage control)
F
16-bit input capture ch.0 external pulse input pin
A
Main clock oscillation output pin
P010
11
12
13
14
15
IN0
General-purpose I/O port
AN0
ADC analog 0 input pin
P011
General-purpose I/O port
IN1
F
AN1
ADC analog 1 input pin
P012
General-purpose I/O port
IN2
F
ADC analog 2 input pin
P013
General-purpose I/O port
IN3
F
ADC analog 3 input pin
P014
General-purpose I/O port
TRG1
F
PPG ch.4, ch.5 external trigger
ADC analog 4 input pin
P015
General-purpose I/O port
F
AN5
ADC analog 5 input pin
P016
General-purpose I/O port
AN6
G
INT6
AN7
ADC analog 6 input pin
INT6 external interrupt input pin
P017
22
16-bit input capture ch.3 external pulse input pin
AN3
16
19
16-bit input capture ch.2 external pulse input pin
AN2
AN4
17
16-bit input capture ch.1 external pulse input pin
General-purpose I/O port
G
ADC analog 7 input pin
INT5
INT5 external interrupt input pin
P020
General-purpose I/O port
SCK1
D
Multi-function serial ch.1 clock I/O pin
TRG0
PPG ch.0 to ch.3 external trigger
P021
General-purpose I/O port
SIN1
23
Multi-function serial ch.1 serial data input pin
L
TXENB
FlexRay ch.B operation enable output pin
INT0
INT0 external interrupt input pin
Document Number: 002-04665 Rev *A
Page 20 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P022
24
25
26
27
28
29
SOT1
Function
General-purpose I/O port
K
Multi-function serial ch.1 serial data output pin
RXDB
FlexRay ch.B data input pin
P023
General-purpose I/O port
SCS1
K
Multi-function serial ch.1 serial chip select I/O pin
TXDB
FlexRay ch.B data output pin
P024
General-purpose I/O port
PPG0
D
PPG ch.0 output pin
STOPWT
FlexRay Stopwatch input pin
P025
General-purpose I/O port
PPG1
K
PPG ch.1 output pin
TXENA
FlexRay ch.A operation enable output pin
P026
General-purpose I/O port
PPG2
K
PPG ch.2 output pin
RXDA
FlexRay ch.A data input pin
P027
General-purpose I/O port
PPG3
K
TXDA
FlexRay ch.A data output pin
P030
34
PPG ch.3 output pin
General-purpose I/O port
M
DAOUT
DAC analog output pin
P031
35
General-purpose I/O port
F
AN14
ADC analog 14 input pin
P032
General-purpose I/O port
36
F
AN13
ADC analog 13 input pin
P033
General-purpose I/O port
TIOB1
40
Base timer ch.1 TIOB input pin
F
TOT3
Reload timer ch.3 output pin
AN12
ADC analog 12 input pin
P034
General-purpose I/O port
TIOA1
41
Base timer ch.1 TIOA I/O pin
F
TIN3
Reload timer ch.3 event input pin
AN11
ADC analog 11 input pin
P035
General-purpose I/O port
TIOB0
42
Base timer ch.0 TIOB input pin
F
TOT2
Reload timer ch.2 output pin
AN10
ADC analog 10 input pin
Document Number: 002-04665 Rev *A
Page 21 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P036
43
TIOA0
General-purpose I/O port
F
Reload timer ch.2 event input pin
AN9
ADC analog 9 input pin
P037
General-purpose I/O port
F
AN8
ADC analog 8 input pin
P040
46
General-purpose I/O port
H
SOT0_0
P041
47
P042
48
General-purpose I/O port
SIN0_0
Multi-function serial ch.0 serial data input pin (0)
P043
General-purpose I/O port
ADTG1
D
A/D converter ch.8 to ch.14 external trigger input pin
MONCLK
Clock monitor output pin
P044
General-purpose I/O port
D
TX0
CAN transmission data 0 output pin
P045
General-purpose I/O port
RX0
E
INT1
ADTG0
CAN reception data 0 input pin
INT1 external interrupt input pin
P046
General-purpose I/O port
D
A/D converter ch.0 to ch.7 external trigger input pin
MM
Clock supervisor main clock stop detection output pin
P047
General-purpose I/O port
TOT0
62
Reload timer ch.0 output pin
E
INT2
INT2 external interrupt input pin
ADTG2
A/D converter ch.19 to ch.20 external trigger input pin
P050
4
Multi-function serial ch.0 clock I/O pin (0)/
I2C ch.0 clock I/O pin (0) (SCL)
D
56
61
Multi-function serial ch.0 serial data output pin(0)/
I2C ch.0 serial data I/O pin (0) (SDA)
General-purpose I/O port
H
SCK0_0
57
Base timer ch.0 TIOA output pin
TIN2
45
50
Function
RTO5
General-purpose I/O port
D
Waveform generator ch.5 output pin
ZIN0
Up/down counter ch.0 ZIN input pin
P051
General-purpose I/O port
RTO4
5
Waveform generator ch.4 output pin
D
AIN1
Up/down counter ch.1 AIN input pin
FRCK5
Free-run timer ch.5 external clock input pin
Document Number: 002-04665 Rev *A
Page 22 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
P052
General-purpose I/O port
RTO3
6
Waveform generator ch.3 output pin
D
BIN1
Up/down counter ch.1 BIN input pin
FRCK4
Free-run timer ch.4 external clock input pin
P053
General-purpose I/O port
RTO2
7
Waveform generator ch.2 output pin
D
ZIN1
Up/down counter ch.1 ZIN input pin
FRCK3
Free-run timer ch.3 external clock input pin
P054
8
9
10
63
RTO1
General-purpose I/O port
D
Free-run timer ch.2 external clock input pin
P055
General-purpose I/O port
RTO0
D
Waveform generator ch.0 output pin
FRCK1
Free-run timer ch.1 external clock input pin
P056
General-purpose I/O port
DTTI0
D
Waveform generator output stop signal input pin 0
FRCK0
Free-run timer ch.0 external clock input pin
P070
General-purpose I/O port
TIN0
E
Reload timer ch.0 event input pin
INT3
INT3 external interrupt input pin
P071
General-purpose I/O port
TIN1
Reload timer ch.1 event input pin
E
AIN0
Up/down counter ch.0 AIN input pin
INT4
INT4 external interrupt input pin
P072
General-purpose I/O port
TOT1
3
Reload timer ch.1 output pin
D
BIN0
Up/down counter ch.0 BIN input pin
RTO6
Waveform generator ch.6 output pin
P093
31
Waveform generator ch.1 output pin
FRCK2
2
30
Function
PPG4
General-purpose I/O port
F
PPG ch.4 output pin
AN19
ADC analog 19 input pin
P094
General-purpose I/O port
PPG5
F
AN20
PPG ch.5 output pin
ADC analog 20 input pin
49
DEBUGIF
I
DEBUG I/F pin
18
AVCC0
-
A/D converter analog power supply
39
AVCC1
-
A/D converter analog power supply
Document Number: 002-04665 Rev *A
Page 23 of 175
MB91580M/S Series
Pin No.
I/O circuit
type*
Pin name
Function
20
AVRH0
-
A/D converter upper limit reference voltage
38
AVRH1
-
A/D converter upper limit reference voltage
AVSS0
21
A/D converter GND
-
AVRL0
A/D converter lower limit reference voltage
AVSS1
37
A/D converter GND
-
AVRL1
A/D converter lower limit reference voltage
60
C
-
External capacity connection output pin
32, 64
VCC5
-
+5.0V power supply
1, 33, 55, 59
VSS
-
GND
* For I/O circuit types, see 4 I/O Circuit Type
Document Number: 002-04665 Rev *A
Page 24 of 175
MB91580M/S Series
4.
I/O Circuit Type
Type
Circuit
Remarks
A
Oscillation feedback resistor: Approx. 1
MΩ
X1
Clock input
X0
Standby control signal
B
CMOS hysteresis input
With 50 kΩ pull-up resistor
Pull-up resistor
CMOS hysteresis input
C
Schmitt input
With high withstand voltage control
N-ch
Mode input
N-ch
High withstand voltage mode
input
N-ch
High withstand voltage control
N-ch
Document Number: 002-04665 Rev *A
Page 25 of 175
MB91580M/S Series
Type
Circuit
Remarks
D
General-purpose I/O port
Pull-up control
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50kΩ pull-up resistor control
P-ch
P-ch
Digital output
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
N-ch
R
CMOS hysteresis input
Automotive input
Standby control
E
General-purpose I/O port
Pull-up control
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
With 50 kΩ pull-up resistor control
P-ch
P-ch
Digital output
N-ch
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
R
CMOS hysteresis input
Automotive input
Standby control
Document Number: 002-04665 Rev *A
Page 26 of 175
MB91580M/S Series
Type
Circuit
Remarks
F
Pull-up control
With analog input, general-purpose
I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
P-ch
P-ch
With 50 kΩ pull-up resistor control
Digital output
N-ch
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
R
CMOS hysteresis input
Automotive input
Standby control
Analog input
G
Pull-up control
With analog input, general-purpose
I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
P-ch
P-ch
With 50 kΩ pull-up resistor control
Digital output
N-ch
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
R
CMOS hysteresis input
Automotive input
Standby control
Analog input
Document Number: 002-04665 Rev *A
Page 27 of 175
MB91580M/S Series
Type
Circuit
Remarks
2
H
With I C, general-purpose I/O port
Pull-up control
P-ch
P-ch
Digital output
CMOS level output
2
IOH=-3mA, IOL=3mA (at I C output)
IOH=-2/-5mA, IOL=2/5mA (other than
above)
With 50 kΩ pull-up resistor control
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
N-ch
Automotive input (0.8Vcc/0.5Vcc)
R
CMOS hysteresis input
Automotive input
Standby control
Open drain I/O
I
Digital output
TTL schmitt input
Document Number: 002-04665 Rev *A
Page 28 of 175
MB91580M/S Series
Type
Circuit
Remarks
K
Pull-up control
With analog output,
general-purpose I/O port
CMOS level output
IOH=-2/-4mA, IOL=2/4mA
P-ch
With 50 kΩ pull-up resistor control
P-ch
Digital output
FlexRay input (0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vccc)
N-ch
R
FlexRay input
Automotive input
Standby control
Analog output
L
Pull-up control
With analog output,
general-purpose I/O port
CMOS level output
IOH=-2/-4mA, IOL=2/4mA
P-ch
With 50 kΩ pull-up resistor control
P-ch
Digital output
N-ch
FlexRay input (0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
R
FlexRay input
Automotive input
Standby control
Analog output
Document Number: 002-04665 Rev *A
Page 29 of 175
MB91580M/S Series
Type
Circuit
Remarks
M
Pull-up control
With D/A converter output,
general-purpose I/O port
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
P-ch
With 50 kΩ pull-up resistor control
P-ch
Digital output
N-ch
CMOS hysteresis input
(0.7Vcc/0.3Vcc)
Automotive input (0.8Vcc/0.5Vcc)
R
CMOS hysteresis input
Automotive input
Standby control
D/A converter output
Document Number: 002-04665 Rev *A
Page 30 of 175
MB91580M/S Series
5. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions
that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress
semiconductor devices.
5.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their sales representative
beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/output functions.
1.
Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
2.
Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause
large current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3.
Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such
pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected
to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing
large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is
called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the
design of products.
Document Number: 002-04665 Rev *A
Page 31 of 175
MB91580M/S Series
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage, or where extremely high levels of
reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating
controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use.
The company will not be responsible for damages arising from such use without prior approval.
5.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on
the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket
contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established
a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Document Number: 002-04665 Rev *A
Page 32 of 175
MB91580M/S Series
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the
following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion
generation may be needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the
level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock
loads is recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
5.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1.
Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels
are anticipated, consider anti-humidity processing.
2.
Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such
cases, use anti-static measures or processing to prevent discharges.
3.
Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the
device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4.
Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
5.
Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If
devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
Document Number: 002-04665 Rev *A
Page 33 of 175
MB91580M/S Series
6.
Handling Devices
The latch-up prevention and pin processing are explained below.
For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings
is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply
current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from
exceeding the maximum ratings in device application.
Also, the analog power supplies (AVCC0, AVCC1, AVRH0, AVRH1) and analog input must not exceed the digital
power supply (VCC5) when the power supply to the analog system is turned on or off.
In the correct power-on sequence, turn on the digital power supply voltage (VCC5) and analog power supply voltages
(AVCC0, AVCC1, AVRH0, AVRH1) simultaneously. Alternatively, turn on the digital power supply voltage (VCC5) first,
and then turn on the analog power supplies (AVCC0, AVCC1, AVRH0, AVRH1).
Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to device malfunction or
latch-up. Connect a 2kΩ or higher resistor to each of unused input pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state
and treated in the same way as for the input pins.
Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be at the
same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external
power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised
ground level, and fulfill the total output current standard, etc. As shown in following figure, all VSS power supply pins
must be treated in the similar way. If multiple VCC or VSS systems are connected, the device cannot operate correctly
even within the guaranteed operating range.
Power Supply Input Pins
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
Document Number: 002-04665 Rev *A
VCC
Page 34 of 175
MB91580M/S Series
The power supply pins should be connected to VCC and VSS of this device at the low impedance from the power
supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is
recommended to use as a bypass capacitor between VCC and VSS pins.
Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to
lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close
position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode pin (MD[1:0])
Connect the MD[1:0] mode pin to the VCC or VSS pin directly.
To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode
pin and VCC or VSS pin on the printed circuit board. Also, use the low-impedance pin connection.
During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to have 50μs or
longer (between 0.2V and 2.7V) during power-on.
Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue
to operate at the free running frequency of the self oscillator circuit built in the PLL. This operation is not guaranteed.
Treatment of A/D converter power supply pins
Connect the pins to have AVCC0 = AVCC1 = AVRH0 = AVRH1 = VCC,
AVSS0/AVRL0 = AVSS1/AVRL1 = VSS even if the A/D converter is not used.
Note on using external clock
The external clock is unsupported.
External direct clock input cannot use.
Document Number: 002-04665 Rev *A
Page 35 of 175
MB91580M/S Series
Power-on sequence of A/D converter power supply analog inputs
Be sure to turn on the digital power supply (VCC5) first, and then turn on the A/D converter power supplies (AVCC0,
AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and analog inputs (AN0 to AN14, AN16 to AN23). Also, turn off the A/D
converter power supplies (AVCC0, AVCC1, AVRH0, AVRH1, AVRL0, AVRL1) and analog inputs (AN0 to AN14, AN16
to AN23) first, and then turn off the digital power supply (VCC5). When the AVRH0 and AVRH1 pin voltages are turned
on or off, they must not exceed AVCC0 and AVCC1. Even if a common analog input pin is used as an input port, its
input voltage must not exceed AVCC0 or AVCC1. (However, the analog power supply voltage and digital power supply
voltage can be turned on or off simultaneously.)
Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the
internal stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the
latest data sheet.
Function Switching of a Multiplexed Port
To switch between the port function and the multiplexed pin function, use the PFR (port function register). For details,
see "I/O PORTS" in Hardware Manual.
Low-power Consumption Mode
To set Sleep mode / Watch mode / Stop mode, or Watch mode (power-off) / Stop mode (power-off), see the section
"Launching Sleep mode / Watch mode / Stop mode" or "Launching Watch mode (power-off) / Stop mode (power-off)"
of "POWER CONSUMPTION CONTROL" in Hardware Manual, and follow the procedures.
Do not perform the following when using a monitor debugger.
•Do not set a break point for the low-power consumption transition program.
•Do not execute an operation step for the low-power consumption transition program.
Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, take
care not to clear its status flag erroneously.
The program must be written not to clear the flag to the status bit, and to set the control bits to have the desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a
single bit only.) The Byte, Half-word, or Word access must be used to write data in the control bits and status flag
simultaneously. During this time, take care not to clear other bits (in this case, the bits of status flag) erroneously.
Note:
These points can be ignored because the bit instructions already take the points into consideration for
registers that support read-modify-write (RMW) operations. These points must be considered when using the bit
instructions for registers that do not support RMW operations.
Document Number: 002-04665 Rev *A
Page 36 of 175
MB91580M/S Series
7.
Block Diagram
MB91F583AM/F584AM/F585AM
Regulator
F R 81s C PU core
M P U
CR oscillator
Ins truc tio n
D e b u g In te rfa ce
D ata
XBS
Power-on reset
X B S C ros sbar S w itch
Wild register
RA M
F la sh
Fro m Ma s te r
On-chip bus Layer 2
To S la ve
Fro m Ma s te r
On-chip bus Layer 1
To S la ve
On-chip bus
Main Flash/WorkFlash
RAMECC/Diagnosis
(XBS-RAM)
DMAC
Flash control register
Bus diagnosis register
Bus
performance
counter
Peripheral bus bridge
CAN (2ch)
FlexRay (1unit)
RAMECC /
Diagnosis
M D 0,M D 1,P040
Asynchronous bus bridge
Asynchronous bus bridge
RXDA-B,TXDA-B,
TXENA-B,STOPWT
Operating
mode register
B ac kUp
RA M
(PCLK1
PCLK2)
FlexRay clock control
CAN prescaler
I/O port setting
(PCLK1
16-bit peripheral bus
32-bit peripheral bus
RX0- 1,
TX0- 1
32
16
Bus bridge
PCLK2)
Multi-function serial interface (4ch)
CRC (2ch)
D/A converter
I / O P ort
TIN0- 3, TOT0- 3
TIOA0- 1, TIOB0- 1
MONCLK
(PCLK2
MTRCLK)
U/D counter (2ch)
Waveform generator (2 units (7ch))
Reload timer (4ch)
Free-run timer (6ch)
Base timer (2ch)
Input capture (4ch)
PPG (6ch)
Output compare (7ch)
Clock Monitor
A/D converter
DTTI0,RTO0-6
FRCK0-5
IN0-3
A DTG0 -2,
A N0 -14, 16-23
I / O P ort
TRG0- 1, PPG0- 5
DAOUT
Motor control extension function
WDT1 calibration
A IN0- 1, BIN0- 1,
Z IN0- 1
SOT0_0-1, SOT1-3,
SIN0_0-1, SIN1-3,
SCK0_0-1, SCK1-3,
SCS1-3
Bus bridge
16-bit)
(32-bit
External interrupt input (8ch)
Clock Supervisor
Interrupt request batch read
INT0- 7
Input cut-off
inhibiting signal
MM
CR oscillation (trimming)
Generation/clear of DMA transfer request
NMI
Watchdog timer (SW and HW)
RSTX
NMIX
Delay interrupt
Clock control
(clock setting, main timer, PLL timer)
Interrupt controller
Power shutdown control
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
Low-voltage detection (external
low-voltage detection)
Regulator control
Low-voltage detection (internal
low-voltage detection)
Document Number: 002-04665 Rev *A
Page 37 of 175
MB91580M/S Series
MB91F583AS/F584AS/F585AS
Regulator
F R 81s C PU core
Power-on reset
M P U
Ins truc tio n
D e b u g In te rfa ce
D ata
XBS
CR oscillator
X B S C ros sbar S w itch
Wild register
RA M
F la sh
Fro m Ma s te r
On-chip bus Layer 2
To S la ve
Fro m Ma s te r
On-chip bus Layer 1
To S la ve
On-chip bus
Main Flash/WorkFlash
RAMECC/Diagnosis
(XBS-RAM)
DMAC
Flash control register
Bus diagnosis register
Bus
performance
counter
Peripheral bus bridge
CAN (1ch)
FlexRay (1unit)
16
Bus bridge
32
Operating
mode register
RAMECC /
Diagnosis
B ac kUp
RA M
M D 0,M D 1,P040
Asynchronous bus bridge
Asynchronous bus bridge
RXDA-B,TXDA-B,
TXENA-B,STOPWT
(PCLK1
(PCLK1
PCLK2)
FlexRay clock control
CAN prescaler
I/O port setting
WDT1 calibration
16-bit peripheral bus
32-bit peripheral bus
RX0,
TX0
PCLK2)
Multi-function serial interface (2ch)
CRC (2ch)
D/A converter
I / O P ort
DAOUT
Motor control extension function
(PCLK2
A IN0- 1, BIN0- 1,
Z IN0- 1
SOT0_0, SOT1,
SIN0_0, SIN1,
SCK0_0, SCK1,
SCS1
MTRCLK)
U/D counter (2ch)
Waveform generator (2 units (7ch))
Reload timer (4ch)
Free-run timer (6ch)
Base timer (2ch)
Input capture (4ch)
PPG (6ch)
Output compare (7ch)
Clock Monitor
A/D converter
TIN0- 3, TOT0- 3
TIOA0- 1, TIOB0- 1
MONCLK
FRCK0-5
IN0-3
A DTG0- 2,
A N0- 14, 19, 20
I / O P ort
TRG0- 1, PPG0- 5
DTTI0,RTO0-6
Bus bridge
(32-bit
16-bit)
External interrupt input (7ch)
Clock Supervisor
Interrupt request batch read
INT0- 6
Input cut-off
inhibiting signal
MM
CR oscillation (trimming)
Generation/clear of DMA transfer request
NMI
Watchdog timer (SW and HW)
RSTX
NMIX
Delay interrupt
Clock control
(clock setting, main timer, PLL timer)
Interrupt controller
Power shutdown control
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
Regulator control
Low-voltage detection (external
low-voltage detection)
Low-voltage detection (internal
low-voltage detection)
Document Number: 002-04665 Rev *A
Page 38 of 175
MB91580M/S Series
8.
Memory Map
MB91F583AM/F583AS
0000_0000 H
IO area
0000_4000 H
0000_6000 H
BackUp RAM(8KB)
0001_0000 H
RAM(32KB)
IO area
0001_8000 H
MB91F584AM/F584AS
0000_0000 H
000C_0000 H
000F_FC00 H
0001_0000 H
0001_0000 H
RAM(48KB)
Flash memory
(256+64)KB
0007_0000 H
Reserved
000E_0000 H
Interrupt vector table
Reset vector table
000F_FC00 H
Flash memory
(384+64)KB
0034_0000 H
Flash memory
(512+64)KB
000F_FC00 H
Reserved
0033_0000 H
Reserved
Document Number: 002-04665 Rev *A
0007_0000 H
WorkFlash
64KB
Reserved
0033_0000 H
WorkFlash
64KB
0034_0000 H
Reserved
FFFF_FFFF H
Interrupt vector table
Reset vector table
0010_0000 H
0034_0000 H
FFFF_FFFF H
Reserved
Reserved
Interrupt vector table
Reset vector table
0010_0000 H
WorkFlash
64KB
RAM(48KB)
0001_C000 H
Reserved
Reserved
0033_0000 H
IO area
0000_4000 H BackUp RAM(8KB)
0000_6000 H
IO area
0001_C000 H
0010_0000 H
0000_0000 H
0000_4000 H BackUp RAM(8KB)
0000_6000 H
IO area
Reserved
0007_0000 H
IO area
MB91F585AM/F585AS
Reserved
FFFF_FFFF H
Page 39 of 175
MB91580M/S Series
9.
I/O Map
The following I/O map shows the relationship between memory space and registers for peripheral resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
Address offset value/Register name
+3
+2
+1
BT1TMR [R] H
BT1TMCR [R/W] B,H,W
00000000 00000000
00000000 00000000
BT1STC [R/W] B
00000000
BT1PCSR/BT1PRLL [R/W] H
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
00000000 00000000
BTSEL [R/W] B
BTSSSR [W] B, H
----0000
--------------11
ADERH [R/W] B, H, W
ADERL [R/W] B, H, W
00000000 00000000
00000000 00000000
ADCR0 [R] B,H,W
ADCS1 [R/W] B,H,W ADCS0 [R/W] B,H,W ADCR1 [R] B,H,W
00000000
------XX
XXXXXXXX
00000000
ADCT1 [R/W] B,H,W ADCT0 [R/W] B,H,W ADSCH [R/W] B,H,W ADECH [R/W] B,H,W
00010000
00101100
---00000
---00000
+0
Block
Base timer 1
A/D converter
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)
The access by the data access attribute
not described is disabled.
Initial register value after reset
The initial register values after reset are indicated as follows:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note:
It is prohibited to access addresses not described here.
Document Number: 002-04665 Rev *A
Page 40 of 175
MB91580M/S Series
MB91F583AM/F584AM/F585AM
Address offset value/Register name
Address
000000H
000004H
000008H
00000CH
+0
+1
+2
+3
PDR00[R/W] B,H,W
PDR01[R/W] B,H,W
PDR02[R/W] B,H,W
PDR03[R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR04[R/W] B,H,W
PDR05[R/W] B,H,W
PDR06[R/W] B,H,W
PDR07[R/W] B,H,W
XXXXXXXX
-XXXXXXX
-XXXXXXX
-----XXX
PDR08[R/W] B,H,W
PDR09[R/W] B,H,W
PDR10[R/W] B,H,W
XXXXXXXX
XXXXXXXX
-----XXX
-
-
-
-
-
-
-
-
WDTCR0[R/W]
WDTCPR0[W]
WDTCR1[R]
WDTCPR1[W]
B,H,W
B,H,W
B,H,W
B,H,W
-0--0000
00000000
----0010
00000000
-
-
-
-
-
Block
Port data register
-
000010H
|
Reserved
000038H
00003CH
000040H
000044H
DICR[R/W] B
-------0
Watchdog timer [S]
Reserved
-
Delay interrupt
000048H
|
-
-
Reserved
TMRLRA0[R/W] H
TMR0[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB0[R/W] H
TMCSR0[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
-
-
00005CH
000060H
000064H
Reload timer 0
000068H
|
-
-
Reserved
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
BT0TMR[R] H
BT0TMCR[R/W] H
00000000 00000000
-0000000 00000000
BT0TMCR2[R/W] B
BT0STC[R/W] B
-------0
-0-0-0-0
BT0PCSR/BT0PRLL[R/W] H
00000000 00000000
-
-
-
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
00000000 00000000
-
-
BT1TMR[R] H
BT1TMCR[R/W] H
00000000 00000000
-0000000 00000000
BT1TMCR2[R/W] B
BT1STC[R/W] B
-------0
-0-0-0-0
-
-
-
BT1PCSR/BT1PRLL[R/W] H
BT1PDUT/BT1PRLH/BT1DTBF[R/W] H
00000000 00000000
00000000 00000000
BTSEL01[R/W] B
----0000
Base timer 0
-
Document Number: 002-04665 Rev *A
BTSSSR[W] B,H
-------- ------11
Base timer 1
Base timer 0,1
Page 41 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
0000A0H
|
-
-
-
-
Reserved
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
TMRLRA1[R/W] H
TMR1[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB1[R/W] H
TMCSR1[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA2[R/W] H
TMR2[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB2[R/W] H
TMCSR2[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA3[R/W] H
TMR3[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB3[R/W] H
TMCSR3[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
-
-
-
-
IRPR0H[R] B,H,W
IRPR0L[R] B,H,W
IRPR1H[R] B,H,W
IRPR1L[R] B,H,W
00------
00------
00------
--------
IRPR2H[R] B,H,W
IRPR2L[R]
B,H,W *5
IRPR3H[R] B,H,W
IRPR3L[R] B,H,W
00------
00-----IRPR5L[R] B,H,W
Reload timer 1
Reload timer 2
Reload timer 3
000118H
|
Reserved
00011CH
000120H
000124H
000128H
00012CH
000130H
000134H
000138H
00013CH
000140 H
000144 H
--------
0000----
IRPR4H[R] B,H,W
IRPR4L[R] B,H,W
IRPR5H[R] B,H,W
00------
000000--
00------
00------
IRPR6H[R] B,H,W
IRPR6L[R] B,H,W
IRPR7H[R] B,H,W
IRPR7L[R] B,H,W
0000----
00------
00------
--------
IRPR8H[R] B,H,W
IRPR8L[R] B,H,W
IRPR9H[R] B,H,W
IRPR9L[R] B,H,W
--------
00------
00------
00------
IRPR10H[R] B,H,W
IRPR10L[R] B,H,W
IRPR11H[R] B,H,W
IRPR11L[R] B,H,W
00------
00------
00------
0000000-
IRPR12H[R] B,H,W
IRPR12L[R] B,H,W
IRPR13H[R] B,H,W
IRPR13L[R] B,H,W
0000000-
00000000
0000000-
00000000
IRPR14H[R] B,H,W
IRPR14L[R] B,H,W
IRPR15H[R] B,H,W
IRPR15L[R] B,H,W
00------
00------
00000000
0000----
IRPR16H[R] B,H,W
IRPR16L[R] B,H,W
IRPR17H[R] B,H,W
IRPR17L[R]B,H,W
00------
00------
00------
--------
-
-
-
-
IRPR18H[R]
B,H,W
--------
Interrupt request
batch read register
IRPR18L[R]
B,H,W
000000--
000148H
|
-
-
Reserved
0001FCH
Document Number: 002-04665 Rev *A
Page 42 of 175
MB91580M/S Series
Address offset value/Register name
Address
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
000228H
00022CH
+0
+1
+2
Block
+3
PCN0[R/W] B,H,W
PCSR0[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT0[W] H,W
PTMR0[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN1[R/W] B,H,W
PCSR1[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT1[W] H,W
PTMR1[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN2[R/W] B,H,W
PCSR2[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT2[W] H,W
PTMR2[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN3[R/W] B,H,W
PCSR3[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT3[W] H,W
PTMR3[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN4[R/W] B,H,W
PCSR4[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT4[W] H,W
PTMR4[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN5[R/W] B,H,W
PCSR5[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT5[W] H,W
PTMR5[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
-
-
GTRS0[R/W] B,H,W
GTRS1[R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
000230H
|
Reserved
0002BCH
0002C0H
0002C4H
GTRS2[R/W] B,H,W
-
-0000000 -0000000
0002C8H
-
-
0002CCH
-
-
0002D0H
-
-
0002D4H
-
-
0002D8H
GTREN0[R/W] H,W
-
-------- --000000
0002DCH
-
0002E0H
-
0002E4H
-
0002E8H
-
PPG Control
GATEC0[R/W] B,H,W
------00
GATEC4[R/W] B,H,W
------00
-
Document Number: 002-04665 Rev *A
-
Reserved
GATEC2[R/W] B,H,W
------00
-
-
-
-
PPG GATE Control
Page 43 of 175
MB91580M/S Series
Address offset value/Register name
Address
0002ECH
0002F0H
0002F4H
0002F8H
0002FCH
+0
+1
+2
+3
-
-
-
-
RCRH0[W] H,W
RCRL0[W] B,H,W
UDCRH0[R] H,W
UDCRL0[R] B,H,W
00000000
00000000
00000000
00000000
CCR0[R/W] B,H
-
00000000 -0001000
RCRH1[W] H,W
RCRL1[W] B,H,W
UDCRH1[R] H,W
00000000
00000000
00000000
CCR1[R/W] B,H
-
00000000 -0001000
000300H
-
000304H
-
000308H
-
00030CH
-
CSR0[R] B
Block
Reserved
U/D counter 0
00000000
UDCRL1[R] B,H,W
00000000
CSR1[R] B
U/D counter 1
00000000
Reserved
-
-
-
-
-
-
Document Number: 002-04665 Rev *A
Reserved
Reserved
Page 44 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
-
-
000314H
-
-
-
000318H
-
00031CH
-
-
-
000324H
000328H
00032CH
000330H
000334H
000338H
00033CH
000340H
000344H
000348H
00034CH
000350H
000354H
000358H
00035CH
000360H
000364H
Block
MPUCR[R/W] H
000310H
000320H
+3
000000-0 ----0100
-
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
-
-
DPVSR[R/W] H
-------- 00000--0
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
-
-
DESR[R/W] H
-------- 00000--0
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR0[R/W] H
000000-0 00000--0
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR1[R/W] H
MPU [S]
000000-0 00000--0
(Only the CPU can
access this area)
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR2[R/W] H
000000-0 00000--0
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR3[R/W] H
000000-0 00000--0
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR4[R/W] H
000000-0 00000--0
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR5[R/W] H
000000-0 00000--0
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
Document Number: 002-04665 Rev *A
PACR6[R/W] H
000000-0 00000--0
Page 45 of 175
MB91580M/S Series
Address offset value/Register name
Address
000368H
+0
+1
+2
+3
Block
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00036CH
-
000370H
-
000374H
-
000378H
-
00037CH
-
000380H
-
000384H
-
000388H
-
00038CH
-
000390H
-
000394H
-
000398H
-
00039CH
-
0003A0H
-
0003A4H
-
0003A8H
-
0003ACH
-
MPU [S]
(Only the CPU can
access this area)
PACR7[R/W] H
000000-0 00000--0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved [S]
Reserved [S]
0003B0H
|
-
Reserved [S]
0003CCH
0003D0H
-
0003D4H
-
0003D8H
-
0003DCH
-
Reserved [S]
0003E0H
|
-
-
-
-
ICSEL0[R/W] B,H,W
ICSEL1[R/W] B,H,W
ICSEL2[R/W] B,H,W
ICSEL3[R/W] B,H,W
-----000
-------0
-------0
-------0
ICSEL4[R/W] B,H,W
ICSEL5[R/W] B,H,W
ICSEL6[R/W] B,H,W
ICSEL7[R/W] B,H,W
-------0
-------0
-------0
ICSEL8[R/W] B,H,W
ICSEL9[R/W] B,H,W
-------0
-------0
Reserved [S]
0003FCH
000400H
000404H
000408H
00040CH
Generation and
clear of DMA
ICSEL10[R/W] B,H,W ICSEL11[R/W] B,H,W transfer request
------00
-------0
-----000
ICSEL12[R/W] B,H,W ICSEL13[R/W] B,H,W ICSEL14[R/W] B,H,W ICSEL15[R/W] B,H,W
-------0
-------0
Document Number: 002-04665 Rev *A
-------0
-------0
Page 46 of 175
MB91580M/S Series
Address offset value/Register name
Address
000410H
000414H
+0
+1
+2
+3
ICSEL16[R/W] B,H,W ICSEL17[R/W] B,H,W ICSEL18[R/W] B,H,W ICSEL19[R/W] B,H,W
-------0
-------0
-------0
-------0
ICSEL20[R/W] B,H,W ICSEL21[R/W] B,H,W ICSEL22[R/W] B,H,W ICSEL23[R/W] B,H,W
Generation and
clear of DMA
ICSEL24[R/W] B,H,W ICSEL25[R/W] B,H,W ICSEL26[R/W] B,H,W ICSEL27[R/W] B,H,W transfer request
-----000
-----000
-------0
-------0
-------0
-----000
-----000
-----000
00041CH
-
-
-
-
000420H
-
-
-
-
-
-
-
-
ICR00[R/W] B,H,W
ICR01[R/W] B,H,W
ICR02[R/W] B,H,W
ICR03[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR04[R/W] B,H,W
ICR05[R/W] B,H,W
ICR06[R/W] B,H,W
ICR07[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR08[R/W] B,H,W
ICR09[R/W] B,H,W
ICR10[R/W] B,H,W
ICR11[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR12[R/W] B,H,W
ICR13[R/W] B,H,W
ICR14[R/W] B,H,W
ICR15[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR16[R/W] B,H,W
ICR17[R/W] B,H,W
ICR18[R/W] B,H,W
ICR19[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR20[R/W] B,H,W
ICR21[R/W] B,H,W
ICR22[R/W] B,H,W
ICR23[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR24[R/W] B,H,W
ICR25[R/W] B,H,W
ICR26[R/W] B,H,W
ICR27[R/W] B,H,W
---11111
---11111
---11111
---11111
000418H
Block
000424H
|
Reserved
00043CH
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
ICR28[R/W] B,H,W
ICR29[R/W] B,H,W
ICR30[R/W] B,H,W
ICR31[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR32[R/W] B,H,W
ICR33[R/W] B,H,W
ICR34[R/W] B,H,W
ICR35[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR36[R/W] B,H,W
ICR37[R/W] B,H,W
ICR38[R/W] B,H,W
ICR39[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR40[R/W] B,H,W
ICR41[R/W] B,H,W
ICR42[R/W] B,H,W
ICR43[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR44[R/W] B,H,W
ICR45[R/W] B,H,W
ICR46[R/W] B,H,W
ICR47[R/W] B,H,W
---11111
---11111
---11111
---11111
-
-
-
-
Interrupt controller
[S]
000470H
|
Reserved [S]
00047CH
Document Number: 002-04665 Rev *A
Page 47 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
Reset control [S]
RSTRR[R]
000480H
B,H,W
XXXX--XX
000484H
000488H
00048CH
DIVR0[R/W] B,H,W
000-----
RSTCR[R/W] B,H,W
STBCR[R/W] B,H,W
111----0
000---11*
-
-
-
DIVR2[R/W] B,H,W
0011----
-
Power
consumption
control [S]
* Writing to STBCR
by DMA is
disabled.
-
Reserved [S]
-
Clock control [S]
Reserved [S]
-
-
-
-
IORR0[R/W] B,H,W
IORR1[R/W] B,H,W
IORR2[R/W] B,H,W
IORR3[R/W] B,H,W
-0000000
-0000000
-0000000
-0000000
IORR4[R/W] B,H,W
IORR5[R/W] B,H,W
IORR6[R/W] B,H,W
IORR7[R/W] B,H,W
-0000000
-0000000
-0000000
-0000000
000498H
-
-
-
-
00049CH
-
-
-
-
0004A0H
-
-
-
-
Reserved
-
-
-
CAN prescaler
-
-
-
-
Reserved
-
-
-
-
Reserved
-
-
-
-
Reserved
000490H
000494H
0004A4H
CANPRE[R/W] B,H,W
---00000
DMA transfer
request from a
peripheral [S]
0004A8H
|
0004ACH
0004B0H
0004B4H
|
0004C0H
0004C4H
0004C8H
CUCR1[R/W] B,H,W
CUTD1[R/W] B,H,W
-------- ---0--00
11000011 01010000
WDT1 calibration
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CCH
|
-
-
-
-
0004E0H
-
-
CSCFG[R/W] B,H,W
CMCFG[R/W] B,H,W
---0----
0004E4H
-
00000000
-
-
-
0004E8H
PLL2DIVM[R/W]
B,H,W
PLL2DIVN[R/W]
B,H,W
PLL2DIVG[R/W]
B,H,W
PLL2MULG[R/W]
B,H,W
----0000
-0000000
----0000
00000000
PLL2CTRL[R/W]
B,H,W
PLL2DIVK[R/W]
----0000
-------0
Reserved
0004DCH
0004ECH
B,H,W
Document Number: 002-04665 Rev *A
CLKR2[R/W] B,H,W
000--000
Clock monitor
FlexRay
clock control *5
-
Page 48 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
Block
+3
0004F0H
|
-
-
-
-
Reserved
0004FCH
000500H
-
Reserved
000504H
-
Reserved
000508H
|
-
-
-
CSELR[R/W] B,H,W
CMONR[R] B,H,W
MTMCR[R/W] B,H,W
-0----00
-01---00
00001111
-
Reserved
00050CH
000510H
000514H
PLLCR[R/W] B,H,W
CSTBR[R/W] B,H,W
PTMCR[R/W] B,H,W
00-00000 11110000
----0000
00------
000518H
-
00051CH
-
000520H
CCPSSELR[R/W]
B,H,W
-
CPUAR[R/W] B,H,W
000528H
00052CH
-
-
-
Clock control [S]
-
Reset [S]
-
-
Reserved [S]
-
-
CCPSDIVR[R/W]
B,H,W
CCPLLFBR[R/W]
B,H,W
CCSSFBR0[R/W]
B,H,W
CCSSFBR1[R/W]
B,H,W
-0000000
--000000
---00000
CCSSCCR0[R/W]
B,H,W
CCSSCCR1[R/W]
----0000
000----- --------
CCCGRCR0[R/W]
B,H,W
CCCGRCR1[R/W]
B,H,W
0---XXXX
-------0
000524H
-
-000-000
B,H,W
CCCGRCR2[R/W]
B,H,W
00----00
00000000
00000000
CCPMUCR0[R/W]
B,H,W
CCPMUCR1[R/W]
B,H,W
Clock control 2
000530H
-
-
0-----00
0--00000
000534H
-
-
-
-
000538H
-
-
-
-
00053CH
-
-
-
-
-
-
-
-
EIRR0[R/W] B,H,W
ENIR0[R/W] B,H,W
ELVR0[R/W] B,H,W
External interrupt
XXXXXXXX
00000000
00000000 00000000
(INT0 to 7)
-
-
-
-
Reserved
-
-
CSV
000540H
|
Reserved
00054CH
000550H
000554H
|
000568H
00056CH
-
CSVCR[R/W] B
-0--1--0
Document Number: 002-04665 Rev *A
Page 49 of 175
MB91580M/S Series
Address offset value/Register name
Address
000570H
+0
+1
+2
Block
+3
CRTR[R/W] B,H,W
01111111
-
-
-
WDT1 calibration
(trimming)
-
-
-
-
Reserved
-
-
-
Regulator control
-
Low-voltage
detection
Reserved
000574H
|
00057CH
000580H
REGSEL[R/W] B,H,W
01--110-
LVD[R/W]
LVD5R[R/W] B,H,W
LVD5F[R/W] B,H,W
-------1
001100-1
-
-
-
-
PMUSTR [R/W]
B,H,W
PMUCTLR[R/W]
B,H,W
PWRTMCTL[R/W]
B,H,W
-
0-----1X
0-00----
-----011
000594H
-
PMUINTF1[R/W]
B,H,W
PMUINTF2[R/W]
B,H,W
00000000
-00-----
000598H
-
-
-
-
00059CH
-
-
-
-
-
-
-
-
Reserved
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
000584H
B,H,W
01000--0
000588H
|
00058CH
000590H
-
PMU
0005A0H
|
0005FCH
000600H
|
00060CH
000610H
|
00063CH
000640H
|
00064CH
000650H
|
00067CH
000680H
|
00068CH
000690H
|
0006BCH
Document Number: 002-04665 Rev *A
Page 50 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
0006C0H
|
-
-
-
-
Reserved [S]
-
-
-
-
Reserved
0006CCH
0006D0H
|
0006F0H
0006F4H
-
Reserved
0006F8H
|
-
-
-
-
Reserved
0006FCH
000700H
-
Reserved
000704H
|
-
-
-
BPCCRA[R/W] B
BPCCRB[R/W] B
BPCCRC[R/W] B
00000000
00000000
00000000
-
Reserved
00070CH
000710H
000714H
000718H
00071CH
-
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
Bus performance
counter
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
000720H
|
-
-
-
-
Reserved
-
-
-
Operation mode
-
-
-
Reserved [S]
FSTR[R/W] B
-----001
Flash memory
register [S]
0007F8H
0007FCH
BMODR[R] B,H,W
XXXXXXXX
000800H
|
-
00083CH
000840H
000844H
FCTLR[R/W] H
-
-0--1000 0--0----
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
-
-
000848H
|
000854H
000858H
WREN[R/W] H
Wild register [S]
00000000 00000000
00085CH
|
-
-
Reserved [S]
00087CH
Document Number: 002-04665 Rev *A
Page 51 of 175
MB91580M/S Series
Address
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
Address offset value/Register name
+0
+1
+2
+3
Block
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
Wild register [S]
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04665 Rev *A
Page 52 of 175
MB91580M/S Series
Address offset value/Register name
Address
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
0008E4H
0008E8H
0008ECH
0008F0H
0008F4H
0008F8H
0008FCH
+0
+1
+2
Block
+3
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild register [S]
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
|
-
-
-
-
Reserved
000BF8H
000BFCH
-
Document Number: 002-04665 Rev *A
UER[W] B,H,W
-------- -------X
OCDU
Page 53 of 175
MB91580M/S Series
Address
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
Address offset value/Register name
+0
+1
+2
+3
Block
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H
DTCR0[R/W] H
0------- -----000
00000000 00000000
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H
DTCR1[R/W] H
0------- -----000
00000000 00000000
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H
DTCR2[R/W] H
0------- -----000
00000000 00000000
DMA controller [S]
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H
DTCR3[R/W] H
0------- -----000
00000000 00000000
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H
DTCR4[R/W] H
0------- -----000
00000000 00000000
Document Number: 002-04665 Rev *A
Page 54 of 175
MB91580M/S Series
Address offset value/Register name
Address
000C48H
000C4CH
000C50H
000C54H
000C58H
000C5CH
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
+0
+1
+2
+3
Block
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H
DTCR5[R/W] H
0------- -----000
00000000 00000000
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H
DTCR6[R/W] H
0------- -----000
00000000 00000000
DSAR6[R/W] W
DMA controller [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H
DTCR7[R/W] H
0------- -----000
00000000 00000000
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80H
|
-
-
-
-
-
-
DNMIR[R/W] B
DILVR[R/W] B
0------0
---11111
000DF0H
000DF4H
000DF8H
000DFCH
000E00H
000E04H
000E08H
000E0CH
DMACR[R/W] W
0------- -------- 0------- --------
-
-
-
DDR00[R/W] B,H
DDR01[R/W] B,H
DDR02[R/W] B,H
DDR03[R/W] B,H
00000000
00000000
00000000
00000000
DDR04[R/W] B,H
DDR05[R/W] B,H
DDR06[R/W] B,H
DDR07[R/W] B,H
00000000
-0000000
-0000000
-----000
DDR08[R/W] B,H
DDR09[R/W] B,H
DDR10[R/W] B,H
00000000
00000000
-----000
-
-
-
Document Number: 002-04665 Rev *A
Reserved [S]
Data direction
register
-
Page 55 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000E10H
|
-
-
-
-
PFR00[R/W] B,H
PFR01[R/W] B,H
PFR02[R/W] B,H
PFR03[R/W] B,H
00000000
00000000
00000000
00000000
PFR04[R/W] B,H
PFR05[R/W] B,H
PFR06[R/W] B,H
PFR07[R/W] B,H
00000000
-0000000
-0000000
-----000
PFR08[R/W] B,H
PFR09[R/W] B,H
PFR10[R/W] B,H
00000000
00000000
-----000
-
-
-
-
-
-
-
-
PDDR00[R] B,H,W
PDDR01[R] B,H,W
PDDR02[R] B,H,W
PDDR03[R] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDDR04[R] B,H,W
PDDR05[R] B,H,W
PDDR06[R] B,H,W
PDDR07[R] B,H,W
XXXXXXXX
-XXXXXXX
-XXXXXXX
-----XXX
PDDR08[R] B,H,W
PDDR09[R] B,H,W
PDDR10[R] B,H,W
XXXXXXXX
XXXXXXXX
-----XXX
-
-
-
-
-
-
-
-
EPFR00[R/W] B,H
EPFR01[R/W] B,H
EPFR02[R/W] B,H
EPFR03[R/W] B,H
------00
---00000
--000000
--000000
EPFR06[R/W] B,H
EPFR07[R/W] B,H
------00
----0000
Reserved
000E1CH
000E20H
000E24H
000E28H
000E2CH
Port function
register
-
000E30H
|
Reserved
000E3CH
000E40H
000E44H
000E48H
000E4CH
Input data direct
read register
-
000E50H
|
Reserved
000E5CH
000E60H
000E64H
-
-
000E68H
EPFR08[R/W]
B,H *5
EPFR09[R/W] B,H
EPFR10[R/W] B,H
-------0
-0000000
----0000
EPFR14[R/W] B,H
-
000E6CH
-
-
000E70H
-
-
-
-
000E74H
-
-
-
-
000E78H
-
-
-
-
000E7CH
-
-
-
-
000E80H
-
-
-
-
-
-
-
-
--0-0-0-
-
Extended port
function register
000E84H
|
Reserved
000EBCH
Document Number: 002-04665 Rev *A
Page 56 of 175
MB91580M/S Series
Address offset value/Register name
Address
000EC0H
000EC4H
000EC8H
000ECCH
+0
+1
PPER00[R/W] B,H
PPER01[R/W] B,H
00000000
PPER04[R/W] B,H
+2
+3
Block
PPER02[R/W] B,H
PPER03[R/W] B,H
00000000
00000000
00000000
PPER05[R/W] B,H
PPER06[R/W] B,H
PPER07[R/W] B,H
00000000
-0000000
-0000000
-----000
PPER08[R/W] B,H
PPER09[R/W] B,H
PPER10[R/W] B,H
00000000
00000000
-----000
-
-
-
-
-
-
-
-
PILR00[R/W] B,H
PILR01[R/W] B,H
PILR02[R/W] B,H
PILR03[R/W] B,H
11111111
11111111
11111111
11111111
PILR04[R/W] B,H
PILR05[R/W] B,H
PILR06[R/W] B,H
PILR07[R/W] B,H
11111111
-1111111
-1111111
-----111
PILR08[R/W] B,H
PILR09[R/W] B,H
PILR10[R/W] B,H
11111111
11111111
-----111
-
-
-
-
-
-
-
-
Reserved
-
-
-
-
Reserved
PODR00[R/W] B,H
PODR01[R/W] B,H
PODR02[R/W] B,H
PODR03[R/W] B,H
00000000
00000000
00000000
00000000
PODR04[R/W] B,H
PODR05[R/W] B,H
PODR06[R/W] B,H
PODR07[R/W] B,H
00000000
-0000000
-0000000
-----000
PODR08[R/W] B,H
PODR09[R/W] B,H
PODR10[R/W] B,H
00000000
00000000
-----000
-
-
-
-
-
-
-
-
Reserved
-
-
-
Port input enable
register
-
-
Port key code
Port pull-up/down
enable register
-
000ED0H
|
Reserved
000EDCH
000EE0H
000EE4H
000EE8H
000EECH
Port input level
selection register
-
000EF0H
|
000EFCH
000F00H
|
000F1CH
000F20H
000F24H
000F28H
000F2CH
Port output drive
register
-
000F30H
|
000F3CH
000F40H
000F44H
000F48H
000F4CH
PORTEN[R/W] B,H,W
------00
KEYCDR[R/W] H
00000000 00000000
ADERH[R/W] B,H
ADERL[R/W] B,H
-------- 11111111
-1111111 11111111
DAER[R/W] B,H
-------0
-
Document Number: 002-04665 Rev *A
-
Analog input
enable register
-
Analog output
enable register
Page 57 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000F50H
|
-
-
-
-
Reserved
-
-
Synchronous/asyn
chronous switch
control
-
Reserved
000FFCH
001000H
SACR[R/W] B,H,W
-------0
PICD[R/W]
B,H,W
----0011
001004H
|
-
-
-
-
-
-
0010BCH
0010C0H
0010C4H
0010C8H
0010CCH
0010D0H
0010D4H
0010D8H
0010DCH
CRCCR[R/W] B,H,W
-0000000
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
CRC arithmetic
operation 0
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
-
-
-
CRCCR1[R/W] B,H,W
-0000000
CRCINIT1[R/W] B,H,W
11111111 11111111 11111111 11111111
CRC arithmetic
operation 1
CRCIN1[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR1[R] B,H,W
11111111 11111111 11111111 11111111
0010E0H
|
-
-
-
-
-
-
Reserved
TCGSE[R/W] B,H,W
Free-run timer
simultaneous
activation
0010FCH
001100H
001104H
001108H
00110CH
001110H
001114H
001118H
TCGS[R/W] B,H,W
------00
CPCLRB0/CPCLR0[R/W] H,W
TCDT0[R/W] H,W
11111111 11111111
00000000 00000000
TCCS0[R/W] B,H,W
--000000
Free-run timer 0
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1[R/W] H,W
TCDT1[R/W] H,W
11111111 11111111
00000000 00000000
TCCS1[R/W] B,H,W
Free-run timer 1
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2[R/W] H,W
TCDT2[R/W] H,W
11111111 11111111
00000000 00000000
TCCS2[R/W] B,H,W
Free-run timer 2
00000000 01000000 ----0000 --------
Document Number: 002-04665 Rev *A
Page 58 of 175
MB91580M/S Series
Address offset value/Register name
Address
00111CH
001120H
001124H
001128H
00112CH
001130H
001134H
001138H
00113CH
001140H
001144H
001148H
00114CH
001150H
001154H
001158H
00115CH
001160H
001164H
001168H
+0
+1
+2
CPCLRB3/CPCLR3[R/W] H,W
TCDT3[R/W] H,W
11111111 11111111
00000000 00000000
+3
Block
Free-run timer 3
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB4/CPCLR4[R/W] H,W
TCDT4[R/W] H,W
11111111 11111111
00000000 00000000
Free-run timer 4
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB5/CPCLR5[R/W] H,W
TCDT5[R/W] H,W
11111111 11111111
00000000 00000000
Free-run timer 5
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 -------FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
-
Free-run timer
selection
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS5[R/W] B,H,W
-----000 -000-000 -000-000 -000-000
FRS6[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
OCCPB0/OCCP0[R/W] H,W
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
00000000 00000000
OCS01[R/W] B,H,W
-110--00 00001100
-
OCMOD01[R/W]
B,H,W
------00
OCCPB2/OCCP2[R/W] H,W
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
00000000 00000000
OCS23[R/W] B,H,W
-110--00 00001100
-
OCMOD23[R/W]
B,H,W
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
00000000 00000000
-110--00 00001100
Document Number: 002-04665 Rev *A
Output compare
2/3
------00
OCCPB4/OCCP4[R/W] H,W
OCS45[R/W] B,H,W
Output compare
0/1
-
OCMOD45[R/W]
B,H,W
Output compare
4/5
------00
Page 59 of 175
MB91580M/S Series
Address offset value/Register name
Address
00116CH
001170H
001174H
001178H
00117CH
001180H
001184H
001188H
00118CH
001190H
+0
+1
+2
OCCPB6/OCCP6[R/W] H,W
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
00000000 00000000
OCS67[R/W] B,H,W
-
-110--00 00001100
OCMOD67[R/W]
B,H,W
OCCPB9/OCCP9[R/W] H,W
00000000 00000000
00000000 00000000
OCS89[R/W] B,H,W
-
-110--00 00001100
OCMOD89[R/W]
B,H,W
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
00000000 00000000
OCS1011[R/W] B,H,W
-
-110--00 00001100
OCMOD1011
[R/W] B,H,W
IPCP1[R] H,W
00000000 00000000
00000000 00000000
ICS01[R/W] B,H,W
-
------00 00000000
IPCP2[R] H,W
IPCP3[R] H,W
00000000 00000000
00000000 00000000
ICS23[R/W] B,H,W
-
------00 00000000
LSYNS[R/W] B,H,W
Input capture 2/3
-
-
-
-
-
00119CH
-
-
0011A0H
-
-
-
-
-
0011ACH
0011B0H
TMRR0[R/W] H,W
TMRR1[R/W] H,W
00000000 00000001
00000000 00000001
TMRR2[R/W] H,W
-
00000000 00000001
DTSCR0[R/W] B,H,W DTSCR1[R/W] B,H,W DTSCR2[R/W] B,H,W
00000000
0011B4H
-
0011B8H
-
0011BCH
-
00000000
DTIR0[R/W] B,H,W
000000-SIGCR10[R/W] B,H,W
00000000
00000000
-
Input capture 0/1
----0000
001198H
0011A8H
Output compare
10/11
------00
IPCP0[R] H,W
------10
Output compare
8/9
------00
OCCPB10/OCCP10[R/W] H,W
DTSR[R/W] B,H,W
Output compare
6/7
------00
OCCPB8/OCCP8[R/W] H,W
001194H
0011A4H
Block
+3
-
Reserved
Reserved
DTTI selection
DTMNS0[R/W] B,H,W
Waveform
generator
0/1/2
00---000
SIGCR20[R/W] B,H,W
000000-1
PICS0[R/W] B,H,W
000000-- -------- -------- --------
Document Number: 002-04665 Rev *A
Page 60 of 175
MB91580M/S Series
Address offset value/Register name
Address
0011C0H
0011C4H
0011C8H
0011CCH
+0
TMRR4[R/W] H,W
00000000 00000001
00000000 00000001
TMRR5[R/W] H,W
00000000
-
-
0011D8H
-
0011E8H
0011ECH
0011F0H
0011F4H
0011F8H
0011FCH
001200H
001204H
001208H
00120CH
001210H
001214H
ADTSS[R/W] B,H,W
-------0
Block
+3
-
Waveform
generator
3/4/5
DTSCR3[R/W] B,H,W DTSCR4[R/W] B,H,W DTSCR5[R/W] B,H,W
0011D4H
0011E4H
-
00000000 00000001
-
0011E0H
+2
TMRR3[R/W] H,W
0011D0H
0011DCH
+1
00000000
DTIR1[R/W] B,H,W
000000-SIGCR11[R/W] B,H,W
00000000
00000000
-
DTMNS1[R/W] B,H,W
00---000
Waveform
SIGCR21[R/W] B,H,W generator
3/4/5
-------1
-
-
-
-
-
-
ADTSE[R/W] B,H,W
-------- 00000000 -0000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
-
ADCOMP16/ADCOMPB16[R/W] H,W
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP18/ADCOMPB18[R/W] H,W
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP22/ADCOMPB22[R/W] H,W
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
-
12-bit A/D
converter
00000000 00000000
-
Document Number: 002-04665 Rev *A
-
-
Page 61 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
001218H
-
-
-
-
00121CH
-
-
-
-
001220H
-
-
-
-
001224H
001228H
00122CH
001230H
001234H
001238H
00123CH
001240H
001244H
001248H
00124CH
001250H
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS8[R/W] B,H,W
ADTCS9[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS10[R/W] B,H,W
ADTCS11[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS12[R/W] B,H,W
ADTCS13[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS14[R/W] B,H,W
-
00000000 0010-000
ADTCS16[R/W] B,H,W
ADTCS17[R/W] B,H,W
00000000 00100000
00000000 00100000
ADTCS18[R/W] B,H,W
ADTCS19[R/W] B,H,W
00000000 00100000
00000000 00100000
ADTCS20[R/W] B,H,W
ADTCS21[R/W] B,H,W
00000000 00100000
00000000 00100000
ADTCS22[R/W] B,H,W
ADTCS23[R/W] B,H,W
00000000 00100000
12-bit A/D
converter
00000000 00100000
001254H
-
-
-
-
001258H
-
-
-
-
00125CH
-
-
-
-
001260H
-
-
-
-
001264H
001268H
00126CH
001270H
001274H
Block
ADTCD0[R] B,H,W
ADTCD1[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD2[R] B,H,W
ADTCD3[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD4[R] B,H,W
ADTCD5[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD6[R] B,H,W
ADTCD7[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD8[R] B,H,W
ADTCD9[R] B,H,W
10--0000 00000000
10--0000 00000000
Document Number: 002-04665 Rev *A
Page 62 of 175
MB91580M/S Series
Address offset value/Register name
Address
001278H
00127CH
001280H
001284H
001288H
00128CH
001290H
+0
+1
+2
ADTCD10[R] B,H,W
ADTCD11[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD12[R] B,H,W
ADTCD13[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD14[R] B,H,W
+3
-
10--0000 00000000
ADTCD16[R] B,H,W
ADTCD17[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD18[R] B,H,W
ADTCD19[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD20[R] B,H,W
ADTCD21[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD22[R] B,H,W
ADTCD23[R] B,H,W
10--0000 00000000
12-bit A/D
converter
10--0000 00000000
001294H
-
-
-
-
001298H
-
-
-
-
00129CH
-
-
-
-
0012A0H
-
-
0012A4H
0012A8H
0012ACH
0012B0H
-
-
ADCS0[R/W] B,H,W
ADCH0[R] B,H,W
ADMD0[R/W] B,H,W
0------- --------
-----000
----0000
ADCS1[R/W] B,H,W
ADCH1[R] B,H,W
ADMD1[R/W] B,H,W
0------- --------
-----000
----0000
ADCS2[R/W] B,H,W
ADCH2[R] B,H,W
ADMD2[R/W] B,H,W
0------- --------
-----000
----0000
-
-
MTRCSR[R/W] B,H,W
-------0
-
RTOSEL0[R/W]
B,H,W
RTOSEL1[R/W]
B,H,W
--000000
-------0
-
001300H
Motor control
extension function
-
-
-
-
-
-
-
-
-
001304H
-
-
-
-
001308H
-
-
-
-
00130CH
-
-
-
-
001310H
-
-
-
-
001314H
-
-
-
-
001318H
-
-
-
-
00131CH
-
-
-
-
001320H
-
-
-
-
001324H
-
0012B4H
Block
0012B8H
|
Reserved
0012FCH
Document Number: 002-04665 Rev *A
Reserved
-
Page 63 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
Block
+3
001328H
|
-
-
-
-
Reserved
00132CH
001330H
-
-
001334H
|
-
-
-
-
Reserved
0013FCH
001400H
DACR[R/W] B,H,W
-------0
-
DADR[R/W] H,W
DAC
------XX XXXXXXXX
001404H
|
-
-
SCR0/(IBCR0)
[R/W] B,H,W
SMR0[R/W] B,H,W
-
-
Reserved
SSR0[R/W]
B,H,W
ESCR0/(IBSR0)
[R/W] B,H,W
0--00011
00000000
0014FCH
001500H
0--00000
001504H
001508H
00150CH
001510H
000000-0
-/(RDR10/(TDR10))[R/W] B,H,W
RDR00/(TDR00)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR0[R/W] B,H,W
STMR0[R] B,H,W
0----000 00000000
00000000 00000000
STMCR0[R/W] B,H,W
-/(SFUR0) [R/W] B,H,W
00000000 00000000
-------- -------- *4
-
-
-/(SFLR10) [R/W]
B,H,W
--------
*4
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C mode
is not set
immediately after
reset
-/(SFLR00) [R/W]
B,H,W
--------
*4
001514H
-
-
-
-
001518H
-
-
-
-
00000000
00151CH
001520H
Multi Function
Serial I/F 0
*3: Reserved
because CSIO
mode is not set
immediately after
reset
FCR10[R/W] B,H,W
FCR00[R/W] B,H,W
*4: Reserved
-/(ISMK0)[R/W] B,H,W -/(ISBA0)[R/W] B,H,W because LIN2.1
mode is not set
-------- *2
-------- *2
immediately after
FBYTE20[R/W] B,H,W FBYTE10[R/W] B,H,W reset
00-00100
-0000000
00000000
BGR0[R/W] H,W
00000000 00000000
Document Number: 002-04665 Rev *A
Page 64 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
SCR1[R/W]
001524H
SMR1[R/W] B,H,W
B,H,W
000000-0
0--00000
001528H
00152CH
001530H
-/(RDR11/(TDR11))[R/W] B,H,W
-------- --------
*3
-/(SCSCR1/SFUR1) [R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
-
00153CH
-
-
BGR1[R/W] H,W
001554H
-
FCR11[R/W] B,H,W
FCR01[R/W] B,H,W
FBYTE21[R/W] B,H,W FBYTE11[R/W] B,H,W
00-00100
-0000000
00000000
00000000
SCR2/(IBCR2)
[R/W] B,H,W
SMR2[R/W] B,H,W
SSR2[R/W]
B,H,W
ESCR2/(IBSR2)
[R/W] B,H,W
0--00011
00000000
000000-0
-/(RDR12/(TDR12))[R/W] B,H,W
RDR02/(TDR02)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR2[R/W] B,H,W
STMR2[R] B,H,W
00000000 00000000
STMCR2[R/W] B,H,W
-/(SCSCR2/SFUR2) [R/W] B,H,W
-------- --------
*3 *4
-/(SCSTR32) [R/W]
B,H,W
-/(SCSTR22) [R/W]
B,H,W
-/(SCSTR12/
-/(SCSTR02/
SFLR12) [R/W] B,H,W SFLR02) [R/W] B,H,W
-------- *3
-------- *3
-------- *3 *4
-------- *3 *4
00155CH
-
-
-
-
001560H
-
-
-
001558H
Multi Function
Serial I/F 2
*1: Byte access is
possible only for
access to lower 8
bits.
0----000 00000000
00000000 00000000
*1: Byte access is
possible only for
access to lower 8
bits.
*3: Reserved
-/(SCSTR11/
-/(SCSTR01/
because CSIO
SFLR11) [R/W] B,H,W SFLR01) [R/W] B,H,W mode is not set
immediately after
-------- *3 *4
-------- *3 *4
reset
*4: Reserved
TBYTE01[R/W]
because LIN2.1
mode is not set
B,H,W
immediately after
00000000
reset
-
00000000 00000000
0--00000
001550H
Multi Function
Serial I/F 1
STMCR1[R/W] B,H,W
-
00154CH
RDR01/(TDR01)[R/W] B,H,W
00000000 00000000
001538H
001548H
00000000
0--00011
STMR1[R] B,H,W
-------- *3
Block
ESCR1[R/W] B,H,W
B,H,W
0----000 00000000
-------- *3
001544H
SSR1[R/W]
SACSR1[R/W] B,H,W
-/(SCSTR21) [R/W]
B,H,W
001540H
+3
-------0 00000000 *1
-/(SCSTR31) [R/W]
B,H,W
001534H
+2
TBYTE02[R/W]
*2: Reserved
because I2C mode
is not set
immediately after
reset
*3: Reserved
because CSIO
mode is not set
immediately after
reset
B,H,W
*4: Reserved
because LIN2.1
-/(ISMK2)[R/W] B,H,W -/(ISBA2)[R/W] B,H,W mode is not set
immediately after
-------- *2
-------- *2
reset
00000000
001564H
001568H
BGR2[R/W] H,W
00000000 00000000
FCR12[R/W] B,H,W
FCR02[R/W] B,H,W
FBYTE22[R/W] B,H,W FBYTE12[R/W] B,H,W
00-00100
-0000000
00000000
Document Number: 002-04665 Rev *A
00000000
Page 65 of 175
MB91580M/S Series
Address offset value/Register name
Address
00156CH
+0
SCR3/(IBCR3)
[R/W] B,H,W
0--00000
001570H
001574H
001578H
+1
SMR3[R/W] B,H,W
000000-0
+2
SSR3[R/W]
B,H,W
ESCR3/(IBSR3)
[R/W] B,H,W
0--00011
00000000
-/(RDR13/(TDR13))[R/W] B,H,W
RDR03/(TDR03)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR3[R/W] B,H,W
STMR3[R] B,H,W
0----000 00000000
00000000 00000000
STMCR3[R/W] B,H,W
-/(SCSCR3/SFUR3) [R/W] B,H,W
00000000 00000000
-------- --------
Multi Function
Serial I/F 3
*1: Byte access is
possible only for
access to lower 8
bits.
*3 *4
-/(SCSTR33) [R/W]
B,H,W
-/(SCSTR23) [R/W]
B,H,W
-/(SCSTR13/
-/(SCSTR03/
SFLR13) [R/W] B,H,W SFLR03) [R/W] B,H,W
-------- *3
-------- *3
-------- *3 *4
-------- *3 *4
001580H
-
-
-
-
001584H
-
-
-
00157CH
Block
+3
TBYTE03[R/W]
*2: Reserved
because I2C mode
is not set
immediately after
reset
*3: Reserved
because CSIO
mode is not set
immediately after
reset
B,H,W
*4: Reserved
because LIN2.1
-/(ISMK3)[R/W] B,H,W -/(ISBA3)[R/W] B,H,W mode is not set
immediately after
-------- *2
-------- *2
reset
00000000
001588H
00158CH
BGR3[R/W] H,W
00000000 00000000
FCR13[R/W] B,H,W
FCR03[R/W] B,H,W
FBYTE23[R/W] B,H,W FBYTE13[R/W] B,H,W
00-00100
-0000000
00000000
00000000
-
-
-
-
001590H
|
Reserved
001FFCH
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
CTRLR0[R/W] B,H,W
STATR0[R/W] B,H,W
-------- 000-0001
-------- 00000000
ERRCNT0 [R] B,H,W
BTR0[R/W] B,H,W
00000000 00000000
-0100011 00000001
INTR0[R] B,H,W
TESTR0[R/W] B,H,W
00000000 00000000
-------- X00000--
BRPER0[R/W] B,H,W
-------- ----0000
-
IF1CREQ0[R/W] B,H,W
IF1CMSK0[R/W] B,H,W
0------- 00000001
-------- 00000000
CAN 0
IF1MSK20[R/W] B,H,W
IF1MSK10[R/W] B,H,W
64msb
11-11111 11111111
11111111 11111111
IF1ARB20[R/W] B,H,W
IF1ARB10[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR0[R/W] B,H,W
00000000 0---0000
-
IF1DTA10[R/W] B,H,W
IF1DTA20[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB10[R/W] B,H,W
IF1DTB20[R/W] B,H,W
00000000 00000000
00000000 00000000
Document Number: 002-04665 Rev *A
Page 66 of 175
MB91580M/S Series
Address offset value/Register name
Address
002028H,
00202CH
002030H,
002034H
002038H,
00203CH
002040H
002044H
002048H
00204CH
002050H
002054H
002058H,
00205CH
002060H,
002064H
+0
-
+1
+2
-
Reserved (IF1 data mirror)
-
-
IF2CREQ0[R/W] B,H,W
IF2CMSK0[R/W] B,H,W
0------- 00000001
-------- 00000000
IF2MSK20[R/W] B,H,W
IF2MSK10[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF2ARB20[R/W] B,H,W
IF2ARB10[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2MCTR0[R/W] B,H,W
00000000 0---0000
-
IF2DTA10[R/W] B,H,W
IF2DTA20[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB10[R/W] B,H,W
IF2DTB20[R/W] B,H,W
00000000 00000000
00000000 00000000
-
-
Reserved (IF2 data mirror)
CAN 0
64msb
002068H
|
Block
+3
-
-
TREQR20[R] B,H,W
TREQR10[R] B,H,W
00000000 00000000
00000000 00000000
TREQR40[R] B,H,W
TREQR30[R] B,H,W
00000000 00000000
00000000 00000000
002088H
-
-
00208CH
-
-
NEWDT20[R] B,H,W
NEWDT10[R] B,H,W
00000000 00000000
00000000 00000000
NEWDT40[R] B,H,W
NEWDT30[R] B,H,W
00207CH
002080H
002084H
002090H
002094H
00000000 00000000
00000000 00000000
002098H
-
-
00209CH
-
-
INTPND20[R] B,H,W
INTPND10[R] B,H,W
00000000 00000000
00000000 00000000
INTPND40[R] B,H,W
INTPND30[R] B,H,W
00000000 00000000
00000000 00000000
0020A8H
-
-
0020ACH
-
-
0020A0H
0020A4H
Document Number: 002-04665 Rev *A
Page 67 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
MSGVAL20[R] B,H,W
MSGVAL10[R] B,H,W
00000000 00000000
00000000 00000000
MSGVAL40[R] B,H,W
MSGVAL30[R] B,H,W
00000000 00000000
00000000 00000000
0020B8H
-
-
0020BCH
-
-
-
-
0020B0H
0020B4H
Block
+3
CAN 0
64msb
0020C0H
|
0020FCH
002100H
002104H
002108H
00210CH
002110H
002114H
002118H
00211CH
002120H
002124H
002128H,
00212CH
002130H,
002134H
002138H,
00213CH
002140H
002144H
002148H
00214CH
CTRLR1[R/W] B,H,W
STATR1[R/W] B,H,W
-------- 000-0001
-------- 00000000
ERRCNT1 [R] B,H,W
BTR1[R/W] B,H,W
00000000 00000000
-0100011 00000001
INTR1[R] B,H,W
TESTR1[R/W] B,H,W
00000000 00000000
-------- X00000--
BRPER1[R/W] B,H,W
-------- ----0000
-
IF1CREQ1[R/W] B,H,W
IF1CMSK1[R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK21[R/W] B,H,W
IF1MSK11[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB21[R/W] B,H,W
IF1ARB11[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR1[R/W] B,H,W
00000000 0---0000
-
IF1DTA11[R/W] B,H,W
IF1DTA21[R/W] B,H,W
CAN 1
00000000 00000000
00000000 00000000
64msb
IF1DTB11[R/W] B,H,W
IF1DTB21[R/W] B,H,W
00000000 00000000
00000000 00000000
-
-
Reserved (IF1 data mirror)
-
-
IF2CREQ1[R/W] B,H,W
IF2CMSK1[R/W] B,H,W
0------- 00000001
-------- 00000000
IF2MSK21[R/W] B,H,W
IF2MSK11[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF2ARB21[R/W] B,H,W
IF2ARB11[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2MCTR1[R/W] B,H,W
00000000 0---0000
Document Number: 002-04665 Rev *A
-
Page 68 of 175
MB91580M/S Series
Address offset value/Register name
Address
002150H
002154H
002158H,
00215CH
002160H,
002164H
+0
+1
+2
IF2DTA11[R/W] B,H,W
IF2DTA21[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB11[R/W] B,H,W
IF2DTB21[R/W] B,H,W
00000000 00000000
00000000 00000000
-
-
Block
+3
Reserved (IF2 data mirror)
002168H
|
-
-
TREQR21[R] B,H,W
TREQR11[R] B,H,W
00000000 00000000
00000000 00000000
TREQR41[R] B,H,W
TREQR31[R] B,H,W
00000000 00000000
00000000 00000000
002188H
-
-
00218CH
-
-
NEWDT21[R] B,H,W
NEWDT11[R] B,H,W
00000000 00000000
00000000 00000000
NEWDT41[R] B,H,W
NEWDT31[R] B,H,W
00217CH
002180H
002184H
002190H
002194H
00000000 00000000
00000000 00000000
002198H
-
-
00219CH
-
-
INTPND21[R] B,H,W
INTPND11[R] B,H,W
00000000 00000000
00000000 00000000
INTPND41[R] B,H,W
INTPND31[R] B,H,W
00000000 00000000
00000000 00000000
0021A8H
-
-
0021ACH
-
-
MSGVAL21[R] B,H,W
MSGVAL11[R] B,H,W
00000000 00000000
00000000 00000000
MSGVAL41[R] B,H,W
MSGVAL31[R] B,H,W
00000000 00000000
00000000 00000000
0021B8H
-
-
0021BCH
-
-
-
-
-
-
0021A0H
0021A4H
0021B0H
0021B4H
CAN 1
64msb
0021C0H
|
0021FCH
002200H
|
Reserved
0022FCH
Document Number: 002-04665 Rev *A
Page 69 of 175
MB91580M/S Series
Address offset value/Register name
Address
002300H
+0
+1
DFCTLR[R/W] B,H,W
-
-0------ --------
002304H
-
002308H
FLIFCTLR[R/W]
B,H,W
+2
+3
DFSTR[R/W] B,H,W
-----001
-
-
-
-
FLIFFER1[R/W]
B,H,W
FLIFFER2[R/W]
B,H,W
--------
--------
-
-
---0--00
Block
WorkFlash
00230CH
|
-
-
Reserved
002FFCH
003000H
003004H
003008H
00300CH
003010H
003014H
003018H
00301CH
003020H
003024H
003028H
00302CH
SEEARX[R] B,H,W
DEEARX[R] B,H,W
--000000 00000000
--000000 00000000
EECSRX[R/W] B,H,W
EFEARX[R/W] B,H,W
----00-0
-
-
XBS RAM
ECC control
register
--000000 00000000
EFECRX[R/W] B,H,W
-------0 00000000 00000000
TEAR0X[R] B,H,W
000----- -------- --000000 00000000
TEAR1X[R] B,H,W
000----- -------- --000000 00000000
TEAR2X[R] B,H,W
000----- -------- --000000 00000000
XBS RAM
TAEARX[R/W] B,H,W
TASARX[R/W] B,H,W
--101111 11111111
--000000 00000000
TFECRX[R/W] B,H,W TICRX[R/W] B,H,W
TTCRX[R/W] B,H,W
----0000
----0000
------00 00001100
-
-
TSRCRX[R/W] B,H,W
0------SEEARA[R] B,H,W
DEEARA[R] B,H,W
--000000 00000000
--000000 00000000
EECSRA[R/W] B,H,W
----00-0
-
-
EFEARA[R/W] B,H,W
--000000 00000000
diagnosis register
TKCCRX[R/W] B,H,W
00----00
Backup RAM
ECC control
register
EFECRA[R/W] B,H,W
-------0 00000000 00000000
Document Number: 002-04665 Rev *A
Page 70 of 175
MB91580M/S Series
Address offset value/Register name
Address
003030H
003034H
003038H
00303CH
003040H
003044H
+0
+1
+2
+3
Block
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
Backup RAM
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
-----111 11111111
-----000 00000000
TFECRA[R/W] B,H,W TICRA[R/W] B,H,W
TTCRA[R/W] B,H,W
----0000
----0000
------00 00001100
-
-
-
-
TSRCRA[R/W] B,H,W
0-------
diagnosis register
TKCCRA[R/W] B,H,W
00----00
003048H
|
-
-
Reserved
0030FCH
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
003124H
BUSDIGSR0[R/W] H,W
BUSDIGSR1[R/W] H,W
00000000 0-----00
00000000 0-----00
BUSDIGSR2[R/W] H,W
BUSTSTR0[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR0[R] W
00000000 00000000 00000000 00000000
BUSADR1[R] W
00000000 00000000 00000000 00000000
Bus diagnosis
BUSADR2[R] W
00000000 00000000 00000000 00000000
BUSDIGSR3[R/W] H,W
-
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR3[R] W
00000000 00000000 00000000 00000000
BUSADR4[R] W
Bus diagnosis
00000000 00000000 00000000 00000000
003128H
|
-
-
-
-
Reserved
003FFCH
004000H
|
Backup RAM
Backup RAM area
005FFCH
006000H
|
-
-
-
-
Reserved
00CFFCH
Document Number: 002-04665 Rev *A
Page 71 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D000H
00D004H
+0
+1
+2
Block
+3
CIF0[R] W
00000100 11111111 01011011 11111111
FlexRay
CIF1[R/W] W
CIF *5
00000000 -------0 -0000000 --------
00D008H
|
-
-
-
-
-
-
-
Reserved
00D00CH
00D010H
-
00D014H
-
00D018H
-
00D01CH
00D020H
00D024H
00D028H
00D02CH
00D030H
00D034H
00D038H
00D03CH
00D040H
00D044H
00D048H
00D04CH
00D050H
LCK[R/W] W
FlexRay
GIF *5
-------- -------- -------- 00000000
EIR[R/W] W
-----000 -----000 ----0000 00000000
SIR[R/W] W
------00 ------00 00000000 00000000
EILS[R/W] W
-----000 -----000 ----0000 00000000
SILS[R/W] W
------11 ------11 11111111 11111111
EIES[R/W] W
-----000 -----000 ----0000 00000000
EIER[R/W] W
-----000 -----000 ----0000 00000000
SIES[R/W] W
FlexRay
------00 ------00 00000000 00000000
INT *5
SIER[R/W] W
------00 ------00 00000000 00000000
ILE[R/W] W
-------- -------- -------- ------00
T0C[R/W] W
--000000 00000000 -0000000 ------00
T1C[R/W] W
--000000 00000010 -------- ------00
STPW1[R/W] W
--000000 00000000 --000000 -0000000
STPW2[R] W
-----000 00000000 -----000 00000000
00D054H
|
-
-
-
-
Reserved
00D07CH
Document Number: 002-04665 Rev *A
Page 72 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D080H
00D084H
00D088H
00D08CH
00D090H
00D094H
00D098H
00D09CH
00D0A0H
00D0A4H
00D0A8H
00D0ACH
00D0B0H
00D0B4H
00D0B8H
00D0BCH
00D0C0H
00D0C4H
00D0C8H
+0
+1
+2
Block
+3
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
SUCC2[R/W] W
FlexRay
----0001 ---00000 00000101 00000100
SUC *5
SUCC3[R/W] W
-------- -------- -------- 00010001
NEMC[R/W] W
FlexRay
-------- -------- -------- ----0000
NEM *5
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
FlexRay
PRTC2[R/W] W
PRT *5
--001111 00101101 --001010 --001110
MHDC[R/W] W
FlexRay
---00000 00000000 -------- -0000000
MHD *5
-
Reserved
GTUC1[R/W] W
-------- ----0000 00000010 10000000
GTUC2[R/W] W
-------- ----0010 --000000 00001010
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
GTUC4[R/W] W
--000000 00001000 --000000 00000111
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
GTUC6[R/W] W
FlexRay
-----000 00000010 -----000 00000000
GTU *5
GTUC7[R/W] W
------00 00000010 ------00 00000100
GTUC8[R/W] W
---00000 00000000 -------- --000010
GTUC9[R/W] W
-------- ------00 ---00001 --000001
GTUC10[R/W] W
-----000 00000010 --000000 00000101
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0CCH
|
-
Reserved
00D0FCH
Document Number: 002-04665 Rev *A
Page 73 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D100H
00D104H
00D108H
00D10CH
00D110H
00D114H
00D118H
00D11CH
00D120H
00D124H
00D128H
00D12CH
00D130H
00D134H
00D138H
00D13CH
00D140H
00D144H
00D148H
00D14CH
00D150H
00D154H
00D158H
+0
+1
+2
+3
Block
CCSV[R] W
--000000 00010000 -100--00 00000000
FlexRay
CCEV[R] W
SUC *5
-------- -------- ---00000 00--0000
-
Reserved
SCV[R] W
-----000 00000000 -----000 00000000
MTCCV[R] W
-------- --000000 --000000 00000000
FlexRay
RCV[R] W
GTU *5
-------- -------- ----0000 00000000
OCV[R] W
-------- -----000 00000000 00000000
SFS[R] W
-------- ----0000 00000000 00000000
SWNIT[R] W
-------- -------- ----0000 00000000
ACS[R/W] W
-------- -------- ---00000 ---00000
ESID1[R] W
-------- -------- 00----00 00000000
ESID2[R] W
-------- -------- 00----00 00000000
ESID3[R] W
-------- -------- 00----00 00000000
ESID4[R] W
-------- -------- 00----00 00000000
ESID5[R] W
FlexRay
GTU *5
-------- -------- 00----00 00000000
ESID6[R] W
-------- -------- 00----00 00000000
ESID7[R] W
-------- -------- 00----00 00000000
ESID8[R] W
-------- -------- 00----00 00000000
ESID9[R] W
-------- -------- 00----00 00000000
ESID10[R] W
-------- -------- 00----00 00000000
ESID11[R] W
-------- -------- 00----00 00000000
Document Number: 002-04665 Rev *A
Page 74 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D15CH
00D160H
00D164H
00D168H
00D16CH
00D170H
00D174H
00D178H
00D17CH
00D180H
00D184H
00D188H
00D18CH
00D190H
00D194H
00D198H
00D19CH
00D1A0H
00D1A4H
00D1A8H
00D1ACH
+0
+1
+2
+3
Block
ESID12[R] W
-------- -------- 00----00 00000000
ESID13[R] W
-------- -------- 00----00 00000000
ESID14[R] W
-------- -------- 00----00 00000000
ESID15[R] W
-------- -------- 00----00 00000000
OSID1[R] W
-------- -------- 00----00 00000000
OSID2[R] W
-------- -------- 00----00 00000000
OSID3[R] W
-------- -------- 00----00 00000000
OSID4[R] W
-------- -------- 00----00 00000000
OSID5[R] W
-------- -------- 00----00 00000000
OSID6[R] W
-------- -------- 00----00 00000000
FlexRay
GTU *5
OSID7[R] W
-------- -------- 00----00 00000000
OSID8[R] W
-------- -------- 00----00 00000000
OSID9[R] W
-------- -------- 00----00 00000000
OSID10[R] W
-------- -------- 00----00 00000000
OSID11[R] W
-------- -------- 00----00 00000000
OSID12[R] W
-------- -------- 00----00 00000000
OSID13[R] W
-------- -------- 00----00 00000000
OSID14[R] W
-------- -------- 00----00 00000000
OSID15[R] W
-------- -------- 00----00 00000000
-
Document Number: 002-04665 Rev *A
Reserved
Page 75 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D1B0H
00D1B4H
00D1B8H
+0
+1
+2
+3
Block
NMV1[R] W
00000000 00000000 00000000 00000000
NMV2[R] W
FlexRay
00000000 00000000 00000000 00000000
NEM *5
NMV3[R] W
00000000 00000000 00000000 00000000
00D1BCH
|
-
Reserved
00D2FCH
00D300H
00D304H
00D308H
00D30CH
00D310H
00D314H
00D318H
00D31CH
00D320H
00D324H
00D328H
00D32CH
00D330H
00D334H
00D338H
MRC[R/W] W
-----001 10000000 00000000 00000000
FRF[R/W] W
-------1 10000000 ---00000 00000000
FRFM[R/W] W
-------- -------- ---00000 000000-FCL[R/W] W
-------- -------- -------- 10000000
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
LDTS[R] W
-----000 00000000 -----000 00000000
FSR[R] W
-------- -------- 00000000 -----000
MHDF[R/W] W
FlexRay
-------- -------- -------0 00000000
MHD *5
TXRQ1[R] W
00000000 00000000 00000000 00000000
TXRQ2[R] W
00000000 00000000 00000000 00000000
TXRQ3[R] W
00000000 00000000 00000000 00000000
TXRQ4[R] W
00000000 00000000 00000000 00000000
NDAT1[R] W
00000000 00000000 00000000 00000000
NDAT2[R] W
00000000 00000000 00000000 00000000
NDAT3[R] W
00000000 00000000 00000000 00000000
Document Number: 002-04665 Rev *A
Page 76 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D33CH
00D340H
00D344H
00D348H
00D34CH
+0
+1
+2
Block
+3
NDAT4[R] W
00000000 00000000 00000000 00000000
MBSC1[R] W
00000000 00000000 00000000 00000000
MBSC2[R] W
FlexRay
00000000 00000000 00000000 00000000
MHD *5
MBSC3[R] W
00000000 00000000 00000000 00000000
MBSC4[R] W
00000000 00000000 00000000 00000000
00D350H
|
-
Reserved
00D3ECH
00D3F0H
00D3F4H
CREL[R] W
00010000 00111001 00000010 00000110
FlexRay
ENDN[R] W
GIF *5
10000111 01100101 01000011 00100001
00D3F8H
|
-
Reserved
00D3FCH
00D400H
|
00D4FCH
00D500H
00D504H
00D508H
00D50CH
00D510H
00D514H
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
WRHS2[R/W] W
-------- -0000000 -----000 00000000
FlexRay
WRHS3[R/W] W
IBF *5
-------- -------- -----000 00000000
IBCM[R/W] W
-------- ------00 -------- -----000
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D518H
|
-
Reserved
00D5FCH
Document Number: 002-04665 Rev *A
Page 77 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D600H
|
00D6FCH
00D700H
00D704H
00D708H
00D70CH
00D710H
00D714H
+0
+1
+2
Block
+3
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
RDHS1[R] W
--000000 -0000000 -----000 00000000
RDHS2[R] W
-0000000 -0000000 -----000 00000000
FlexRay
RDHS3[R] W
OBF *5
--000000 --000000 -----000 00000000
MBS[R] W
--000000 --000000 00-00000 00000000
OBCM[R/W] W
-------- ------00 -------- ------00
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D718H
|
-
Reserved
-
Reserved
-
Reserved [S]
00D7FCH
00D800H
|
00EFFCH
00F000H
|
00FEFCH
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
-
-
OCDU [S]
-
-
Reserved [S]
00FF04H
|
-
-
00FF0CH
00FF10H
00FF14H
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
|
-
-
-
-
Reserved [S]
00FFF4H
00FFF8H
00FFFCH
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDIR0[R] B,H,W
OCDU [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]:
It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
*5:
For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ has corresponding
functions.
Document Number: 002-04665 Rev *A
Page 78 of 175
MB91580M/S Series
The following registers are reserved registers for models without the FlexRay function.
000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H
Document Number: 002-04665 Rev *A
Page 79 of 175
MB91580M/S Series
I/O Map (MB91F583AS/F584AS/F585AS)
Address offset value/Register name
Address
000000H
000004H
+0
-
+1
PDR02[R/W] B,H,W
PDR03[R/W] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR05[R/W] B,H,W
XXXXXXXX
-XXXXXXX
-
00000CH
-
+3
PDR01[R/W] B,H,W
PDR04[R/W] B,H,W
000008H
+2
PDR09[R/W] B,H,W
-
PDR07[R/W] B,H,W
-----XXX
-
-
-
-
-
-
-
-
-
WDTCR0[R/W]
WDTCPR0[W]
WDTCR1[R]
WDTCPR1[W]
B,H,W
B,H,W
B,H,W
B,H,W
-0--0000
00000000
----0010
00000000
-
-
-
-
-
---XX---
Block
Port data register
000010H
|
Reserved
000038H
00003CH
000040H
000044H
DICR[R/W] B
-------0
Watchdog timer [S]
Reserved
-
Delay interrupt
000048H
|
-
-
Reserved
TMRLRA0[R/W] H
TMR0[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB0[R/W] H
TMCSR0[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
-
-
00005CH
000060H
000064H
Reload timer 0
000068H
|
-
-
Reserved
00007CH
000080H
000084H
000088H
BT0TMR[R] H
BT0TMCR[R/W] H
00000000 00000000
-0000000 00000000
BT0TMCR2
BT0STC
[R/W] B
[R/W] B
-------0
-0-0-0-0
Base timer 0
BT0PCSR/BT0PRLL
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
[R/W] H
00000000 00000000
00008CH
-
-
00000000 00000000
-
Document Number: 002-04665 Rev *A
-
-
Page 80 of 175
MB91580M/S Series
Address offset value/Register name
Address
000090H
000094H
000098H
00009CH
+0
+1
BT1TMR[R] H
+2
+3
BT1TMCR[R/W] H
00000000 00000000
-0000000 00000000
BT1TMCR2
BT1STC
[R/W] B
[R/W] B
-------0
-0-0-0-0
-
-
BT1PCSR/BT1PRLL
BT1PDUT/BT1PRLH/BT1DTBF
[R/W] H
[R/W] H
00000000 00000000
00000000 00000000
BTSEL01[R/W] B
----0000
Block
-
BTSSSR[W] B,H
Base timer 1
Base timer 0, 1
-------- ------11
0000A0H
|
-
-
-
-
Reserved
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
TMRLRA1[R/W] H
TMR1[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB1[R/W] H
TMCSR1[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA2[R/W] H
TMR2[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB2[R/W] H
TMCSR2[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
TMRLRA3[R/W] H
TMR3[R] H
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMRLRB3[R/W] H
TMCSR3[R/W] B,H,W
XXXXXXXX XXXXXXXX
00000000 0-000000
-
-
Reload timer 1
Reload timer 2
Reload timer 3
000118H
|
-
-
Reserved
00011CH
Document Number: 002-04665 Rev *A
Page 81 of 175
MB91580M/S Series
Address offset value/Register name
Address
000120H
000124H
000128H
00012CH
000130H
000134H
000138H
00013CH
000140 H
000144 H
+0
+1
+2
IRPR0H[R] B,H,W
IRPR0L[R] B,H,W
IRPR1H[R] B,H,W
IRPR1L[R] B,H,W
00------
00------
00------
--------
IRPR2H[R] B,H,W
IRPR2L[R]
B,H,W *5
IRPR3H[R] B,H,W
IRPR3L[R] B,H,W
00------
00------
--------
0000----
IRPR4H[R] B,H,W
IRPR4L[R] B,H,W
IRPR5H[R] B,H,W
IRPR5L[R] B,H,W
00------
000000--
00------
00------
IRPR6H[R] B,H,W
IRPR6L[R] B,H,W
IRPR7H[R] B,H,W
IRPR7L[R] B,H,W
0000----
00------
00------
--------
IRPR8H[R] B,H,W
IRPR8L[R] B,H,W
IRPR9H[R] B,H,W
IRPR9L[R] B,H,W
--------
00------
00------
00------
IRPR10H[R] B,H,W
IRPR10L[R] B,H,W
IRPR11H[R] B,H,W
IRPR11L[R] B,H,W
00------
00------
00------
0000000-
IRPR12H[R] B,H,W
IRPR12L[R] B,H,W
IRPR13H[R] B,H,W
IRPR13L[R] B,H,W
0000000-
00000000
0000000-
---00---
IRPR14H[R] B,H,W
IRPR14L[R] B,H,W
IRPR15H[R] B,H,W
IRPR15L[R] B,H,W
00------
00------
00000000
0000----
IRPR16H[R] B,H,W
IRPR16L[R] B,H,W
IRPR17H[R] B,H,W
00------
--------
--------
IRPR18H[R]B,H,W
--------
IRPR18L[R]B,H,W
-
-
000000--
Block
+3
Interrupt request
batch read register
IRPR17L[R]
B,H,W
--------
-
-
-
-
000148H
|
Reserved
0001FCH
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
PCN0[R/W] B,H,W
PCSR0[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT0[W] H,W
PTMR0[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN1[R/W] B,H,W
PCSR1[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT1[W] H,W
PTMR1[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN2[R/W] B,H,W
PCSR2[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT2[W] H,W
PTMR2[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN3[R/W] B,H,W
PCSR3[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT3[W] H,W
PTMR3[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
Document Number: 002-04665 Rev *A
PPG0
PPG1
PPG2
PPG3
Page 82 of 175
MB91580M/S Series
Address offset value/Register name
Address
000220H
000224H
000228H
00022CH
+0
+1
+2
Block
+3
PCN4[R/W] B,H,W
PCSR4[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT4[W] H,W
PTMR4[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
PCN5[R/W] B,H,W
PCSR5[W] H,W
00000000 000000-0
XXXXXXXX XXXXXXXX
PDUT5[W] H,W
PTMR5[R] H,W
XXXXXXXX XXXXXXXX
11111111 11111111
-
-
GTRS0[R/W] B,H,W
GTRS1[R/W] B,H,W
-0000000 -0000000
-0000000 -0000000
PPG4
PPG5
000230H
|
Reserved
0002BCH
0002C0H
0002C4H
GTRS2[R/W] B,H,W
-
-0000000 -0000000
0002C8H
-
-
0002CCH
-
-
0002D0H
-
-
0002D4H
-
-
0002D8H
GTREN0[R/W] H,W
-
0002E0H
-
0002E4H
-
0002E8H
-
0002ECH
0002F0H
0002F4H
0002F8H
0002FCH
-
-------- --000000
0002DCH
PPG Control
GATEC0[R/W] B,H,W
------00
GATEC4[R/W] B,H,W
-
Reserved
GATEC2[R/W] B,H,W
------00
-
-
-
-
-
-
-
-
-
RCRH0[W]
RCRL0[W]
UDCRH0[R]
H,W
B,H,W
H,W
00000000
00000000
00000000
------00
CCR0[R/W] B,H
-
00000000 -0001000
RCRH1[W]
RCRL1[W]
UDCRH1[R]
H,W
B,H,W
H,W
00000000
00000000
00000000
CCR1[R/W] B,H
-
00000000 -0001000
000300H
-
000304H
-
000308H
-
00030CH
-
PPG GATE Control
Reserved
UDCRL0[R] B,H,W
00000000
U/D counter 0
CSR0[R] B
00000000
UDCRL1[R] B,H,W
00000000
U/D counter 1
CSR1[R] B
00000000
Reserved
-
-
-
-
-
-
Document Number: 002-04665 Rev *A
Reserved
Reserved
Page 83 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
-
-
000314H
-
-
-
000318H
-
00031CH
-
-
-
000324H
000328H
00032CH
000330H
000334H
000338H
00033CH
000340H
000344H
000348H
00034CH
000350H
000354H
000358H
00035CH
000360H
000364H
Block
MPUCR[R/W] H
000310H
000320H
+3
000000-0 ----0100
-
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
-
-
DPVSR[R/W] H
-------- 00000--0
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
-
-
DESR[R/W] H
-------- 00000--0
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR0[R/W] H
000000-0 00000--0
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR1[R/W] H
MPU [S]
000000-0 00000--0
(Only the CPU can
access this area)
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR2[R/W] H
000000-0 00000--0
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR3[R/W] H
000000-0 00000--0
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR4[R/W] H
000000-0 00000--0
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
PACR5[R/W] H
000000-0 00000--0
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
-
-
Document Number: 002-04665 Rev *A
PACR6[R/W] H
000000-0 00000--0
Page 84 of 175
MB91580M/S Series
Address offset value/Register name
Address
000368H
+0
+1
+2
+3
Block
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00036CH
-
000370H
-
000374H
-
000378H
-
00037CH
-
000380H
-
000384H
-
000388H
-
00038CH
-
000390H
-
000394H
-
000398H
-
00039CH
-
0003A0H
-
0003A4H
-
0003A8H
-
0003ACH
-
MPU [S]
(Only the CPU can
access this area)
PACR7[R/W] H
000000-0 00000--0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved [S]
Reserved [S]
0003B0H
|
-
Reserved [S]
0003CCH
0003D0H
-
0003D4H
-
0003D8H
-
0003DCH
-
Reserved [S]
0003E0H
|
-
-
-
-
Reserved [S]
0003FCH
Document Number: 002-04665 Rev *A
Page 85 of 175
MB91580M/S Series
Address offset value/Register name
Address
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
+0
+1
+2
+3
ICSEL0[R/W] B,H,W
ICSEL1[R/W] B,H,W
ICSEL2[R/W] B,H,W
ICSEL3[R/W] B,H,W
-----000
-------0
-------0
-------0
ICSEL4[R/W] B,H,W
ICSEL5[R/W] B,H,W
ICSEL6[R/W] B,H,W
ICSEL7[R/W] B,H,W
-------0
-------0
-------0
-----000
ICSEL8[R/W] B,H,W
ICSEL9[R/W] B,H,W
ICSEL10[R/W] B,H,W ICSEL11[R/W] B,H,W
-------0
-------0
------00
Block
-------0
ICSEL12[R/W] B,H,W ICSEL13[R/W] B,H,W ICSEL14[R/W] B,H,W ICSEL15[R/W] B,H,W
Generation and
clear of DMA
ICSEL16[R/W] B,H,W ICSEL17[R/W] B,H,W ICSEL18[R/W] B,H,W ICSEL19[R/W] B,H,W transfer request
-------0
-------0
-------0
-------0
-------0
-------0
-------0
-------0
ICSEL20[R/W] B,H,W ICSEL21[R/W] B,H,W ICSEL22[R/W] B,H,W ICSEL23[R/W] B,H,W
-------0
-----000
-----000
-----000
ICSEL24[R/W] B,H,W ICSEL25[R/W] B,H,W ICSEL26[R/W] B,H,W ICSEL27[R/W] B,H,W
-----000
-----000
-------0
-------0
00041CH
-
-
-
-
000420H
-
-
-
-
-
-
-
-
ICR00[R/W] B,H,W
ICR01[R/W] B,H,W
ICR02[R/W] B,H,W
ICR03[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR04[R/W] B,H,W
ICR05[R/W] B,H,W
ICR06[R/W] B,H,W
ICR07[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR08[R/W] B,H,W
ICR09[R/W] B,H,W
ICR10[R/W] B,H,W
ICR11[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR12[R/W] B,H,W
ICR13[R/W] B,H,W
ICR14[R/W] B,H,W
ICR15[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR16[R/W] B,H,W
ICR17[R/W] B,H,W
ICR18[R/W] B,H,W
ICR19[R/W] B,H,W
000424H
|
Reserved
00043CH
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
---11111
---11111
---11111
---11111
ICR20[R/W] B,H,W
ICR21[R/W] B,H,W
ICR22[R/W] B,H,W
ICR23[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR24[R/W] B,H,W
ICR25[R/W] B,H,W
ICR26[R/W] B,H,W
ICR27[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR28[R/W] B,H,W
ICR29[R/W] B,H,W
ICR30[R/W] B,H,W
ICR31[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR32[R/W] B,H,W
ICR33[R/W] B,H,W
ICR34[R/W] B,H,W
ICR35[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR36[R/W] B,H,W
ICR37[R/W] B,H,W
ICR38[R/W] B,H,W
ICR39[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR40[R/W] B,H,W
ICR41[R/W] B,H,W
ICR42[R/W] B,H,W
ICR43[R/W] B,H,W
---11111
---11111
---11111
---11111
ICR44[R/W] B,H,W
ICR45[R/W] B,H,W
ICR46[R/W] B,H,W
ICR47[R/W] B,H,W
---11111
---11111
---11111
---11111
Document Number: 002-04665 Rev *A
Interrupt controller
[S]
Page 86 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000470H
|
-
-
-
-
Reserved [S]
00047CH
Reset control [S]
RSTRR[R]
000480H
B,H,W
XXXX--XX
000484H
000488H
00048CH
DIVR0[R/W] B,H,W
000-----
RSTCR[R/W] B,H,W
STBCR[R/W] B,H,W
111----0
000---11 *
-
-
-
DIVR2[R/W] B,H,W
0011----
-
Power
consumption
control [S]
* Writing to STBCR
by DMA is
disabled.
-
Reserved [S]
-
Clock control [S]
Reserved [S]
-
-
-
-
IORR0[R/W] B,H,W
IORR1[R/W] B,H,W
IORR2[R/W] B,H,W
IORR3[R/W] B,H,W
-0000000
-0000000
-0000000
-0000000
IORR4[R/W] B,H,W
IORR5[R/W] B,H,W
IORR6[R/W] B,H,W
IORR7[R/W] B,H,W
-0000000
-0000000
-0000000
-0000000
000498H
-
-
-
-
00049CH
-
-
-
-
0004A0H
-
-
-
-
Reserved
-
-
-
CAN prescaler
-
-
-
-
Reserved
-
-
-
-
Reserved
-
-
-
-
Reserved
000490H
000494H
0004A4H
CANPRE[R/W] B,H,W
---00000
DMA transfer
request from a
peripheral [S]
0004A8H
|
0004ACH
0004B0H
0004B4H
|
0004C0H
0004C4H
0004C8H
CUCR1[R/W] B,H,W
CUTD1[R/W] B,H,W
-------- ---0--00
11000011 01010000
WDT1 calibration
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CCH
|
-
-
0004E0H
-
-
0004E4H
-
-
-
-
CSCFG[R/W] B,H,W
CMCFG[R/W] B,H,W
---0----
00000000
-
-
Reserved
0004DCH
Document Number: 002-04665 Rev *A
Clock monitor
Page 87 of 175
MB91580M/S Series
Address offset value/Register name
Address
0004E8H
0004ECH
+0
+1
+2
+3
PLL2DIVM[R/W]
B,H,W
PLL2DIVN[R/W]
B,H,W
PLL2DIVG[R/W]
B,H,W
PLL2MULG[R/W]
B,H,W
----0000
-0000000
----0000
00000000
PLL2CTRL[R/W]
B,H,W
PLL2DIVK[R/W]
----0000
-------0
-
-
B,H,W
CLKR2[R/W] B,H,W
000--000
Block
FlexRay
clock control *5
-
0004F0H
|
-
-
Reserved
0004FCH
000500H
-
Reserved
000504H
-
Reserved
000508H
|
-
-
-
CSELR[R/W] B,H,W
CMONR[R] B,H,W
MTMCR[R/W] B,H,W
-0----00
-01---00
00001111
-
Reserved
00050CH
000510H
000514H
PLLCR[R/W] B,H,W
CSTBR[R/W] B,H,W
PTMCR[R/W] B,H,W
00-00000 11110000
----0000
00------
000518H
-
00051CH
-
000520H
CCPSSELR[R/W]
B,H,W
-
CPUAR[R/W] B,H,W
000528H
-
-
Reset [S]
-
-
Reserved [S]
-
-
CCPSDIVR[R/W]
B,H,W
CCPLLFBR[R/W]
B,H,W
CCSSFBR0[R/W]
B,H,W
CCSSFBR1[R/W]
B,H,W
-0000000
--000000
---00000
CCSSCCR0[R/W]
B,H,W
CCSSCCR1[R/W] B,H,W
-000-000
----0000
00052CH
-
Clock control [S]
-
0---XXXX
-------0
000524H
-
000----- --------
CCCGRCR0[R/W]
B,H,W
CCCGRCR1[R/W]
B,H,W
CCCGRCR2[R/W]
B,H,W
00----00
00000000
00000000
CCPMUCR0[R/W]
B,H,W
CCPMUCR1[R/W]
B,H,W
Clock control 2
000530H
-
-
0-----00
0--00000
000534H
-
-
-
-
000538H
-
-
-
-
00053CH
-
-
-
-
-
-
-
-
EIRR0[R/W] B,H,W
ENIR0[R/W] B,H,W
ELVR0[R/W] B,H,W
External interrupt
-XXXXXXX
-0000000
--000000 00000000
(INT0 to 6)
000540H
|
Reserved
00054CH
000550H
Document Number: 002-04665 Rev *A
Page 88 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
Block
+3
000554H
|
-
-
-
-
Reserved
-
-
CSV
000568H
CSVCR[R/W] B
00056CH
-
000570H
CRTR[R/W] B,H,W
01111111
-
-
-
WDT1 calibration
(trimming)
-
-
-
-
Reserved
-
-
-
Regulator control
-
Low-voltage
detection
Reserved
-0--1--0
000574H
|
00057CH
000580H
000584H
REGSEL[R/W] B,H,W
01--110-
LVD[R/W]
LVD5R[R/W] B,H,W
LVD5F[R/W] B,H,W
-------1
001100-1
-
-
-
-
PMUSTR [R/W]
B,H,W
PMUCTLR[R/W]
B,H,W
PWRTMCTL[R/W]
B,H,W
-
0-----1X
0-00----
-----011
-
PMUINTF1[R/W]
B,H,W
PMUINTF2[R/W]
B,H,W
00000000
-00-----
B,H,W
01000--0
000588H
|
00058CH
000590H
000594H
-
000598H
-
-
-
-
00059CH
-
-
-
-
-
-
-
-
PMU
0005A0H
|
Reserved
0005FCH
000600H
|
-
Reserved [S]
00060CH
000610H
|
-
-
-
-
Reserved [S]
00063CH
000640H
|
-
Reserved [S]
00064CH
000650H
|
-
-
-
-
Reserved [S]
00067CH
000680H
|
-
Reserved [S]
00068CH
Document Number: 002-04665 Rev *A
Page 89 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000690H
|
-
-
-
-
Reserved [S]
0006BCH
0006C0H
|
-
Reserved [S]
0006CCH
0006D0H
|
-
-
-
-
Reserved
0006F0H
0006F4H
-
Reserved
0006F8H
|
-
-
-
-
Reserved
0006FCH
000700H
-
Reserved
000704H
|
-
-
-
BPCCRA[R/W] B
BPCCRB[R/W] B
BPCCRC[R/W] B
00000000
00000000
00000000
-
Reserved
00070CH
000710H
000714H
000718H
00071CH
-
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
Bus performance
counter
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
000720H
|
-
-
-
-
Reserved
-
-
-
Operation mode
-
-
-
Reserved [S]
FSTR[R/W] B
-----001
Flash memory
register [S]
0007F8H
0007FCH
BMODR[R] B,H,W
XXXXXXXX
000800H
|
-
00083CH
000840H
000844H
FCTLR[R/W] H
-
-0--1000 0--0----
-
-
-
Reserved [S]
-
-
-
-
Reserved [S]
-
-
000848H
|
000854H
000858H
Document Number: 002-04665 Rev *A
WREN[R/W] H
00000000 00000000
Wild register [S]
Page 90 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
00085CH
|
-
-
-
-
Reserved [S]
00087CH
000880H
000884H
000888H
00088CH
000890H
000894H
000898H
00089CH
0008A0H
0008A4H
0008A8H
0008ACH
0008B0H
0008B4H
0008B8H
0008BCH
0008C0H
0008C4H
0008C8H
0008CCH
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR05[R/W] W
Wild register [S]
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04665 Rev *A
Page 91 of 175
MB91580M/S Series
Address offset value/Register name
Address
0008D0H
0008D4H
0008D8H
0008DCH
0008E0H
0008E4H
0008E8H
0008ECH
0008F0H
0008F4H
0008F8H
0008FCH
+0
+1
+2
Block
+3
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild register [S]
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX-WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
|
-
-
-
-
Reserved
000BF8H
000BFCH
-
Document Number: 002-04665 Rev *A
UER[W] B,H,W
-------- -------X
OCDU
Page 92 of 175
MB91580M/S Series
Address
000C00H
000C04H
000C08H
000C0CH
000C10H
000C14H
000C18H
000C1CH
000C20H
000C24H
000C28H
000C2CH
000C30H
000C34H
000C38H
000C3CH
000C40H
000C44H
Address offset value/Register name
+0
+1
+2
+3
Block
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DCSR0[R/W] H
DTCR0[R/W] H
0------- -----000
00000000 00000000
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
DCSR1[R/W] H
DTCR1[R/W] H
0------- -----000
00000000 00000000
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
DCSR2[R/W] H
DTCR2[R/W] H
0------- -----000
00000000 00000000
DMA controller [S]
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
DCSR3[R/W] H
DTCR3[R/W] H
0------- -----000
00000000 00000000
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
DCSR4[R/W] H
DTCR4[R/W] H
0------- -----000
00000000 00000000
Document Number: 002-04665 Rev *A
Page 93 of 175
MB91580M/S Series
Address offset value/Register name
Address
000C48H
000C4CH
000C50H
000C54H
000C58H
000C5CH
000C60H
000C64H
000C68H
000C6CH
000C70H
000C74H
000C78H
000C7CH
+0
+1
+2
+3
Block
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
DCSR5[R/W] H
DTCR5[R/W] H
0------- -----000
00000000 00000000
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
DCSR6[R/W] H
DTCR6[R/W] H
0------- -----000
00000000 00000000
DSAR6[R/W] W
DMA controller [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
DCSR7[R/W] H
DTCR7[R/W] H
0------- -----000
00000000 00000000
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80H
|
-
-
-
-
-
-
DNMIR[R/W] B
DILVR[R/W] B
0------0
---11111
-
-
-
DDR01[R/W] B,H
DDR02[R/W] B,H
DDR03[R/W] B,H
00000000
00000000
00000000
000DF0H
000DF4H
000DF8H
000DFCH
000E00H
000E04H
DMACR[R/W] W
0------- -------- 0------- -------DDR04[R/W] B,H
DDR05[R/W] B,H
00000000
-0000000
000E08H
-
000E0CH
-
DDR09[R/W] B,H
---00---
Document Number: 002-04665 Rev *A
-
Reserved [S]
DDR07[R/W] B,H
-----000
-
-
-
-
Data direction
register
Page 94 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000E10H
|
-
-
-
-
PFR01[R/W] B,H
PFR02[R/W] B,H
PFR03[R/W] B,H
00000000
00000000
00000000
Reserved
000E1CH
000E20H
000E24H
PFR04[R/W] B,H
PFR05[R/W] B,H
00000000
-0000000
000E28H
-
000E2CH
-
PFR09[R/W] B,H
-
PFR07[R/W] B,H
-----000
-
-
-
-
-
-
-
-
PDDR01[R] B,H,W
PDDR02[R] B,H,W
PDDR03[R] B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
---00---
Port function
register
000E30H
|
Reserved
000E3CH
000E40H
000E44H
PDDR04[R] B,H,W
PDDR05[R] B,H,W
XXXXXXXX
-XXXXXXX
000E48H
-
000E4CH
-
PDDR09[R] B,H,W
-
PDDR07[R] B,H,W
-----XXX
-
-
-
-
-
-
-
-
-
EPFR00[R/W] B,H
EPFR01[R/W] B,H
EPFR02[R/W] B,H
EPFR03[R/W] B,H
-------0
------00
-----000
--000000
EPFR06[R/W] B,H
EPFR07[R/W] B,H
------00
----0000
---XX---
Input data direct
read register
000E50H
|
Reserved
000E5CH
000E60H
000E64H
-
-
000E68H
EPFR08[R/W]
B,H *5
EPFR09[R/W] B,H
EPFR10[R/W] B,H
-------0
-0000000
----0000
-
000E6CH
-
-
-
-
000E70H
-
-
-
-
000E74H
-
-
-
-
000E78H
-
-
-
-
000E7CH
-
-
-
-
000E80H
-
-
-
-
-
-
-
-
Extended port
function register
000E84H
|
Reserved
000EBCH
Document Number: 002-04665 Rev *A
Page 95 of 175
MB91580M/S Series
Address offset value/Register name
Address
000EC0H
000EC4H
+0
-
+1
PPER02[R/W] B,H
PPER03[R/W] B,H
00000000
00000000
00000000
PPER05[R/W] B,H
00000000
-0000000
-
000ECCH
-
+3
PPER01[R/W] B,H
PPER04[R/W] B,H
000EC8H
+2
PPER09[R/W] B,H
-
PPER07[R/W] B,H
-----000
-
-
-
-
-
-
-
-
PILR01[R/W] B,H
PILR02[R/W] B,H
PILR03[R/W] B,H
11111111
11111111
11111111
---00---
Block
Port pull-up/down
enable register
000ED0H
|
Reserved
000EDCH
000EE0H
000EE4H
PILR04[R/W] B,H
PILR05[R/W] B,H
11111111
-1111111
000EE8H
-
000EECH
-
PILR09[R/W] B,H
-
PILR07[R/W] B,H
-----111
Port input level
selection register
-
-
-
-
-
-
-
-
-
Reserved
-
-
-
-
Reserved
PODR01[R/W] B,H
PODR02[R/W] B,H
PODR03[R/W] B,H
00000000
00000000
00000000
---11---
000EF0H
|
000EFCH
000F00H
|
000F1CH
000F20H
000F24H
PODR04[R/W] B,H
PODR05[R/W] B,H
00000000
-0000000
000F28H
-
000F2CH
-
PODR09[R/W] B,H
-
PODR07[R/W] B,H
-----000
Port output drive
register
-
-
-
-
-
-
-
-
Reserved
-
-
-
Port input enable
register
-
-
Port key code
---00---
000F30H
|
000F3CH
000F40H
000F44H
000F48H
000F4CH
PORTEN[R/W] B,H,W
------00
KEYCDR[R/W] H
00000000 00000000
ADERH[R/W] B,H
ADERL[R/W] B,H
-------- ---11---
-1111111 11111111
DAER[R/W] B,H
-------0
-
Document Number: 002-04665 Rev *A
-
Analog input
enable register
-
Analog output
enable register
Page 96 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
000F50H
|
-
-
-
-
Reserved
-
-
Synchronous/asyn
chronous switch
control
-
Reserved
000FFCH
001000H
SACR[R/W] B,H,W
-------0
PICD[R/W]
B,H,W
----0011
001004H
|
-
-
-
-
-
-
0010BCH
0010C0H
0010C4H
0010C8H
0010CCH
0010D0H
0010D4H
0010D8H
0010DCH
CRCCR[R/W] B,H,W
-0000000
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
CRC arithmetic
operation 0
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
-
-
-
CRCCR1[R/W] B,H,W
-0000000
CRCINIT1[R/W] B,H,W
11111111 11111111 11111111 11111111
CRC arithmetic
operation 1
CRCIN1[R/W] B,H,W
00000000 00000000 00000000 00000000
CRCR1[R] B,H,W
11111111 11111111 11111111 11111111
0010E0H
|
-
-
-
-
-
-
Reserved
TCGSE[R/W] B,H,W
Free-run timer
simultaneous
activation
0010FCH
001100H
001104H
001108H
00110CH
001110H
001114H
001118H
TCGS[R/W] B,H,W
------00
CPCLRB0/CPCLR0[R/W] H,W
TCDT0[R/W] H,W
11111111 11111111
00000000 00000000
TCCS0[R/W] B,H,W
--000000
Free-run timer 0
00000000 01000000 ----0000 -------CPCLRB1/CPCLR1[R/W] H,W
TCDT1[R/W] H,W
11111111 11111111
00000000 00000000
TCCS1[R/W] B,H,W
Free-run timer 1
00000000 01000000 ----0000 -------CPCLRB2/CPCLR2[R/W] H,W
TCDT2[R/W] H,W
11111111 11111111
00000000 00000000
TCCS2[R/W] B,H,W
Free-run timer 2
00000000 01000000 ----0000 --------
Document Number: 002-04665 Rev *A
Page 97 of 175
MB91580M/S Series
Address offset value/Register name
Address
00111CH
001120H
001124H
001128H
00112CH
001130H
001134H
001138H
00113CH
001140H
001144H
001148H
00114CH
001150H
001154H
001158H
00115CH
001160H
001164H
001168H
+0
+1
+2
CPCLRB3/CPCLR3[R/W] H,W
TCDT3[R/W] H,W
11111111 11111111
00000000 00000000
+3
Block
Free-run timer 3
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB4/CPCLR4[R/W] H,W
TCDT4[R/W] H,W
11111111 11111111
00000000 00000000
Free-run timer 4
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 -------CPCLRB5/CPCLR5[R/W] H,W
TCDT5[R/W] H,W
11111111 11111111
00000000 00000000
Free-run timer 5
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 -------FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
-
Free-run timer
selection
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
FRS5[R/W] B,H,W
-----000 -000-000 -000-000 -000-000
FRS6[R/W] B,H,W
-------- -----000 -000---- -------OCCPB0/OCCP0[R/W] H,W
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
00000000 00000000
OCS01[R/W] B,H,W
-110--00 00001100
OCMOD01[R/W]
-
B,H,W
------00
OCCPB2/OCCP2[R/W] H,W
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
00000000 00000000
OCS23[R/W] B,H,W
-110--00 00001100
-
OCMOD23[R/W]
B,H,W
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
00000000 00000000
-110--00 00001100
Document Number: 002-04665 Rev *A
Output compare
2/3
------00
OCCPB4/OCCP4[R/W] H,W
OCS45[R/W] B,H,W
Output compare
0/1
-
OCMOD45[R/W]
B,H,W
Output compare
4/5
------00
Page 98 of 175
MB91580M/S Series
Address offset value/Register name
Address
00116CH
001170H
001174H
001178H
00117CH
+0
+1
+2
OCCPB6/OCCP6[R/W] H,W
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
00000000 00000000
OCS67[R/W] B,H,W
-
-110--00 00001100
00000000 00000000
00000000 00000000
OCS89[R/W] B,H,W
-
-110--00 00001100
OCCPB10/OCCP10[R/W] H,W
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
00000000 00000000
B,H,W
-
001190H
OCMOD1011
[R/W] B,H,W
IPCP0[R] H,W
IPCP1[R] H,W
00000000 00000000
00000000 00000000
B,H,W
-
IPCP2[R] H,W
IPCP3[R] H,W
00000000 00000000
00000000 00000000
ICS23[R/W] B,H,W
-
------00 00000000
LSYNS[R/W] B,H,W
-
-
-
-
-
00119CH
-
-
0011A0H
-
-
-
-
-
0011A8H
0011ACH
0011B0H
------10
TMRR0[R/W] H,W
TMRR1[R/W] H,W
00000000 00000001
00000000 00000001
TMRR2[R/W] H,W
-
00000000 00000001
DTSCR0[R/W] B,H,W DTSCR1[R/W] B,H,W DTSCR2[R/W] B,H,W
00000000
0011B4H
-
0011B8H
-
0011BCH
-
00000000
DTIR0[R/W] B,H,W
000000-SIGCR10[R/W] B,H,W
00000000
00000000
-
Input capture 0/1
Input capture 2/3
001198H
DTSR[R/W] B,H,W
Output compare
10/11
------00
001194H
0011A4H
Output compare
8/9
------00
------00 00000000
00118CH
OCMOD89[R/W]
B,H,W
------00
ICS01[R/W]
001188H
Output compare
6/7
------00
OCCPB9/OCCP9[R/W] H,W
-110--00 00001100
001184H
OCMOD67[R/W]
B,H,W
OCCPB8/OCCP8[R/W] H,W
OCS1011[R/W]
001180H
Block
+3
-
Reserved
Reserved
DTTI selection
DTMNS0[R/W] B,H,W
Waveform
generator
0/1/2
00---000
SIGCR20[R/W] B,H,W
000000-1
PICS0[R/W] B,H,W
000000-- -------- -------- --------
Document Number: 002-04665 Rev *A
Page 99 of 175
MB91580M/S Series
Address offset value/Register name
Address
0011C0H
0011C4H
0011C8H
0011CCH
+0
+1
+2
TMRR3[R/W] H,W
TMRR4[R/W] H,W
00000000 00000001
00000000 00000001
TMRR5[R/W] H,W
-
00000000 00000001
DTSCR3[R/W] B,H,W DTSCR4[R/W] B,H,W DTSCR5[R/W] B,H,W
00000000
-
0011D0H
-
0011D4H
-
00000000
DTIR1[R/W] B,H,W
000000-SIGCR11[R/W] B,H,W
00000000
Document Number: 002-04665 Rev *A
00000000
-
Block
+3
-
Waveform
generator
DTMNS1[R/W] B,H,W 3/4/5
00---000
SIGCR21[R/W] B,H,W
-------1
Page 100 of 175
MB91580M/S Series
Address offset value/Register name
Address
0011D8H
0011DCH
0011E0H
0011E4H
0011E8H
0011ECH
0011F0H
0011F4H
0011F8H
0011FCH
001200H
+0
ADTSS[R/W] B,H,W
-------0
+2
+3
-
-
-
-
-
-
-------- ---00--- -0000000 00000000
ADCOMP0/ADCOMPB0[R/W] H,W
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP2/ADCOMPB2[R/W] H,W
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP4/ADCOMPB4[R/W] H,W
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP6/ADCOMPB6[R/W] H,W
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP8/ADCOMPB8[R/W] H,W
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP10/ADCOMPB10[R/W] H,W
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP12/ADCOMPB12[R/W] H,W
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
00000000 00000000
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
-
001208H
-
12-bit A/D
converter
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
-
001210H
-
001214H
-
-
-
-
001218H
-
-
-
-
00121CH
-
-
-
-
001220H
-
-
-
-
001224H
001228H
00122CH
001230H
Block
ADTSE[R/W] B,H,W
001204H
00120CH
+1
-
ADTCS0[R/W] B,H,W
ADTCS1[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS2[R/W] B,H,W
ADTCS3[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS4[R/W] B,H,W
ADTCS5[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS6[R/W] B,H,W
ADTCS7[R/W] B,H,W
00000000 0010-000
00000000 0010-000
Document Number: 002-04665 Rev *A
Page 101 of 175
MB91580M/S Series
Address offset value/Register name
Address
001234H
001238H
00123CH
001240H
+0
+2
ADTCS8[R/W] B,H,W
ADTCS9[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS10[R/W] B,H,W
ADTCS11[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS12[R/W] B,H,W
ADTCS13[R/W] B,H,W
00000000 0010-000
00000000 0010-000
ADTCS14[R/W] B,H,W
-
001248H
-
+3
ADTCS19[R/W] B,H,W
00000000 00100000
ADTCS20[R/W] B,H,W
-
00000000 00100000
001250H
-
001254H
-
-
-
-
001258H
-
-
-
-
00125CH
-
-
-
-
001260H
-
-
-
-
001264H
001268H
00126CH
001270H
001274H
001278H
00127CH
001280H
ADTCD1[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD2[R] B,H,W
ADTCD3[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD4[R] B,H,W
ADTCD5[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD6[R] B,H,W
ADTCD7[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD8[R] B,H,W
ADTCD9[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD10[R] B,H,W
ADTCD11[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD12[R] B,H,W
ADTCD13[R] B,H,W
10--0000 00000000
10--0000 00000000
ADTCD14[R] B,H,W
001288H
-
12-bit A/D
converter
-
10--0000 00000000
-
00128CH
-
ADTCD0[R] B,H,W
001284H
Block
-
00000000 0010-000
001244H
00124CH
+1
ADTCD19[R] B,H,W
10--0000 00000000
ADTCD20[R] B,H,W
-
10--0000 00000000
001290H
-
001294H
-
-
-
-
001298H
-
-
-
-
Document Number: 002-04665 Rev *A
Page 102 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
00129CH
-
-
-
-
0012A0H
-
-
-
-
0012A4H
0012A8H
0012ACH
0012B0H
ADCS0[R/W]
ADCH0[R]
B,H,W
B,H,W
0------- --------
-----000
ADCS1[R/W]
ADCH1[R]
B,H,W
B,H,W
0------- --------
-----000
ADCS2[R/W]
ADCH2[R]
B,H,W
B,H,W
0------- --------
-----000
MTRCSR[R/W] B,H,W
-------0
-
RTOSEL0[R/W]
B,H,W
RTOSEL1[R/W]
B,H,W
--000000
-------0
-
001300H
-
ADMD0[R/W] B,H,W
----0000
ADMD1[R/W] B,H,W
12-bit A/D
converter
----0000
ADMD2[R/W] B,H,W
----0000
Motor control
extension function
-
-
-
-
-
-
-
-
-
001304H
-
-
-
-
001308H
-
-
-
-
00130CH
-
-
-
-
001310H
-
-
-
-
001314H
-
-
-
-
001318H
-
-
-
-
00131CH
-
-
-
-
001320H
-
-
-
-
001324H
-
0012B4H
Block
+3
0012B8H
|
Reserved
0012FCH
Reserved
-
001328H
|
-
-
-
-
00132CH
001330H
-
-
001334H
|
-
-
-
-
H,W
-
Reserved
0013FCH
001400H
DACR[R/W] B,H,W
-------0
DADR[R/W]
DAC
------XX XXXXXXXX
001404H
|
-
-
-
-
Reserved
0014FCH
Document Number: 002-04665 Rev *A
Page 103 of 175
MB91580M/S Series
Address offset value/Register name
Address
001500H
001504H
001508H
00150CH
001510H
+0
+1
+2
SCR0/(IBCR0)
[R/W] B,H,W
SMR0
SSR0
[R/W] B,H,W
[R/W] B,H,W
ESCR0/(IBSR0)
[R/W] B,H,W
0--00000
000000-0
0--00011
00000000
-/(RDR10/(TDR10))[R/W] B,H,W
RDR00/(TDR00)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR0[R/W] B,H,W
STMR0[R] B,H,W
0----000 00000000
00000000 00000000
STMCR0[R/W] B,H,W
-/(SFUR0) [R/W] B,H,W
00000000 00000000
-------- -------- *4
-
-
-/(SFLR10) [R/W]
B,H,W
--------
001514H
-
-
-
001518H
-
-
-
00151CH
001520H
001524H
001528H
00152CH
001530H
001534H
001538H
+3
*4
*2: Reserved
because I2C mode
is not set
immediately after
reset
*4
-
FCR00[R/W] B,H,W
00-00100
-0000000
00000000
00000000
SCR1[R/W] B,H,W
SMR1[R/W] B,H,W
SSR1[R/W] B,H,W
ESCR1[R/W] B,H,W
0--00000
000000-0
0--00011
00000000
00000000 00000000
FCR10[R/W] B,H,W
-/(RDR11/(TDR11))[R/W] B,H,W
RDR01/(TDR01)[R/W] B,H,W
-------- -------- *3
-------0 00000000 *1
SACSR1[R/W] B,H,W
STMR1[R] B,H,W
Multi Function
Serial I/F 1
0----000 00000000
00000000 00000000
STMCR1[R/W] B,H,W
-/(SCSCR1/SFUR1) [R/W] B,H,W
00000000 00000000
-------- -------- *3 *4
-/(SCSTR31) [R/W]
B,H,W
-/(SCSTR21) [R/W]
B,H,W
-------- *3
-------- *3
-
-
-
-
001544H
BGR1[R/W] H,W
-
-
00000000 00000000
*1: Byte access is
possible only for
access to lower 8
bits.
*3: Reserved
-/(SCSTR11/
-/(SCSTR01/
SFLR11) [R/W] B,H,W SFLR01) [R/W] B,H,W because CSIO
mode is not set
-------- *3 *4
-------- *3 *4
immediately after
reset
B,H,W
00000000
001540H
*3: Reserved
because CSIO
mode is not set
immediately after
reset
*4: Reserved
-/(ISMK0)[R/W] B,H,W -/(ISBA0)[R/W] B,H,W because LIN2.1
mode is not set
-------- *2
-------- *2
immediately after
FBYTE20[R/W] B,H,W FBYTE10[R/W] B,H,W reset
BGR0[R/W] H,W
TBYTE01[R/W]
00153CH
Multi Function
Serial I/F 0
*1: Byte access is
possible only for
access to lower 8
bits.
-/(SFLR00) [R/W]
B,H,W
--------
Block
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset
-
FCR11[R/W] B,H,W
FCR01[R/W] B,H,W
FBYTE21[R/W] B,H,W FBYTE11[R/W] B,H,W
00-00100
-0000000
00000000
00000000
-
-
-
-
001548H
|
Reserved
001FFCH
Document Number: 002-04665 Rev *A
Page 104 of 175
MB91580M/S Series
Address offset value/Register name
Address
002000H
002004H
002008H
00200CH
002010H
002014H
002018H
00201CH
002020H
002024H
002028H,
00202CH
002030H,
002034H
002038H,
00203CH
002040H
002044H
002048H
00204CH
002050H
002054H
002058H,
00205CH
002060H,
002064H
+0
+1
+2
CTRLR0[R/W] B,H,W
STATR0[R/W] B,H,W
-------- 000-0001
-------- 00000000
ERRCNT0 [R] B,H,W
BTR0[R/W] B,H,W
00000000 00000000
-0100011 00000001
INTR0[R] B,H,W
TESTR0[R/W] B,H,W
00000000 00000000
-------- X00000--
BRPER0[R/W] B,H,W
-------- ----0000
-
IF1CREQ0[R/W] B,H,W
IF1CMSK0[R/W] B,H,W
0------- 00000001
-------- 00000000
IF1MSK20[R/W] B,H,W
IF1MSK10[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF1ARB20[R/W] B,H,W
IF1ARB10[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1MCTR0[R/W] B,H,W
00000000 0---0000
Block
+3
-
IF1DTA10[R/W] B,H,W
IF1DTA20[R/W] B,H,W
00000000 00000000
00000000 00000000
IF1DTB10[R/W] B,H,W
IF1DTB20[R/W] B,H,W
00000000 00000000
00000000 00000000
-
-
CAN 0
64msb
Reserved (IF1 data mirror)
-
-
IF2CREQ0[R/W] B,H,W
IF2CMSK0[R/W] B,H,W
0------- 00000001
-------- 00000000
IF2MSK20[R/W] B,H,W
IF2MSK10[R/W] B,H,W
11-11111 11111111
11111111 11111111
IF2ARB20[R/W] B,H,W
IF2ARB10[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2MCTR0[R/W] B,H,W
00000000 0---0000
-
IF2DTA10[R/W] B,H,W
IF2DTA20[R/W] B,H,W
00000000 00000000
00000000 00000000
IF2DTB10[R/W] B,H,W
IF2DTB20[R/W] B,H,W
00000000 00000000
00000000 00000000
-
-
Reserved (IF2 data mirror)
Document Number: 002-04665 Rev *A
Page 105 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
Block
+3
002068H
|
-
-
TREQR20[R] B,H,W
TREQR10[R] B,H,W
00000000 00000000
00000000 00000000
TREQR40[R] B,H,W
TREQR30[R] B,H,W
00000000 00000000
00000000 00000000
002088H
-
-
00208CH
-
-
NEWDT20[R] B,H,W
NEWDT10[R] B,H,W
00000000 00000000
00000000 00000000
NEWDT40[R] B,H,W
NEWDT30[R] B,H,W
00207CH
002080H
002084H
002090H
002094H
00000000 00000000
00000000 00000000
002098H
-
-
00209CH
-
-
CAN 0
INTPND20[R] B,H,W
INTPND10[R] B,H,W
64msb
00000000 00000000
00000000 00000000
INTPND40[R] B,H,W
INTPND30[R] B,H,W
00000000 00000000
00000000 00000000
0020A8H
-
-
0020ACH
-
-
MSGVAL20[R] B,H,W
MSGVAL10[R] B,H,W
00000000 00000000
00000000 00000000
MSGVAL40[R] B,H,W
MSGVAL30[R] B,H,W
00000000 00000000
00000000 00000000
0020B8H
-
-
0020BCH
-
-
-
-
-
-
0020A0H
0020A4H
0020B0H
0020B4H
0020C0H
|
0020FCH
002100H
|
Reserved
0022FCH
002300H
DFCTLR[R/W] B,H,W
-
-0------ --------
002304H
-
002308H
FLIFCTLR[R/W]
B,H,W
DFSTR[R/W] B,H,W
-----001
-
-
-
-
FLIFFER1[R/W]
B,H,W
FLIFFER2[R/W]
B,H,W
--------
--------
-
-
---0--00
WorkFlash
00230CH
|
-
-
Reserved
002FFCH
Document Number: 002-04665 Rev *A
Page 106 of 175
MB91580M/S Series
Address offset value/Register name
Address
003000H
003004H
003008H
00300CH
003010H
003014H
003018H
00301CH
003020H
003024H
003028H
00302CH
003030H
003034H
003038H
00303CH
003040H
003044H
+0
+1
SEEARX[R] B,H,W
+2
--000000 00000000
EECSRX[R/W] B,H,W
EFEARX[R/W] B,H,W
-
Block
DEEARX[R] B,H,W
--000000 00000000
----00-0
+3
-
XBS RAM
ECC control
register
--000000 00000000
EFECRX[R/W] B,H,W
-------0 00000000 00000000
TEAR0X[R] B,H,W
000----- -------- --000000 00000000
TEAR1X[R] B,H,W
000----- -------- --000000 00000000
TEAR2X[R] B,H,W
000----- -------- --000000 00000000
TAEARX[R/W] B,H,W
TASARX[R/W] B,H,W
--101111 11111111
--000000 00000000
TFECRX[R/W] B,H,W TICRX[R/W] B,H,W
----0000
TSRCRX[R/W] B,H,W
0-------
----0000
-
SEEARA[R] B,H,W
----00-0
-
diagnosis register
TTCRX[R/W]
B,H,W
------00 00001100
-
TKCCRX[R/W] B,H,W
00----00
DEEARA[R] B,H,W
--000000 00000000
EECSRA[R/W] B,H,W
XBS RAM
--000000 00000000
-
EFEARA[R/W]
Backup RAM
B,H,W
ECC control
register
--000000 00000000
EFECRA[R/W] B,H,W
-------0 00000000 00000000
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
TAEARA[R/W] B,H,W
TASARA[R/W] B,H,W
-----111 11111111
-----000 00000000
TFECRA[R/W] B,H,W TICRA[R/W] B,H,W
----0000
TSRCRA[R/W] B,H,W
0-------
----0000
Backup RAM
diagnosis register
TTCRA[R/W]
B,H,W
------00 00001100
-
-
-
-
TKCCRA[R/W] B,H,W
00----00
003048H
|
-
-
Reserved
0030FCH
Document Number: 002-04665 Rev *A
Page 107 of 175
MB91580M/S Series
Address offset value/Register name
Address
003100H
003104H
003108H
00310CH
003110H
003114H
003118H
00311CH
003120H
003124H
+0
+1
+2
Block
+3
BUSDIGSR0[R/W] H,W
BUSDIGSR1[R/W] H,W
00000000 0-----00
00000000 0-----00
BUSDIGSR2[R/W] H,W
BUSTSTR0[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR0[R] W
00000000 00000000 00000000 00000000
BUSADR1[R] W
00000000 00000000 00000000 00000000
BUSADR2[R] W
00000000 00000000 00000000 00000000
Bus diagnosis
BUSDIGSR3[R/W] H,W
-
00000000 0-----00
BUSDIGSR4[R/W] H,W
BUSTSTR1[R/W] H,W
00000000 0-----00
00--0000 00000000
BUSADR3[R] W
00000000 00000000 00000000 00000000
BUSADR4[R] W
00000000 00000000 00000000 00000000
003128H
|
-
-
-
-
Reserved
003FFCH
004000H
|
Backup RAM
Backup RAM area
005FFCH
006000H
|
-
-
-
-
Reserved
00CFFCH
00D000H
00D004H
CIF0[R] W
00000100 11111111 01011011 11111111
FlexRay
CIF1[R/W] W
CIF *5
00000000 -------0 -0000000 --------
00D008H
|
-
-
-
-
-
-
-
Reserved
00D00CH
00D010H
-
00D014H
-
00D018H
-
00D01CH
LCK[R/W] W
FlexRay
GIF *5
-------- -------- -------- 00000000
Document Number: 002-04665 Rev *A
Page 108 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D020H
00D024H
00D028H
00D02CH
00D030H
00D034H
00D038H
00D03CH
00D040H
00D044H
00D048H
00D04CH
00D050H
+0
+1
+2
Block
+3
EIR[R/W] W
-----000 -----000 ----0000 00000000
SIR[R/W] W
------00 ------00 00000000 00000000
EILS[R/W] W
-----000 -----000 ----0000 00000000
SILS[R/W] W
------11 ------11 11111111 11111111
EIES[R/W] W
-----000 -----000 ----0000 00000000
EIER[R/W] W
-----000 -----000 ----0000 00000000
SIES[R/W] W
FlexRay
------00 ------00 00000000 00000000
INT *5
SIER[R/W] W
------00 ------00 00000000 00000000
ILE[R/W] W
-------- -------- -------- ------00
T0C[R/W] W
--000000 00000000 -0000000 ------00
T1C[R/W] W
--000000 00000010 -------- ------00
STPW1[R/W] W
--000000 00000000 --000000 -0000000
STPW2[R] W
-----000 00000000 -----000 00000000
00D054H
|
-
-
-
-
Reserved
00D07CH
00D080H
00D084H
00D088H
00D08CH
00D090H
00D094H
00D098H
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
SUCC2[R/W] W
FlexRay
----0001 ---00000 00000101 00000100
SUC *5
SUCC3[R/W] W
-------- -------- -------- 00010001
NEMC[R/W] W
FlexRay
-------- -------- -------- ----0000
NEM *5
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
FlexRay
PRTC2[R/W] W
PRT *5
--001111 00101101 --001010 --001110
MHDC[R/W] W
FlexRay
---00000 00000000 -------- -0000000
MHD *5
Document Number: 002-04665 Rev *A
Page 109 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D09CH
00D0A0H
00D0A4H
00D0A8H
00D0ACH
00D0B0H
00D0B4H
00D0B8H
00D0BCH
00D0C0H
00D0C4H
00D0C8H
+0
+1
-
+2
+3
Block
Reserved
GTUC1[R/W] W
-------- ----0000 00000010 10000000
GTUC2[R/W] W
-------- ----0010 --000000 00001010
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
GTUC4[R/W] W
--000000 00001000 --000000 00000111
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
GTUC6[R/W] W
FlexRay
-----000 00000010 -----000 00000000
GTU *5
GTUC7[R/W] W
------00 00000010 ------00 00000100
GTUC8[R/W] W
---00000 00000000 -------- --000010
GTUC9[R/W] W
-------- ------00 ---00001 --000001
GTUC10[R/W] W
-----000 00000010 --000000 00000101
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0CCH
|
-
Reserved
00D0FCH
00D100H
00D104H
00D108H
00D10CH
CCSV[R] W
--000000 00010000 -100--00 00000000
FlexRay
CCEV[R] W
SUC *5
-------- -------- ---00000 00--0000
-
Document Number: 002-04665 Rev *A
Reserved
Page 110 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D110H
00D114H
00D118H
00D11CH
00D120H
00D124H
00D128H
00D12CH
00D130H
00D134H
00D138H
00D13CH
+0
+1
+2
+3
Block
SCV[R] W
-----000 00000000 -----000 00000000
MTCCV[R] W
-------- --000000 --000000 00000000
RCV[R] W
-------- -------- ----0000 00000000
OCV[R] W
-------- -----000 00000000 00000000
SFS[R] W
-------- ----0000 00000000 00000000
SWNIT[R] W
-------- -------- ----0000 00000000
ACS[R/W] W
FlexRay
GTU *5
-------- -------- ---00000 ---00000
ESID1[R] W
-------- -------- 00----00 00000000
ESID2[R] W
-------- -------- 00----00 00000000
ESID3[R] W
-------- -------- 00----00 00000000
ESID4[R] W
-------- -------- 00----00 00000000
Document Number: 002-04665 Rev *A
Page 111 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D140H
00D144H
00D148H
00D14CH
00D150H
00D154H
00D158H
00D15CH
00D160H
00D164H
00D168H
00D16CH
00D170H
00D174H
00D178H
00D17CH
00D180H
00D184H
00D188H
00D18CH
00D190H
00D194H
+0
+1
+2
+3
Block
ESID5[R] W
-------- -------- 00----00 00000000
ESID6[R] W
-------- -------- 00----00 00000000
ESID7[R] W
-------- -------- 00----00 00000000
ESID8[R] W
-------- -------- 00----00 00000000
ESID9[R] W
-------- -------- 00----00 00000000
ESID10[R] W
-------- -------- 00----00 00000000
ESID11[R] W
-------- -------- 00----00 00000000
ESID12[R] W
-------- -------- 00----00 00000000
ESID13[R] W
-------- -------- 00----00 00000000
ESID14[R] W
-------- -------- 00----00 00000000
ESID15[R] W
-------- -------- 00----00 00000000
-
FlexRay
GTU *5
OSID1[R] W
-------- -------- 00----00 00000000
OSID2[R] W
-------- -------- 00----00 00000000
OSID3[R] W
-------- -------- 00----00 00000000
OSID4[R] W
-------- -------- 00----00 00000000
OSID5[R] W
-------- -------- 00----00 00000000
OSID6[R] W
-------- -------- 00----00 00000000
OSID7[R] W
-------- -------- 00----00 00000000
OSID8[R] W
-------- -------- 00----00 00000000
OSID9[R] W
-------- -------- 00----00 00000000
OSID10[R] W
-------- -------- 00----00 00000000
Document Number: 002-04665 Rev *A
Page 112 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D198H
00D19CH
00D1A0H
00D1A4H
00D1A8H
00D1ACH
00D1B0H
00D1B4H
00D1B8H
+0
+1
+2
+3
Block
OSID11[R] W
-------- -------- 00----00 00000000
OSID12[R] W
-------- -------- 00----00 00000000
OSID13[R] W
FlexRay
-------- -------- 00----00 00000000
GTU *5
OSID14[R] W
-------- -------- 00----00 00000000
OSID15[R] W
-------- -------- 00----00 00000000
-
Reserved
NMV1[R] W
00000000 00000000 00000000 00000000
NMV2[R] W
FlexRay
00000000 00000000 00000000 00000000
NEM *5
NMV3[R] W
00000000 00000000 00000000 00000000
00D1BCH
|
-
Reserved
00D2FCH
Document Number: 002-04665 Rev *A
Page 113 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D300H
00D304H
00D308H
00D30CH
00D310H
00D314H
00D318H
00D31CH
00D320H
00D324H
00D328H
00D32CH
00D330H
00D334H
00D338H
00D33CH
00D340H
00D344H
00D348H
00D34CH
+0
+1
+2
+3
Block
MRC[R/W] W
-----001 10000000 00000000 00000000
FRF[R/W] W
-------1 10000000 ---00000 00000000
FRFM[R/W] W
-------- -------- ---00000 000000-FCL[R/W] W
-------- -------- -------- 10000000
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
LDTS[R] W
-----000 00000000 -----000 00000000
FSR[R] W
-------- -------- 00000000 -----000
MHDF[R/W] W
-------- -------- -------0 00000000
TXRQ1[R] W
00000000 00000000 00000000 00000000
TXRQ2[R] W
00000000 00000000 00000000 00000000
FlexRay
TXRQ3[R] W
MHD *5
00000000 00000000 00000000 00000000
TXRQ4[R] W
00000000 00000000 00000000 00000000
NDAT1[R] W
00000000 00000000 00000000 00000000
NDAT2[R] W
00000000 00000000 00000000 00000000
NDAT3[R] W
00000000 00000000 00000000 00000000
NDAT4[R] W
00000000 00000000 00000000 00000000
MBSC1[R] W
00000000 00000000 00000000 00000000
MBSC2[R] W
00000000 00000000 00000000 00000000
MBSC3[R] W
00000000 00000000 00000000 00000000
MBSC4[R] W
00000000 00000000 00000000 00000000
00D350H
|
-
Reserved
00D3ECH
Document Number: 002-04665 Rev *A
Page 114 of 175
MB91580M/S Series
Address offset value/Register name
Address
00D3F0H
00D3F4H
+0
+1
+2
Block
+3
CREL[R] W
00010000 00111001 00000010 00000110
FlexRay
ENDN[R] W
GIF *5
10000111 01100101 01000011 00100001
00D3F8H
|
-
Reserved
00D3FCH
00D400H
|
00D4FCH
00D500H
00D504H
00D508H
00D50CH
00D510H
00D514H
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
WRHS2[R/W] W
-------- -0000000 -----000 00000000
FlexRay
WRHS3[R/W] W
IBF *5
-------- -------- -----000 00000000
IBCM[R/W] W
-------- ------00 -------- -----000
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D518H
|
-
Reserved
00D5FCH
00D600H
|
00D6FCH
00D700H
00D704H
00D708H
00D70CH
00D710H
00D714H
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
RDHS1[R] W
--000000 -0000000 -----000 00000000
RDHS2[R] W
-0000000 -0000000 -----000 00000000
RDHS3[R] W
--000000 --000000 -----000 00000000
FlexRay
OBF *5
MBS[R] W
--000000 --000000 00-00000 00000000
OBCM[R/W] W
-------- ------00 -------- ------00
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D718H
|
-
Reserved
00D7FCH
Document Number: 002-04665 Rev *A
Page 115 of 175
MB91580M/S Series
Address offset value/Register name
Address
+0
+1
+2
+3
Block
00D800H
|
-
Reserved
-
Reserved [S]
00EFFCH
00F000H
|
00FEFCH
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
-
-
OCDU [S]
-
-
Reserved [S]
00FF04H
|
-
-
00FF0CH
00FF10H
00FF14H
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18H
|
-
-
-
-
Reserved [S]
00FFF4H
00FFF8H
00FFFCH
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDIR0[R] B,H,W
OCDU [S]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]:
It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
*5:
For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ has corresponding
functions.
The following registers are reserved registers for models without the FlexRay function.
000125H IRPR2L[5:4], 000E68H, 0004E8H-0004EFH, 00D000H-00D717H
Document Number: 002-04665 Rev *A
Page 116 of 175
MB91580M/S Series
10. Interrupt Vector Table
MB91F583AM/F584AM/F585AM
Interrupt number
Interrupt factor
Decimal
Inter
rupt Offset
Hexa
decimal level
TBR default
address
RN
Interrupt
request
batch read
target
*1
Reset
System reserved
System reserved
System reserved
System reserved
FPU exception
Instruction access protection violation
exception
Data access protection violation exception
Data access error interrupts
INTE instruction
Instruction break
System reserved
System reserved
System reserved
Exception of invalid instruction
NMI request
Error generation at internal bus diagnosis
RAM double-bit error
Backup RAM double-bit error
0
1
2
3
4
5
00
01
02
03
04
05
-
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
-
-
6
06
-
3E4H
000FFFE4H
-
-
7
8
9
10
11
12
13
14
07
08
09
0A
0B
0C
0D
0E
-
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
-
-
15
0F
15(FH
)
3C0H
Fixed
000FFFC0H
-
External interrupt 0-7
16
10
000FFFBCH
0
-
Reload timer 0 / 1
17
11
000FFFB8H
1
Reload timer 2 / 3
18
12
000FFFB4H
2
19
13
ICR0
3B0H
3
000FFFB0H
3*2
20
14
ICR0
3ACH
4
000FFFACH
4
-
21
15
ICR0
3A8H
5
000FFFA8H
5*2
22
16
ICR0
3A4H
6
000FFFA4H
6
-
23
17
ICR0
3A0H
7
000FFFA0H
7*2
24
18
ICR0
39CH
8
000FFF9CH
8
-
25
19
ICR0
398H
9
000FFF98H
9*2
26
1A
000FFF94H
10
-
*4
27
1B
000FFF90H
-
-
*4
28
1C
000FFF8CH
-
-
Multifunction serial interface ch.0
(reception completed)/
Multifunction serial interface ch.0
(status)
Multifunction serial interface ch.0
(transmission completed)
Multifunction serial interface ch.1
(reception completed)/
Multifunction serial interface ch.1
(status)
Multifunction serial interface ch.1
(transmission completed)
Multifunction serial interface ch.2
(reception completed)/
Multifunction serial interface ch.2
(status)
Multifunction serial interface ch.2
(transmission completed)
Multifunction serial interface ch.3
(reception completed)/
Multifunction serial interface ch.3
(status)
Multifunction serial interface ch.3
(transmission completed)
Document Number: 002-04665 Rev *A
ICR0
3BCH
0
ICR0
3B8H
1
ICR0
3B4H
2
ICR1
394H
0
ICR1
390H
1
ICR1
38CH
2
Page 117 of 175
MB91580M/S Series
Interrupt number
Interrupt factor
Decimal
TBR default
address
RN
Interrupt
request
batch read
target
388H
000FFF88H
-
-
384H
000FFF84H
-
-
380H
000FFF80H
-
-
37CH
000FFF7CH
-
-
378H
000FFF78H
-
-
374H
000FFF74H
-
-
23
ICR1
370H
9
000FFF70H
-
24
ICR2
36CH
0
000FFF6CH
20*3
368H
000FFF68H
-
-
364H
000FFF64H
22
360H
000FFF60H
23
35CH
000FFF5CH
24
ICR2
358H
5
000FFF58H
25
000FFF54H
26
000FFF50H
27
000FFF4CH
28
348H
000FFF48H
29
344H
000FFF44H
30
340H
000FFF40H
-
-
33CH
000FFF3CH
-
-
338H
000FFF38H
33
334H
000FFF34H
34
330H
000FFF30H
35
32CH
000FFF2CH
36
328H
000FFF28H
37
324H
000FFF24H
38
Inter
rupt Offset
Hexa
decimal level
CAN 0
29
1D
CAN 1
30
1E
FlexRay 0 *5
31
1F
FlexRay 1 *5
32
20
FlexRay timer 0 *5
33
21
*5
34
22
FlexRay timer 1
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
35
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
Main timer/PLL timer/
PLL gear for FlexRay*5/
36
PLL alarm for FlexRay*5
Clock calibration unit
37
(CR oscillation)
U/D counter 0 / 1
25
38
26
39
27
40
28
41
29
42
2A
43
2B
44
2C
ICU 0 (fetching) / ICU 1 (fetching)
45
2D
ICU 2 (fetching) / ICU 3 (fetching)
46
2E
*4
47
2F
*4
48
30
OCU 0 (match) / OCU 1 (match)
49
31
OCU 2 (match) / OCU 3 (match)
50
32
OCU 4 (match) / OCU 5 (match)
51
33
OCU 6 (match) / OCU 7 (match)
52
34
OCU 8 (match) / OCU 9 (match)
53
35
OCU 10 (match) / OCU 11 (match)
54
36
Free-run timer 0 (0 detection) /
(compare clear)
Free-run timer 1 (0 detection) /
(compare clear)
Free-run timer 2 (0 detection) /
(compare clear)
PPG 0 / 1 / 2 / 3
Free-run timer 3 (0 detection) /
(compare clear)
Free-run timer 4 (0 detection) /
(compare clear)
Free-run timer 5 (0 detection) /
(compare clear)
PPG 4 / 5
Document Number: 002-04665 Rev *A
ICR1
3
ICR1
4
ICR1
5
ICR1
6
ICR1
7
ICR1
8
ICR2
1
ICR2
2
ICR2
3
ICR2
4
ICR2
354H
6
ICR2
350H
7
ICR2
34CH
8
ICR2
9
ICR3
0
ICR3
1
ICR3
2
ICR3
3
ICR3
4
ICR3
5
ICR3
6
ICR3
7
ICR3
8
*1
Page 118 of 175
MB91580M/S Series
Interrupt number
Interrupt factor
WG dead timer underflow 0 / 1 / 2
WG dead timer reload 0 / 1 / 2
WG DTTI 0
WG dead timer underflow 3 / 4 / 5
WG dead timer reload 3 / 4 / 5
WG DTTI 1
Decimal
Inter
rupt Offset
Hexa
decimal level
TBR default
address
RN
Interrupt
request
batch read
target
*1
55
37
ICR3
320H
9
000FFF20H
39
56
38
ICR4
31CH
0
000FFF1CH
40
AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
57
39
318H
000FFF18H
41
AD converter 8 / 9 / 10 / 11 / 12 / 13 / 14
58
3A
314H
000FFF14H
42
310H
000FFF10H
43
30CH
000FFF0CH
44
308H
000FFF08H
45
304H
000FFF04H
-
300H
000FFF00H
-
-
2FCH
2F8H
2F4H
|
000H
000FFEFCH
000FFEF8H
000FFEF4H
|
000FFC00H
-
-
-
-
AD converter 16 / 17 / 18 / 19 / 20 / 21 / 22
59
/ 23
Base timer 0 IRQ 0/
60
base timer 0 IRQ 1
Base timer 1 IRQ 0/
61
base timer 1 IRQ 1
3B
3C
3D
DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
62
3E
Delay interrupt
63
3F
System reserved
System reserved
64
65
66
|
255
40
41
42
|
FF
Used with the INT instruction.
ICR4
1
ICR4
2
ICR4
3
ICR4
4
ICR4
5
ICR4
6
ICR4
7
-
*1 :Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN
(resource number) is assigned.
2
*2 :The multi-function serial interface status does not support DMA transfer caused by I C reception.
*3 :"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.
*4 :For MB91F583AM/F584AM/F585AM, the interrupt vectors are unused.
*5 :For FlexRay, the MB91F583AMG/F584AMG/F585AMG/F583AMJ/F584AMJ/F585AMJ have corresponding
functions.
Document Number: 002-04665 Rev *A
Page 119 of 175
MB91580M/S Series
MB91F583AS/F584AS/F585AS
Interrupt number
Interrupt factor
Inter
rupt Offset
Hexa
Decimal
decimal level
TBR default
address
*1
RN
Interrupt
request
batch read
target
Reset
0
00
-
3FCH
000FFFFCH
-
-
System reserved
1
01
-
3F8H
000FFFF8H
-
-
System reserved
2
02
-
3F4H
000FFFF4H
-
-
System reserved
3
03
-
3F0H
000FFFF0H
-
-
System reserved
4
04
-
3ECH
000FFFECH
-
-
FPU exception
5
05
-
3E8H
000FFFE8H
-
-
Instruction access protection violation
exception
6
06
-
3E4H
000FFFE4H
-
-
Data access protection violation exception
7
07
-
3E0H
000FFFE0H
-
-
Data access error interrupts
8
08
-
3DCH
000FFFDCH
-
-
INTE instruction
9
09
-
3D8H
000FFFD8H
-
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
-
NMI request
Error generation at internal bus diagnosis
RAM double-bit error
Backup RAM double-bit error
15
0F
15(FH
)
Fixed
3C0H
000FFFC0H
-
External interrupt 0-6
16
10
ICR0
0
3BCH
000FFFBCH
0
-
Reload timer 0 / 1
17
11
ICR0
1
3B8H
000FFFB8H
1
Reload timer 2 / 3
18
12
ICR0
2
3B4H
000FFFB4H
2
Multifunction serial interface ch.0 (reception
completed)/
Multifunction serial interface ch.0
(status)
19
13
ICR0
3
3B0H
000FFFB0H
3*2
Multifunction serial interface ch.0
(transmission completed)
20
14
ICR0
4
3ACH
000FFFACH
4
-
Multifunction serial interface ch.1 (reception
completed)/
Multifunction serial interface ch.1
(status)
21
15
ICR0
5
3A8H
000FFFA8H
5*2
Multifunction serial interface ch.1
(transmission completed)
22
16
ICR0
6
3A4H
000FFFA4H
6
-
*4
23
17
ICR0
7
3A0H
000FFFA0H
-
-
*4
24
18
ICR0
8
39CH
000FFF9CH
-
-
*4
25
19
ICR0
9
398H
000FFF98H
-
-
Document Number: 002-04665 Rev *A
Page 120 of 175
MB91580M/S Series
Interrupt number
Interrupt factor
Inter
rupt Offset
Hexa
Decimal
decimal level
TBR default
address
*1
RN
Interrupt
request
batch read
target
*4
26
1A
ICR1
0
394H
000FFF94H
-
-
*4
27
1B
ICR1
1
390H
000FFF90H
-
-
*4
28
1C
ICR1
2
38CH
000FFF8CH
-
-
CAN 0
29
1D
ICR1
3
388H
000FFF88H
-
-
*4
30
1E
ICR1
4
384H
000FFF84H
-
-
FlexRay 0 *5
31
1F
ICR1
5
380H
000FFF80H
-
-
FlexRay 1 *5
32
20
ICR1
6
37CH
000FFF7CH
-
-
FlexRay timer 0 *5
33
21
ICR1
7
378H
000FFF78H
-
-
FlexRay timer 1 *5
34
22
ICR1
8
374H
000FFF74H
-
-
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization completed
Error generation at Backup RAM diagnosis
35
23
ICR1
9
370H
000FFF70H
-
Main timer/PLL timer/
PLL gear for FlexRay*5/
PLL alarm for FlexRay*5
36
24
ICR2
0
36CH
000FFF6CH
20*3
Clock calibration unit
(CR oscillation)
37
25
ICR2
1
368H
000FFF68H
-
-
U/D counter 0 / 1
38
26
ICR2
2
364H
000FFF64H
22
Free-run timer 0 (0 detection) /
(compare clear)
39
27
ICR2
3
360H
000FFF60H
23
Free-run timer 1 (0 detection) /
(compare clear)
40
28
ICR2
4
35CH
000FFF5CH
24
Free-run timer 2 (0 detection) /
(compare clear)
PPG 0 / 1 / 2 / 3
41
29
ICR2
5
358H
000FFF58H
25
Free-run timer 3 (0 detection) /
(compare clear)
42
2A
ICR2
6
354H
000FFF54H
26
Free-run timer 4 (0 detection) /
(compare clear)
43
2B
ICR2
7
350H
000FFF50H
27
Free-run timer 5 (0 detection) /
(compare clear)
PPG 4 / 5
44
2C
ICR2
8
34CH
000FFF4CH
28
Document Number: 002-04665 Rev *A
Page 121 of 175
MB91580M/S Series
Interrupt number
Interrupt factor
Inter
rupt Offset
Hexa
Decimal
decimal level
TBR default
address
*1
RN
Interrupt
request
batch read
target
ICU 0 (fetching) / ICU 1 (fetching)
45
2D
ICR2
9
348H
000FFF48H
29
ICU 2 (fetching) / ICU 3 (fetching)
46
2E
ICR3
0
344H
000FFF44H
30
*4
47
2F
ICR3
1
340H
000FFF40H
-
-
*4
48
30
ICR3
2
33CH
000FFF3CH
-
-
OCU 0 (match) / OCU 1 (match)
49
31
ICR3
3
338H
000FFF38H
33
OCU 2 (match) / OCU 3 (match)
50
32
ICR3
4
334H
000FFF34H
34
OCU 4 (match) / OCU 5 (match)
51
33
ICR3
5
330H
000FFF30H
35
OCU 6 (match) / OCU 7 (match)
52
34
ICR3
6
32CH
000FFF2CH
36
OCU 8 (match) / OCU 9 (match)
53
35
ICR3
7
328H
000FFF28H
37
OCU 10 (match) / OCU 11 (match)
54
36
ICR3
8
324H
000FFF24H
38
WG dead timer underflow 0 / 1 / 2
WG dead timer reload 0 / 1 / 2
WG DTTI 0
55
37
ICR3
9
320H
000FFF20H
39
WG dead timer underflow 3 / 4 / 5
WG dead timer reload 3 / 4 / 5
WG DTTI 1
56
38
ICR4
0
31CH
000FFF1CH
40
AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
57
39
ICR4
1
318H
000FFF18H
41
AD converter 8 / 9 / 10 / 11 / 12 / 13 / 14
58
3A
ICR4
2
314H
000FFF14H
42
AD converter 19 / 20
59
3B
ICR4
3
310H
000FFF10H
43
Base timer 0 IRQ 0/
base timer 0 IRQ 1
60
3C
ICR4
4
30CH
000FFF0CH
44
Base timer 1 IRQ 0/
base timer 1 IRQ 1
61
3D
ICR4
5
308H
000FFF08H
45
DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
62
3E
ICR4
6
304H
000FFF04H
-
Delay interrupt
63
3F
ICR4
7
300H
000FFF00H
-
-
System reserved
64
40
-
2FCH
000FFEFCH
-
-
System reserved
65
41
-
2F8H
000FFEF8H
-
-
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
-
Document Number: 002-04665 Rev *A
Page 122 of 175
MB91580M/S Series
*1 :Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN
(resource number) is assigned.
2
*2 :The multi-function serial interface status does not support DMA transfer caused by I C reception.
*3 :"PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.
*4 :For MB91F583AS/F584AS/F585AS, the interrupt vectors are unused.
*5 :For FlexRay, the MB91F583ASG/F584ASG/F585ASG/F583ASJ/F584ASJ/F585ASJ have corresponding functions
Document Number: 002-04665 Rev *A
Page 123 of 175
MB91580M/S Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Min
Power supply voltage *1, *2
*1 ,*2
Analog power supply voltage
*1
Analog reference voltage
*1
Remarks
Max
VCC
VSS-0.3
VSS+6.0
V
AVCC
VSS-0.3
VSS+6.0
V
Avcc ≤ Vcc
AVRH
VSS-0.3
VSS+6.0
V
AVRH ≤ AVCC
Input voltage
VI
VSS-0.3
VCC+0.3
V
Analog pin input voltage*1
VIA
VSS-0.3
VCC+0.3
V
Output voltage
VO
VSS-0.3
VCC+0.3
V
Maximum clamp current
ICLAMP
-
4
mA
*9
Total maximum clamp current
Σ|ICLAMP |
-
20
mA
*9
IOL1
-
7
mA
When setting to 2mA*6
IOL2
-
14
mA
When setting to 4mA *7
IOL3
-
17.5
mA
When setting to 5mA *8
IOLAV1
-
2
mA
When setting to 2mA *6
IOLAV2
-
4
mA
When setting to 4mA *7
IOLAV3
-
5
mA
When setting to 5mA *8
ΣIOL
-
50
mA
*6
IOH1
-
-7
mA
When setting to 2mA *6
"H" level maximum output current*3 IOH2
-
-14
mA
When setting to 4mA *7
IOH3
-
-17.5
mA
When setting to 5mA *8
IOHAV1
-
-2
mA
When setting to 2mA *6
IOHAV2
-
-4
mA
When setting to 4mA *7
IOHAV3
-
-5
mA
When setting to 5mA *8
"H" level total output current*5
ΣIOH
-
-50
mA
*6
Power consumption
PD
-
690
mW
Operating temperature
TA
-40
+125
°C
Storage temperature
Tstg
-55
+150
°C
*1
"L" level maximum output current*3
"L" level average output current*4
"L" level total output current*5
"H" level average output current*4
*10, *11
*1: These parameters are based on the condition that VSS=AVSS =0.0V.
*2: Caution must be taken that AVCC does not exceed VCC.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Corresponding pins: General-purpose ports
*7: Corresponding pins: General-purpose ports of P021 to P023, P025 to P027
*8: Corresponding pins: General-purpose ports other than those of P021 to P023, P025 to P027
Document Number: 002-04665 Rev *A
Page 124 of 175
MB91580M/S Series
*9: • Corresponding pins: General-purpose ports
• Use the devices within recommended operating conditions.
• Use the devices with direct voltage (current).
• The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
• Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the + B
input potential can increase the potential at the Vcc pin via a protective diode, possibly affecting other devices.
• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied
through the pin, the microcontroller may operate incompletely.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset
may not function in the power supply voltage.
• Do not leave + B input pins open.
Sample recommended circuit
MB91580M/S series
Protective diode
Limiting resistor
current
+B input (12 to 16V)
*10: To use this product at TA=125°C, equip this on a multilayer board with four or more layers.
To equip this on a single-layer board, change the operating conditions (operating frequency, power supply voltage,
etc) to use this at the power consumption PD=415mW or lower, or use this at TA=105°C or lower.
*11: When it is used exceeding TA=125°C, contact your sales representative.
WARNING
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage,
current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-04665 Rev *A
Page 125 of 175
MB91580M/S Series
11.2 Recommended Operating Conditions
(VSS= AVSS=0.0V)
Value
Parameter
Symbol
Unit
Min
Remarks
Max
VCC
4.5
5.5
V
AVCC
4.5
5.5
V
VCC
3.7
5.5
V
AVCC
3.7
5.5
V
Smoothing capacitor
CS
4.7
(tolerance within ±50%)
µF
Use a ceramic capacitor or a capacitor that has
the similar frequency characteristics.
Use a capacitor with a capacitance greater than
CS as the smoothing capacitor on the VCC pin.
Operating
temperature
TA
-40
°C
*2
Recommended operation guarantee range
Power supply voltage
*1
Operation guarantee range
+125
*1: For connection of smoothing capacitor CS, see the figure below.
*2: When it is used exceeding TA=125°C, contact your sales representative.
C Pin Connection Diagram
C
CS
VS S
AVS S
WARNING
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under any
conditions other than these conditions may adversely affect reliability of device and could result in device failure. No
warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If
you are considering application under any conditions other than listed herein, please contact sales representatives
beforehand.
Document Number: 002-04665 Rev *A
Page 126 of 175
MB91580M/S Series
11.3 DC Characteristics
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Max
When CMOS
schmitt input
0.7 × VCC
level is selected
-
VCC+0.3
V
When
Automotive
input level is
selected
0.8 × VCC
-
VCC+0.3
V
P025 to P027
When FlexRay
input level is
selected
0.7 × VCC
-
VCC+0.3
V
VIH4
RSTX, NMIX
-
0.7 × VCC
-
VCC+0.3
V
VIH5
MD0, MD1
-
0.7 × VCC
-
VCC+0.3
V
VIH6
DEBUGIF
-
2.0
-
VCC+0.3
V
Remarks
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
VIH1
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P000 to P007*,
P010 to P017,
P020 to P027,
"H" level input
voltage
P030 to P037,
P040 to P047,
P050 to P056,
VIH2
*
P060 to P066 ,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
VIH3
P021 to P023,
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 127 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Remarks
Max
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
When CMOS
schmitt input
Vss-0.3
level is selected
-
0.3 × VCC
V
When
Automotive
input level is
selected
Vss-0.3
-
0.5 × VCC
V
P025 to P027
When FlexRay
input level is
selected
Vss-0.3
-
0.3 × VCC
V
VIL4
RSTX, NMIX
-
Vss-0.3
-
0.3 × VCC
V
VIL5
MD0, MD1
-
Vss-0.3
-
0.3 × VCC
V
VIL6
DEBUGIF
-
Vss-0.3
-
0.8
V
VIL1
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P000 to P007*,
P010 to P017,
P020 to P027,
"L" level input
voltage
P030 to P037,
P040 to P047,
P050 to P056,
VIL2
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
VIL3
P021 to P023,
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 128 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%,VSS= AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Remarks
Max
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
VOH1
P060 to P066*,
P070 to P072,
Vcc=4.5V
IOH=-2.0mA
Vcc-0.5
-
Vcc
V
Vcc-0.5
-
Vcc
V
Vcc-0.5
-
Vcc
V
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
"H" level output
voltage
VOH2
P021 to P023,
Vcc=4.5V
P025 to P027
IOH=-4.0mA
When
FlexRay is
selected
P000 to P007*,
P010 to P017,
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
VOH3
P060 to P066*,
P070 to P072,
Vcc=4.5V
IOH=-5.0mA
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 129 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Remarks
Max
P000 to P007*,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
P050 to P056,
VOL1
P060 to P066*,
P070 to P072,
Vcc=4.5V
IOL=2.0mA
0
-
0.4
V
0
-
0.4
V
0
-
0.4
V
0
-
0.4
V
0
-
0.25
V
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
VOL2
P021 to P023,
Vcc=4.5V
P025 to P027
IOL=4.0mA
When FlexRay is
selected
P000 to P007*,
P010 to P017,
"L" level output
voltage
P020, P024,
P030 to P037,
P040 to P047,
P050 to P056,
VOL3
P060 to P066*,
P070 to P072,
Vcc=4.5V
IOL=5.0mA
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
P040, P041,
VOL4
P063*, P064*,
Vcc=4.5V
P080*, P081*,
IOL=3.0mA
I2C shared pin
(when I2C is
selected)
P083*,P084*
VOL5
DEBUGIF
Vcc=2.7V
IOL=25.0mA
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 130 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Input Leak
Current
IIL
All input pins
RUP1
RSTX, NMIX
Vcc= AVCC=5.5V
Typ
-5
-
+5
µA
-
25
-
100
kΩ
When pull-up
resistance is
selected
25
-
100
kΩ
-
-
5
15
pF
VSS < VI < VCC
Remarks
Max
*
P000 to P007 ,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P047,
Pull-up
resistance
P050 to P056,
RUP2
P060 to P066*,
P070 to P072,
P080 to P087*,
P090 to P092*,
P093, P094,
P095 to P097*,
P100 to P102*
Input Capacitor
CIN
Other thanVCC,
VSS, AVCC,
AVSS,
C
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 131 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter
Symbol
Pin
name
Value
Conditions
Unit
Min
Normal
operations
Typ
Remarks
Max
-
80
110
mA
FlexRay =ON
-
73
103
mA
FlexRay =OFF
-
77
107
mA
FlexRay =ON
-
70
100
mA
FlexRay =OFF
-
62
89
mA
FlexRay =ON
-
57
85
mA
FlexRay =OFF
-
61
88
mA
FlexRay =ON
-
56
84
mA
FlexRay =OFF
-
95
125
mA
*
-
95
125
mA
*
FCP=128MHz,
FCPM=128MHz,
FCPP=32MHz
Normal
operations
FCP=128MHz,
FCPM=32MHz,
FCPP=32MHz
Normal
operations
FCP=80MHz,
Power supply
current
FCPM=80MHz,
ICC
VCC5
FCPP=40MHz
Normal
operations
FCP=80MHz,
FCPM=40MHz,
FCPP=40MHz
Flash write
FCP=128MHz,
FCPM=128MHz,
FCPP=32MHz
Flash erase
FCP=128MHz,
FCPM=128MHz,
FCPP=32MHz
*: This series has 2 types of flash; main flash and WorkFlash; however, this is the specification when only one of those
is written/erased.
Document Number: 002-04665 Rev *A
Page 132 of 175
MB91580M/S Series
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AVSS=0.0V)
Parameter
Symbol
Pin
name
Value
Conditions
Unit
Min
Typ
Remarks
Max
CPU sleep
FCP=128MHz,
FCPm=128MHz,
FCPP=32MHz
ICCS
-
41
66
mA
*1, *2 ,*3, *4
-
19
45
mA
*1, *2 ,*3 ,*4
-
1.2
1.8
mA
-
2.7
3.3
mA
-
0.3
0.4
mA
-
1.8
1.9
mA
-
0.7
0.8
mA
-
2.2
2.3
mA
-
0.6
1.1
mA
TA=25°C, *1 ,*2
-
1.0
1.6
mA
TA=25°C, *3 ,*4
-
0.1
0.2
mA
TA=25°C, *1, *2
-
0.5
0.6
mA
TA=25°C, *3, *4
Bus sleep
FCP=128MHz,
FCPm=128MHz,
FCPP=32MHz
ICCBS
When using external clock*5
Clock mode
4MHz source
oscillation
ICCT
TA=25°C, *1, *2 ,*3 ,*4
When using crystal
TA=25°C, *1, *2, *3, *4
When using external clock*5
Power supply
current
VCC5
TA=25°C, *1, *2
When using crystal
ICCTS
Clock mode
shutdown
4MHz source
oscillation
TA=25°C, *1, *2
When using external clock*5
TA=25°C, *3, *4
When using crystal
ICCH
ICCHS
TA=25°C, *3 ,*4
STOP mode
STOP mode
shutdown
*1:MB91F583AMG/F584AMG/F585AMG/F583AMH/F584AMH/F585AMH
*2:MB91F583ASG/F584ASG/F585ASG/F583ASH/F584ASH/F585ASH
*3:MB91F583AMJ/F584AMJ/F585AMJ/F583AMK/F584AMK/F585AMK
*4:MB91F583ASJ/F584ASJ/F585ASJ/F583ASK/F584ASK/F585ASK
*5: The power supply current is the current value when the external clock is supplied from the X1 pin. Note that
the power supply current value when using the external clock is different from that using the oscillator.
Document Number: 002-04665 Rev *A
Page 133 of 175
MB91580M/S Series
11.4 AC Characteristics
11.4.1
Main Clock Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Parameter
Value
Pin
name
Symbol
Conditions
Unit
Min
Typ
Remarks
Max
Source oscillation clock
frequency
FC
X0, X1
-
4
-
20
MHz
Source oscillation clock
cycle time
tCYL
X0, X1
-
50
-
250
ns
FCP
-
-
-
-
128
MHz
CPU clock
FCPP
-
-
-
-
40
MHz
Peripheral bus clock
FCPM
-
-
-
-
128
MHz
Motor clock
tCP
-
-
7.82
-
-
ns
CPU clock
tCPP
-
-
25
-
-
ns
Peripheral bus clock
Motor clock
Internal operating clock
frequency*
Internal operating clock
cycle time*
tCPM
-
-
7.82
-
-
ns
CAN PLL jitter
(during lock)
tPJ
-
-
-10
-
+10
ns
Built-in CR oscillation
frequency
FCCR
-
-
50
100
150
kHz
*: The maximum/minimum value is defined when using the main clock and PLL clock.
X0,X1 clock timing
tCYL
X0
Document Number: 002-04665 Rev *A
Page 134 of 175
MB91580M/S Series
CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
t1
t2
t3
tn-1
tn
Ideal clock
Slow
t2
t1
PLL output
t3
tn-1
tn
Fast
Guaranteed operation range
Power supply voltage VCC (V)
Internal operation clock frequency vs. Power supply voltage
MB91F58x recommended
guaranteed operation range
MB91F58x guaranteed
operation range
5.5
4.5
3.7
PLL guaranteed
operation range
2
4
128
Internal operation clock frequency FCP (MHz)
Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less.
Document Number: 002-04665 Rev *A
Page 135 of 175
MB91580M/S Series
Oscillation clock frequency vs. Internal operation clock frequency
Oscillation
clock
frequency
Internal operation clock frequency
PLL clock
Main
Multipli Multipli Multipli Multipli
Multiplied
Multiplied
clock
...
...
ed by 1 ed by 2 ed by 3 ed by 4
by 20
by 32
4MH 2MH
4MHz
z
z
8MHz
12MHz 16MHz ...
80MHz
...
128MHz
Example of oscillation circuit
X0
X1
4MHz
C1=12pF
R=330Ω
C2=12pF
Note: If it is impossible to start the oscillation within or equal to 20ms when starting from the
oscillation stop state, the clock supervisor performs a detection of oscillation stop and moves
to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.
In addition, when configuring the oscillator circuit, it is recommended to ask matching
evaluation of the circuit to oscillator manufacturers for the design.
Document Number: 002-04665 Rev *A
Page 136 of 175
MB91580M/S Series
AC characteristics are specified by the following measurement reference voltage values.
Input Signal Waveform
Output Signal Waveform
Hysteresis Input Pin (Automotive)
Output Pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis Input Pin (CMOS schmitt)
0.7Vcc
0.3Vcc
Hysteresis Input Pin (FlexRay)
0.65Vcc
0.35Vcc
11.4.2
Reset input
(TA: Recommended operating conditions, Vcc =5.0V±10%, Vss=AVss=0.0V)
Parameter
Symbol
Value
Pin
name
Conditions
Reset input time
tRSTL
RSTX
Reset input removal
width
Unit
Min
-
Remarks
Max
10
-
µs
During normal
operation
Oscillation time of
oscillator*
+0.1
-
ms
At Stop mode
100
-
µs
At Clock mode
1
-
µs
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For crystal
oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several
hundred µs and several ms, and for an external clock, the time is 0 ms.
tRSTL
RSTX
0.2Vcc
Document Number: 002-04665 Rev *A
0.2Vcc
Page 137 of 175
MB91580M/S Series
In Stop mode
tRSTL
RSTX
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction
execution
Internal reset
11.4.3
Power-on Conditions
(TA: Recommended operating conditions, VSS=0.0V)
Parameter
Value
Pin
name
Symbol
Conditions
Unit
Min
Typ
Max
Remarks
Level detection
voltage
-
VCC5
-
2.024
2.200
2.376
V
When turning on
power
Level detection
hysteresis width
-
VCC5
-
-
100
-
mV
During voltage
drop
Level detection
time
-
-
-
-
-
30
μs
*1
Slope detection
undetected
standard
-
VCC5
VCC=level detection
release level
-
-
4
mV/μs
*2
Power off time
tOFF
VCC5
-
50
-
-
ms
*3
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope detection.
This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
Document Number: 002-04665 Rev *A
Page 138 of 175
MB91580M/S Series
11.4.4
Multi-function Serial
CSIO timing (SMR:MD2-0="010"b)
Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock cycle time
SCK ↓ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↑
setup time
tSCYC
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
tSLOVI
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
tSHIXI
Serial clock "H"pulse
width
tSHSL
Serial clock "L"pulse
width
tSLSH
delay time
Valid SIN ⇒ SCK ↑
setup time
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Master mode
CL=50pF
tIVSHI
SCK ↑ ⇒ Valid SIN hold
time
SCK ↓ ⇒ SOT
Remarks
Max
tSLOVE
tIVSHE
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*, SIN1,
SIN2*, SIN3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
*
SCK0_0, SCK0_1 ,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*, SIN1,
SIN2*, SIN3*
Slave mode
CL=50pF
SCK ↑ ⇒ Valid SIN hold
time
tSHIXE
SCK fall time
tF
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
SCK rise time
tR
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 139 of 175
MB91580M/S Series
tSCYC
VOH
SCK
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
Master Mode
tSLSH
SCK
tSHSL
VIH
VIH
VIL
VIL
tF
VIH
tR
tSLOVE
SOT
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave Mode
Document Number: 002-04665 Rev *A
Page 140 of 175
MB91580M/S Series
Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock cycle time
SCK ↑ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↓
setup time
tSCYC
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
tSHOVI
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
tSLIXI
Serial clock "H"pulse
width
tSHSL
Serial clock "L"pulse
width
tSLSH
tSHOVE
delay time
Valid SIN ⇒ SCK ↓
setup time
4tCPP
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Master mode
CL=50pF
tIVSLI
SCK ↓ ⇒ Valid SIN hold
time
SCK ↑ ⇒ SOT
Remarks
Max
tIVSLE
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SIN1, SIN2*, SIN3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
*
SCK0_0, SCK0_1 ,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SIN1, SIN2*, SIN3*
Slave mode
CL=50pF
SCK ↓ ⇒ Valid SIN hold
time
tSLIXE
SCK fall time
tF
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
SCK rise time
tR
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 141 of 175
MB91580M/S Series
tSCYC
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
SIN
VIH
VIL
VIL
Master Mode
tSLSH
tSHSL
SCK
VIH
VIH
VIL
tR
tF
VIL
VIL
tSHOVE
SOT
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave Mode
Document Number: 002-04665 Rev *A
Page 142 of 175
MB91580M/S Series
SPI compatible (SCR:SPI=1) and serial clock output signal detect level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10% , VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock cycle time
SCK ↑ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↓
setup time
SCK ↓ ⇒ Valid SIN
hold time
SOT ⇒ SCK ↓
delay time
tSCYC
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
4tCPP
-
ns
tSHOVI
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
-30
+30
ns
30
-
ns
0
-
ns
2tCPP-30
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
tIVSLI
tSLIXI
tSOVLI
Serial clock "H"pulse
width
tSHSL
Serial clock "L"pulse
width
tSLSH
SCK ↑ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↓
setup time
SCK ↓ ⇒ Valid SIN
hold time
tSHOVE
Master mode
SCK0_0, SCK0_1*,
*
*
SCK1, SCK2 , SCK3 , CL=50pF
SIN0_0, SIN0_1*,
SIN1, SIN2*, SIN3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
Remarks
Max
Slave mode
tIVSLE
tSLIXE
*
CL=50pF
SCK0_0, SCK0_1 ,
SCK1, SCK2*, SCK3*,
*
SIN0_0, SIN0_1 ,
SIN1, SIN2*, SIN3*
SCK fall time
tF
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
SCK rise time
tR
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
-
5
ns
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 143 of 175
MB91580M/S Series
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
Master Mode
tSHSL
tSLSH
VIH
VIH
VIH
SCK
VIL
tF
VIL
tR
VIL
tSHOVE
*
SOT
VOH
VOL
VOH
VOL
tIVSLE
SIN
tSLIXE
VIH
VIH
VIL
VIL
*: Changes when writing to TDR register
Slave Mode
Document Number: 002-04665 Rev *A
Page 144 of 175
MB91580M/S Series
SPI compatible (SCR:SPI=1) and serial clock output signal detect level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock cycle time
SCK ↓ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↑
setup time
SCK ↑ ⇒ Valid SIN
hold time
SOT ⇒ SCK ↑
delay time
tSCYC
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
4tCPP
-
ns
tSLOVI
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
-30
+30
ns
30
-
ns
0
-
ns
2tCPP-30
-
ns
tCPP+10
-
ns
2tCPP-10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
tIVSHI
tSHIXI
tSOVHI
Serial clock
"H" pulse width
tSHSL
Serial clock
"L" pulse width
tSLSH
SCK ↓ ⇒ SOT
delay time
Valid SIN ⇒ SCK ↑
setup time
SCK ↑ ⇒ Valid SIN
hold time
SCK fall time
tSLOVE
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SIN1, SIN2*, SIN3*
CL=50pF
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SOT0_0, SOT0_1*,
SOT1, SOT2*, SOT3*
tSHIXE
SCK0_0, SCK0_1*,
SCK1, SCK2*, SCK3*,
SIN0_0, SIN0_1*,
SIN1, SIN2*, SIN3*
tF
SCK0_0, SCK0_1*,
SCK1, SCK2*,
tIVSHE
Master mode
Remarks
Max
Slave mode
CL=50pF
SCK3*
SCK rise time
tR
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
*: Only available with MB91F583AM/F584AM/F585AM
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 145 of 175
MB91580M/S Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tIVSHI
tSHIXI
VIH
VIL
SIN
VIH
VIL
Master Mode
tSHSL
VIH
SCK
VIL
tR
tSLSH
VIH
tF
*
SOT
VOH
VOL
tSLOVE
VOH
VOL
tIVSHE
SIN
VIH
VIL
VIL
tSHIXE
VIH
VIL
VIH
VIL
*: Changes when writing to TDR register
Slave Mode
Document Number: 002-04665 Rev *A
Page 146 of 175
MB91580M/S Series
When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "H" (SMR:SCINV=0)
Serial chip select inactive level "H" (SCSCR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
SCS ↓ ⇒ SCK ↓
setup time
SCK ↑ ⇒ SCS ↑
hold time
SCS deselect time
SCS ↓ ⇒ SCK ↓
setup time
SCK ↑ ⇒ SCS ↑
hold time
SCS deselect time
SCS ↓ ⇒ SOT
delay time
SCS ↑ ⇒ SOT
delay time
tCSSI
SCK1, SCK2*4,
SCS1, SCS2*4,
Master mode
tCSHI
SCS3*4
CL=50pF
tCSDI
SCS1, SCS2*4, SCS3*4
tCSSE
*1
tCSSU +50
*1
ns
tCSHD -50
*2
tCSHD +0
*2
ns
-50+5tCPP
*3
+tCSDS
+50+5tCPP
*3
+tCSDS
ns
3tCPP+30
-
ns
0
-
ns
3tCPP+30
-
ns
-
40
ns
0
-
ns
tCSSU +0
SCK3*4,
SCK1, SCK2*4,
SCK3*4,
Remarks
Max
SCS1, SCS2*4,
tCSHE
SCS3*4
tCSDE
SCS1, SCS2*4, SCS3*4
Slave mode
CL=50pF
*4
tDSE
SCS1, SCS2 ,
SCS3*4,
SOT1, SOT2*4,
tDEE
SOT3*4
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 147 of 175
MB91580M/S Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tCSDE
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
Document Number: 002-04665 Rev *A
Page 148 of 175
MB91580M/S Series
When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR:SCINV=1)
Serial chip select inactive level "H" (SCSCR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
SCS ↓ ⇒ SCK ↑
setup time
SCK ↓ ⇒ SCS ↑
hold time
SCS deselect time
SCS ↓ ⇒ SCK ↑
setup time
SCK ↓ ⇒ SCS ↑
hold time
SCS deselect time
SCS ↓ ⇒ SOT
delay time
SCS ↑ ⇒ SOT
delay time
tCSSI
tCSHI
tCSDI
tCSSE
SCK1, SCK2*4,
*1
tCSSU +50
*1
ns
tCSHD -50
*2
tCSHD +0
*2
ns
-50+5tCPP
*3
+tCSDS
+50+5tCPP
*3
+tCSDS
ns
3tCPP+30
-
ns
0
-
ns
3tCPP+30
-
ns
-
40
ns
0
-
ns
tCSSU +0
SCK3*4,
SCS1, SCS2*4,
Master mode
SCS3*4
CL=50pF
SCS1, SCS2*4,
SCS3*4
SCK1, SCK2*4,
SCK3*4,
Remarks
Max
SCS1, SCS2*4,
tCSHE
SCS3*4
tCSDE
SCS1, SCS2*4,
SCS3*4
tDSE
SCS1, SCS2*4,
SCS3*4,
Slave mode
CL=50pF
SOT1, SOT2*4,
tDEE
SOT3*4
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 149 of 175
MB91580M/S Series
SCS output
tCSHI
tCSSI
tCSDI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tCSDE
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
Document Number: 002-04665 Rev *A
Page 150 of 175
MB91580M/S Series
When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "H" (SMR:SCINV=0)
Serial chip select inactive level "L" (SCSCR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
SCS ↑ ⇒ SCK ↓
setup time
SCK ↑ ⇒ SCS ↓
hold time
SCS deselect time
SCS ↑ ⇒ SCK ↓
setup time
SCK ↑ ⇒ SCS ↓
hold time
SCS deselect time
SCS ↑ ⇒ SOT
delay time
SCK1, SCK2*4,
SCS1, SCS2*4,
Master mode
tCSHI
SCS3*4
CL=50pF
tCSDI
SCS1, SCS2*4, SCS3*4
tCSSE
*1
tCSSU +50
*1
ns
tCSHD -50
*2
tCSHD +0
*2
ns
-50+5tCPP
*3
+tCSDS
+50+5tCPP
*3
+tCSDS
ns
3tCPP+30
-
ns
0
-
ns
3tCPP+30
-
ns
-
40
ns
0
-
ns
tCSSU +0
SCK3*4,
SCK1, SCK2*4,
SCK3*4,
SCS1, SCS2*4,
tCSHE
SCS3*4
tCSDE
SCS1, SCS2*4, SCS3*4
tDSE
SCS1, SCS2*4, SCS3*4,
Slave mode
CL=50pF
*4
SCS ↓ ⇒ SOT
delay time
tCSSI
Remarks
Max
SOT1, SOT2 ,
tDEE
SOT3*4
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 151 of 175
MB91580M/S Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
Document Number: 002-04665 Rev *A
Page 152 of 175
MB91580M/S Series
When the serial chip select is used (SCSCR:CSEN=1)
Serial clock output signal detect level "L" (SMR:SCINV=1)
Serial chip select inactive level "L" (SCSCR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
SCS ↑ ⇒ SCK ↑
setup time
SCK ↓ ⇒ SCS ↓
hold time
SCS deselect time
SCS ↑ ⇒ SCK ↑
setup time
SCK ↓ ⇒ SCS ↓
hold time
SCS deselect time
SCS ↑ ⇒ SOT
delay time
SCS ↓ ⇒ SOT
delay time
tCSSI
SCK1, SCK2*4,
SCS1, SCS2*4,
Master mode
tCSHI
SCS3*4
CL=50pF
tCSDI
SCS1, SCS2*4, SCS3*4
tCSSE
*1
tCSSU +50
*1
ns
tCSHD -50
*2
tCSHD +0
*2
ns
-50+5tCPP
*3
+tCSDS
+50+5tCPP
*3
+tCSDS
ns
3tCPP+30
-
ns
0
-
ns
3tCPP+30
-
ns
-
40
ns
0
-
ns
tCSSU +0
SCK3*4,
SCK1, SCK2*4,
SCK3*4,
Remarks
Max
SCS1, SCS2*4,
tCSHE
SCS3*4
tCSDE
SCS1, SCS2*4, SCS3*4
tDSE
SCS1, SCS2*4, SCS3*4,
Slave mode
CL=50pF
*4
SOT1, SOT2 ,
tDEE
SOT3*4
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
*4: Only available with MB91F583AM/F584AM/F585AM
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
Document Number: 002-04665 Rev *A
Page 153 of 175
MB91580M/S Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master Mode
tCSDE
SCS input
tCSHE
tCSSE
SCK input
SOT
(Normal Sync
transfer)
tDEE
tDSE
SOT
(SPI compatible)
Slave Mode
Document Number: 002-04665 Rev *A
Page 154 of 175
MB91580M/S Series
UART (Async Serial Interface) timing (SMR:MD2-0="000"b, "001"b)
When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock
"L" pulse width
Serial clock
"H" pulse width
tSLSH
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
tSHSL
CL=50pF
Remarks
Max
tCPP+10
-
ns
tCPP+10
-
ns
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
*: Only available with MB91F583AM/F584AM/F585AM
tR
tSLSH
VIH
VIH
SCK
tF
tSHSL
VIL
VIH
VIL
VIL
When the external clock is selected
LIN interface (v2.1)( LIN Communication Control Interface (v2.1)) timing (SMR:MD2-0="011"b)
When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Serial clock
"L" pulse width
Serial clock
"H" pulse width
tSLSH
SCK0_0, SCK0_1*,
SCK1, SCK2*,
SCK3*
tSHSL
CL=50pF
Remarks
Max
tCPP+10
-
ns
tCPP+10
-
ns
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
*: Only available with MB91F583AM/F584AM/F585AM
tR
SCK
VIH
VIL
tF
tSHSL
tSLSH
VIH
VIH
VIL
VIL
When the external clock is selected
Document Number: 002-04665 Rev *A
Page 155 of 175
MB91580M/S Series
2
I C timing (SMR:MD2-0="100"b)
(TA: Recommended operating conditions, VCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter
Symbol
Pin name
Standard
mode
Conditions
Min
SCL clock frequency
fSCL
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
Max
High-speed
mode*3
Min
Unit
Remarks
Max
0
100
0
400
kHz
4.0
-
0.6
-
µs
(SCL)
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
"Repeat START
condition" hold time
tHDSTA
SDA ↓ → SCL ↓
(SCL)
SOT0_0,
SOT0_1*5,
SOT2*5, SOT3*5
(SDA)
"L" width for SCL
clock
tLOW
4.7
-
1.3
-
µs
"H" width for SCL
clock
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
tHIGH
(SCL)
4.0
-
0.6
-
µs
4.7
-
0.6
-
µs
"Repeat START
condition" setup time
CL=50pF
tSUSTA
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
"STOP condition"
setup time
R=(VP/IOL) *1
tHDDAT
SCK0_0,
SCK0_1*5,
SCK2*5, SCK3*5
3.45
0
*2
0
250
-
4.0
4.7
(SCL)
tSUDAT
SOT0_0,
SOT0_1*5,
SOT2*5, SOT3*5
0.90
*3
µs
100
-
ns
-
0.6
-
µs
-
1.3
-
µs
-
ns
(SDA)
tSUSTO
SCL ↑ → SDA ↑
Bus free time
between "STOP
condition" and
"START condition"
tBUF
-
Noise filter
tSP
-
2tCPP
-
*4
2tCPP
*4
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. VP
shows that the power supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
2
2
*3: A high-speed mode I C bus device can be used on a standard mode I C bus system as long as the device satisfies
the requirement of "tSUDAT ≥ 250 ns".
2
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the peripheral bus to 8MHz or more when using I C.
*5: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 156 of 175
MB91580M/S Series
SDA
t SUSTA
t SUDAT
t BUF
t LOW
SCL
t HDSTA
11.4.5
t HDDAT
t HIGH
t SP
t HDSTA
t SUSTO
Timer Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Remarks
Max
TIN0 to TIN3,
IN0 to IN3,
FRCK0 to FRCK5,
Input pulse
width
tTIWH,
tTIWL
-
4tCPP
-
ns
-
2tCPP
-
ns
TIOA1, TIOB0, TIOB1
AIN0,AIN1,
BIN0,BIN1,
ZIN0,ZIN1
Timer input timing
TINx
INx
FRCKx
TIOAx,TIOBx
AINx,BINx,ZINx
11.4.6
tTIWH
VIH
t TIWL
VIH
VIL
VIL
Trigger Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10% VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Remarks
Max
*
INT0 to INT6, INT7 ,
Input pulse
width
tTRGH,
ADTG0 to ADTG2,
tTRGL
RX0, RX1 ,
*
5tCPP
-
ns
1
-
µs
-
TRG0, TRG1,
At Stop mode
DTTI0
*: Only available with MB91F583AM/F584AM/F585AM
Document Number: 002-04665 Rev *A
Page 157 of 175
MB91580M/S Series
Trigger input timing
tTRGH
INTx
ADTGx
RXx
TRGx
DTTIx
11.4.7
t TRGL
VIH
VIH
VIL
VIL
NMI Input Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Input pulse width
tNMIL
NMIX
-
4tCPP
Remarks
Max
-
ns
NMIX input timing
t NMIL
NMIX
VIH
VIH
VIL
Document Number: 002-04665 Rev *A
VIL
Page 158 of 175
MB91580M/S Series
11.4.8
Low-voltage Detection (External Low-voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Remarks
Max
Power supply
voltage range
VDP5
VCC5
-
3.7
-
5.5
V
Detection voltage
VDL
VCC5
*1
-8%
3.9
+8%
V
When power supply
voltage falls and
detection level is set
initially
Hysteresis width
VHYS
VCC5
-
-
0.1
-
V
When power supply
voltage rises
Low-voltage
detection time
Td
-
-
-
-
30
μs
Power supply
voltage fluctuation
rate
-
VCC5
-
-2
-
2
V/ms
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the
low-voltage detection time (Td), there is the possibility to generate or release after the power supply voltage has
exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation of the
power supply within the limits of the power supply voltage fluctuation rate.
11.4.9
Low-voltage Detection (Internal Low-voltage Detection)
(TA: Recommended operating conditions, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Typ
Remarks
Max
Power supply
voltage range
VRDP5
-
-
1.1
-
1.3
V
Detection voltage
VRDL
-
*
0.8
0.9
1.0
V
When power supply
voltage falls
Hysteresis width
VRHYS
-
-
-
0.1
-
V
When power supply
voltage rises
Low-voltage
detection time
-
-
-
-
-
30
μs
*: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to generate or
release after the power supply voltage has exceeded the detection voltage range.
Document Number: 002-04665 Rev *A
Page 159 of 175
MB91580M/S Series
11.5
A/D Converter
11.5.1
Electrical Characteristics
(TA: Recommended operating conditions, VCC =5.0V±10%, AVCC=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Unit
Min
Typ
Remarks
Max
Resolution
-
-
-
-
12
bit
Non linearity error
-
-
-4.0
-
+4.0
LSB
Differential linearity
error
-
-
-1.9
-
+1.9
LSB
Zero transition voltage VOT
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
AVRL+
0.5LSB-20
-
AVRL+
0.5LSB+20
mV
Full-scale transition
voltage
VFST
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
AVRH1.5LSB-20
-
AVRH1.5LSB+20
mV
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
Analog port input
current
IAIN
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
-1.0
-
1.0
µA
VAVSS ≤ VAIN
≤VAVCC
Analog input voltage
VAIN
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
AVSS
-
AVRH
V
4.5
-
5.5
V
-
0.0
-
V
-
1.5
2.1
mA
3 units
operating
-
-
25
µA
3 units
operating*2
-
3
6
mA
3 units
operating
-
-
4.8
µA
3 units
operating*2
-
-
4
LSB
Every 1 unit*4
AVRH
AVRH0,
AVRH1
1LSB=
(VFST-VOT)/40
94
Avcc ≥ AVRH
Reference voltage
AVRL
IA
IAH
AVRL0,
AVRL1,
AVCC0,
AVCC1
Power supply current
IR
IRH
Variation between
channels
-
AVRH0,
AVRH1
AN0 to AN14, AN16 to
AN18*3, AN19, AN20,
AN21 to AN23*3
*1: Time for each channel.
*2: The Power supply current (Vcc=AVcc=5.0V) is specified if the A/D converter is not operating and CPU is stopped.
*3: Only available with MB91F583AM/F584AM/F585AM
*4: Unit0
AN0 to AN7
Unit1
AN8 to AN14
Unit2
AN16 to AN23
Document Number: 002-04665 Rev *A
Page 160 of 175
MB91580M/S Series
11.5.2
Definition of Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Linearity error :
Deviation of the actual conversion characteristics from a straight line that connects the zero
transition point ("0000 0000 0000"←→"0000 0000 0001") to the full-scale transition point ("1111
1111 1110"←→"1111 1111 1111").
Differential linearity error:
Deviation of the input voltage from the ideal value that is required to change the output
code by 1LSB.
Linearity error
Differential linearity error
FFF
N+1
Digital output
FFD
VFST
(Actuallymeasured
value)
004
VNT
(Actually-measured value)
Actual conversion
characteristics
003
Digital output
FFE
Ideal characteristics
Actual conversion
characteristics
{1 LSB (N - 1) + VOT}
Actual conversion
characteristics
N
N-1
V(N+1)T
VNT
002
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
N-2
001
Actual conversion
characteristics
VOT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVRH
AVSS
(AVRL)
Analog input
AVRH
VNT - {1LSB×(N-1) + V OT}
[LSB]
1LSB
V(N + 1)T - VNT
Differential linearity error of digital output N =
-1 LSB [LSB]
1LSB
VFST - VOT
1LSB =
[V]
4094
Linearity error of digital output N =
VOT: Voltage at which the digital output changes from "000 H" to "001 H".
VFST: Voltage at which the digital output changes from "FFE H" to "FFF H".
11.5.3
Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient. In this case, it
is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.
Document Number: 002-04665 Rev *A
Page 161 of 175
MB91580M/S Series
Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
12bit A/D
R
1.9kΩ (max)
C
8.3pF (max) (4.5V
Avcc
5.5V)
Note: Listed values must be considered as reference values.
Document Number: 002-04665 Rev *A
Page 162 of 175
MB91580M/S Series
11.6 D/A Converter
(TA: Recommended operating conditions, VCC=AVCC=5.0V±10%, VSS=AVSS=0.0V)
Value
Parameter
Symbol
Pin name
Unit
Min
Typ
Remarks
Max
Resolution
-
-
-
-
10
bit
Differential linearity error
-
-
-4.0
-
+4.0
LSB
When the analog output
voltage is 0.5V to 4.5V
11.7 Flash memory
11.7.1
Electrical Characteristics
Value
Parameter
Unit
Min
Typ
Remarks
Max
8 Kbyte sector*1
-
200
800
ms
-
300
1100
ms
-
400
2000
ms
-
700
3700
ms
8-bit writing time
-
9
288
µs
Excluding overhead time at system level*1
16-bit writing time
-
12
384
µs
Excluding overhead time at system level*1
ECC writing time
-
9
288
µs
Excluding overhead time at system level*1
Sector erase time
Erase cycle*2/
Data retention time
8 Kbyte sector*1
including internal preprogramming time
64 Kbyte sector*1
excluding internal preprogramming time
64 Kbyte sector*1
including internal preprogramming time
Average temperature TA=+85°C *3
1,000 cycles/20 years,
10,000 cycles/10 years,
excluding internal preprogramming time
-
-
-
100,000 cycles/5 years
*1: The guaranteed value for erase up to 100,000 cycles
*2: Number of erase cycles for each sector
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
Document Number: 002-04665 Rev *A
Page 163 of 175
MB91580M/S Series
11.7.2
Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might disappear while writing or erasing, be sure to turn the power off by using an
external low-voltage detection function.
*
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL ), hold Vcc at 2.7V or
more within the duration calculated by the following expression:
*
Td [µs] + (PCLK cycle[µs] × 257) + 50[µs]
*: See "4. AC characteristics (8) Low-voltage detection (External low-voltage detection)."
Document Number: 002-04665 Rev *A
Page 164 of 175
MB91580M/S Series
12. Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
normal operation
(VCC = 5.5V)
100.00
ICC5 [mA]
(1)
(2)
(3)
(4)
(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128MHz, FlexRay=ON
(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=ON
(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=ON
(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=ON
10.00
-50
0
50
100
150
TA [ºC]
normal operation
(VCC = 5.5V)
100.00
ICC5 [mA]
(1)
(2)
(3)
(4)
(1)Fcp=128MHz, Fcpp=32MHz, Fcpm=128MHz, FlexRay=OFF
(2)Fcp=128MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=OFF
(3)Fcp=80MHz, Fcpp=40MHz, Fcpm=80MHz, FlexRay=OFF
(4)Fcp=80MHz, Fcpp=40MHz, Fcpm=40MHz, FlexRay=OFF
10.00
-50
0
50
100
150
TA [ºC]
Document Number: 002-04665 Rev *A
Page 165 of 175
MB91580M/S Series
sleep mode
ICCS5/ICCBS5 [mA]
100.000
(VCC = 5.5V)
CPU Sleep(128MHz)
BUS Sleep (128MHz)
10.000
-50
0
50
100
150
TA [ºC]
Document Number: 002-04665 Rev *A
Page 166 of 175
MB91580M/S Series
Watch mode
(VCC = 5.5V)
10.000
Main osc (4MHz)
ICCT5 [mA]
1.000
External clock (4MHz)
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Stop mode
(VCC = 5.5V)
10.000
ICCH5 [mA]
1.000
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04665 Rev *A
Page 167 of 175
MB91580M/S Series
Watch mode(power off)
1000.00
(VCC = 5.5V)
Main osc (4MHz)
ICCT52 [µA]
100.00
External clock (4MHz)
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
Stop mode(power off)
(VCC = 5.5V)
1000.00
ICCH52 [µA]
100.00
10.00
1.00
0.10
0.01
-50
0
50
100
150
TA [ºC]
Document Number: 002-04665 Rev *A
Page 168 of 175
MB91580M/S Series
13. Ordering Information
Part number
Package*
MB91F583AMGPMC-GTE1
MB91F584AMGPMC-GTE1
MB91F585AMGPMC-GTE1
MB91F583AMHPMC-GTE1
MB91F584AMHPMC-GTE1
MB91F585AMHPMC-GTE1
100-pin plastic LQFP
MB91F583AMJPMC-GTE1
(FPT-100P-M20)
MB91F584AMJPMC-GTE1
MB91F585AMJPMC-GTE1
MB91F583AMKPMC-GTE1
MB91F584AMKPMC-GTE1
MB91F585AMKPMC-GTE1
MB91F583ASGPMC1-GTE1
MB91F584ASGPMC1-GTE1
MB91F585ASGPMC1-GTE1
MB91F583ASHPMC1-GTE1
MB91F584ASHPMC1-GTE1
MB91F585ASHPMC1-GTE1
64-pin plastic LQFP
MB91F583ASJPMC1-GTE1
(FPT-64P-M24)
MB91F584ASJPMC1-GTE1
MB91F585ASJPMC1-GTE1
MB91F583ASKPMC1-GTE1
MB91F584ASKPMC1-GTE1
MB91F585ASKPMC1-GTE1
*: For details of the package, see Package Dimensions
Document Number: 002-04665 Rev *A
Page 169 of 175
MB91580M/S Series
14. Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
"A"
1
25
0.50(.020)
C
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.20 ±0.05
(.008 ±.002)
0.08(.003) M
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
Document Number: 002-04665 Rev *A
0.145±0.055
(.006 ±.002)
0°~8°
0.50 ±0.20
(.020 ±.008)
0.60 ±0.15
(.024 ±.006)
0.10 ±0.10
(.004 ±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 170 of 175
MB91580M/S Series
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
32
49
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
INDEX
0°~8°
17
64
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.20±0.05
0.50(.020)
(.008±.002)
C
0.08(.003)
2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3
Document Number: 002-04665 Rev *A
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 171 of 175
MB91580M/S Series
15. Major Changes
Spansion Publication Number: MB91F585AMG_DS705-00013
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
The product series name should be corrected.
MB91F585MG
MB91F585AMG
MB91F585MH
MB91F585AMH
MB91F585MJ
MB91F585AMJ
MB91F585MK
MB91F585AMK
MB91F584MG
MB91F584AMG
MB91F584MH
MB91F584AMH
MB91F584MJ
MB91F584AMJ
MB91F584MK
MB91F584AMK
MB91F583MG
MB91F583AMG
MB91F583MH
MB91F583AMH
MB91F583MJ
-
-
MB91F583AMJ
→
MB91F583MK
MB91F585SG
MB91F583AMK
MB91F585ASG
MB91F585SH
MB91F585ASH
MB91F585SJ
MB91F585ASJ
MB91F585SK
MB91F585ASK
MB91F584SG
MB91F584ASG
MB91F584SH
MB91F584ASH
MB91F584SJ
MB91F584ASJ
MB91F584SK
MB91F584ASK
MB91F583SG
MB91F583ASG
MB91F583SH
MB91F583ASH
MB91F583SJ
MB91F583ASJ
MB91F583SK
MB91F583ASK
The features of CR oscillation should be corrected.
Oscillation frequency: 100kHz, with frequency accuracy ± 10%
2
↓
Features
Oscillation frequency: 100kHz, with frequency accuracy ± 50%
(pre-trimming)
The specification of "H" level input voltage and "L" level input
voltage of FlexRay should be corrected.
22
I/O Circuit Type
FlexRay input (0.65Vcc/0.35Vcc)
↓
FlexRay input (0.7Vcc/0.3Vcc)
Document Number: 002-04665 Rev *A
Page 172 of 175
MB91580M/S Series
Page
Section
Change Results
The memory map should be corrected.
33
54,85
Memory Map
I/O Map
Address:00150CH
The address of "Reset vector table" and "Interrupt vector table"
should be added
The register name should be corrected.
STMCR00 → STMCR0
I/O Map
54,55,85
Address: 00150 EH, 001510H, 001511H,
001512H,
The registers should be deleted.
SCS CR0,SCSTR30,SCSTR20,SCSTR10,SCSTR00
001513H
The initial values of MHDS should be corrected.
63,92
I/O Map
Address:00D310H
-0000000 -0000000 -0000000 10000000
↓
-0000000 -0000000 -0000000 00000000
The specification of "H" level input voltage of P021-P023,P025-P027
should be corrected.
104
Electrical Characteristics
DC Caharacteristics
Min:0.65 ×Vcc
↓
Min: 0.7 × Vcc
The specification of "L" level input voltage of P021-P023,P025-P027
should be corrected.
105
Electrical Characteristics
DC Caharacteristics
Max: 0.35 × Vcc
↓
Max: 0.3 × Vcc
Electrical Characteristics
111
AC Characteristics
The remarks of "CAN PLL jitter" should be deleted.
Main Clock Timing
The specifications of "The Built-in CR oscillation frequency" should
be corrected.
Electrical Characteristics
111
AC Characteristics
Main Clock Timing
Min: 90kHz,
Max: 110kHz
↓
Min:50kHz
Max:150kHz,
-
-
Company name and layout design change
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04665 Rev *A
Page 173 of 175
MB91580M/S Series
Document History
Document Title: MB91F583AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91F584AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK, MB91F585AMG/AMH/AMJ/AMK/ASG/ASH/ASJ/ASK,
MB91580M/S Series FR81S, 32-bit Microcontroller Datasheet
Document Number: 002-04665
Revision
ECN
Orig. of
Change
Submission
Date
**
−
KOJM
04/18/2014
*A
5139690
KOJM
03/29/2016 Updated to Cypress template
Document Number: 002-04665 Rev *A
Description of Change
Migrated to Cypress and assigned document number 002-04665.
No change to document contents or format.
Page 174 of 175
MB91580M/S Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.
To find the office closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
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cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
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Interface
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/go/interface
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Community | Forums | Blogs | Video | Training
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cypress.com/go/psoc
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cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation 2013-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress").
This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of
the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any
license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have
a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive,
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those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document
without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in
this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed,
intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices
or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses
where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or
system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or
in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from
or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of
Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of
their respective owners.
Document Number: 002-04665 Rev *A
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