POSEICO SPA Via Pillea 42-44, 16153 Genova - ITALY Tel. + 39 010 8599400 - Fax + 39 010 8682006 Sales Office: Tel. + 39 010 8599400 - [email protected] PHASE CONTROL THYRISTOR AT706LT Repetitive voltage up to Mean forward current Surge current 800 V 4767 A 70 kA FINAL SPECIFICATION Feb. 17 - Issue: 1 Symbol Characteristic Conditions Tj [°C] Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 800 V V RSM Non-repetitive peak reverse voltage 125 900 V V DRM Repetitive peak off-state voltage 125 800 V I RRM Repetitive peak reverse current V=VRRM 125 200 mA I DRM Repetitive peak off-state current V=VDRM 125 200 mA I T (AV) Mean forward current 180° sin, 50 Hz, Th=55°C, double side cooled 4767 A I T (AV) Mean forward current 180° sin, 50 Hz, Tc=85°C, double side cooled I TSM Surge forward current CONDUCTING 125 3802 A 70 kA I² t I² t Sine wave, 10 ms without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 125 0,84 V r T On-state slope resistance 125 0,060 mohm 3 24500 x 10 10000 A 125 1,44 A²s V SWITCHING di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 3100 A; gate 10V, 5W 125 320 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 V/µs t d Gate controlled delay time, typical VD=100V; gate source 10V, 10W , tr=.5 µs 25 t q Circuit commutated turn-off time, typical dv/dt = 20 V/µs linear up to 75% VDRM Q rr Reverse recovery charge di/dt = -20 A/µs, I= 2050 A I rr Peak reverse recovery current VR= 50 V I H Holding current, typical VD=5V, gate open circuit 25 300 mA I L Latching current, typical VD=5V, tp=30µs 25 700 mA V GT Gate trigger voltage VD=5V 25 3,50 V I GT Gate trigger current VD=5V 25 250 mA V GD Non-trigger gate voltage, min. VD=VDRM 125 0,25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) 5 V P GM Peak gate power dissipation 150 W P G Average gate power dissipation 2 W R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T j Operating junction temperature 3 160 125 µs µs µC A GATE Pulse width 100 µs MOUNTING F 9,5 °C/kW 2 °C/kW -30 / 125 °C Mounting force 40,0 / 50,0 kN Mass 1150 ORDERING INFORMATION : AT706LT S 08 standard specification VRRM/100 g AT706LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb. 17 - Issue: 1 DISSIPATION CHARACTERISTICS SQUARE WAVE Th [°C] 130 120 110 100 90 80 70 60 50 30° 60° 90° 120° 180° DC 40 0 1000 2000 3000 4000 5000 6000 7000 IT(AV) [A] PF(AV) [W] 8000 DC 180° 7000 120° 60° 6000 90° 30° 5000 4000 3000 2000 1000 0 0 1000 2000 3000 IT(AV) [A] 4000 5000 6000 7000 AT706LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb. 17 - Issue: 1 DISSIPATION CHARACTERISTICS SINE WAVE Th [°C] 130 120 110 100 90 80 70 60 50 30° 60° 90° 120° 180° 40 0 1000 2000 3000 4000 5000 6000 IT(AV) [A] PF(AV) [W] 8000 180° 120° 7000 60° 90° 30° 6000 5000 4000 3000 2000 1000 0 0 1000 2000 3000 IT(AV) [A] 4000 5000 6000 AT706LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION Feb. 17 - Issue: 1 SURGE CHARACTERISTIC Tj = 125 °C 16000 80 14000 70 12000 60 10000 50 ITSM [kA] On-State Current [A] ON-STATE CHARACTERISTIC Tj = 125 °C 8000 6000 40 30 4000 20 2000 10 0 0 0 0,5 1 1,5 2 1 On-State Voltage [V] 10 n° cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 10 9 8 Zth j-h [°C/kW] 7 6 5 4 3 2 1 0 0,001 0,01 0,1 1 t[s] 10 100 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SpA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100