E2G0016-17-41 ¡ Semiconductor MSM512100/L ¡ Semiconductor This version: Jan. 1998 MSM512100/L Previous version: May 1997 2,097,152-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM512100/L is a 2,097,152-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM512100/L achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM512100/L is available in a 26/20-pin plastic SOJ. The MSM512100L (the low-power version) is specially designed for lower-power applications. FEATURES • 2,097,152-word ¥ 1-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM512100/L-xxSJ) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM512100/L-60 60 ns 30 ns 15 ns 15 ns 110 ns 440 mW MSM512100/L-70 70 ns 35 ns 20 ns 20 ns 130 ns 385 mW MSM512100/L-80 80 ns 40 ns 20 ns 20 ns 150 ns 330 mW 5.5 mW/ 0.55 mW (L-version) 1/16 ¡ Semiconductor MSM512100/L PIN CONFIGURATION (TOP VIEW) DIN 1 26 VSS WE 2 25 DOUT RAS 3 24 CAS NC 4 23 OE A10R 5 22 A9 A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 26/20-Pin Plastic SOJ Pin Name A0 - A9, A10R RAS Function Address Input Row Address Strobe CAS Column Address Strobe DIN Data Input DOUT Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection 2/16 ¡ Semiconductor MSM512100/L BLOCK DIAGRAM Timing Generator RAS Timing Generator CAS 10 Column Address Buffers 10 Column Decoders Write Clock Generator WE OE Internal Address Counter A0 - A9 10 A10R 1 Row Address Buffers Refresh Control Clock 11 Row Decoders Word Drivers Sense Amplifiers Memory Cells I/O Selector Input Buffer Output Buffer DOUT DIN VCC On Chip VBB Generator VSS 3/16 ¡ Semiconductor MSM512100/L ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 6 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DOUT) COUT — 7 pF Parameter Input Capacitance (A0 - A9, A10R, DIN) 4/16 ¡ Semiconductor MSM512100/L DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM512100 MSM512100 MSM512100 /L-60 /L-70 /L-80 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 80 — 70 — 60 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 100 — 100 — — 80 — 70 — 5 — — 80 — — 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) DOUT disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V 1 100 mA 1, 5 — 60 mA 1, 2 5 — 5 mA — 70 — 60 mA 1, 2 60 — 50 — 40 mA 1, 3 200 — 200 — 200 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, Supply Current ICC6 (CAS before RAS Refresh) 1 DOUT = enable Average Power RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. Average Power tRC = 125 ms, ICC10 CAS before RAS, Supply Current (Battery Backup) Notes : 1. 2. 3. 4. 5. mA tRAS £ 1 ms 1, 4, 5 ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/16 ¡ Semiconductor MSM512100/L AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter MSM512100 MSM512100 MSM512100 /L-70 /L-80 /L-60 Unit Note Symbol Min. Max. Min. Max. Min. Max. tRC 110 — 130 — 150 — ns tRWC 130 — 155 — 175 — ns tPC 40 — 45 — 50 — ns tPRWC 60 — 70 — 75 — ns Access Time from RAS tRAC — 60 — 70 — 80 ns 4, 5, 6 Access Time from CAS tCAC — 15 — 20 — 20 ns 4, 5 Access Time from Column Address tAA — 30 — 35 — 40 ns 4, 6 Access Time from CAS Precharge tCPA — 35 — 40 — 45 ns 4 Access Time from OE tOEA — 15 — 20 — 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 — 0 — 0 — ns 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 0 15 0 20 0 20 ns 7 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 20 0 20 ns 7 3 Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Transition Time tT 3 50 3 50 3 50 ns Refresh Period tREF — 16 — 16 — 16 ms Refresh Period (L-version) tREF — 128 — 128 — 128 ms RAS Precharge Time tRP 40 — 50 — 60 — ns RAS Pulse Width tRAS 60 10,000 70 10,000 80 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 60 100,000 70 100,000 80 100,000 ns RAS Hold Time tRSH 15 — 20 — 20 — ns RAS Hold Time referenced to OE tROH 15 — 20 — 20 — ns CAS Precharge Time (Fast Page Mode) tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 15 10,000 20 10,000 20 10,000 ns CAS Hold Time tCSH 60 — 70 — 80 — ns CAS to RAS Precharge Time tCRP 5 — 5 — 5 — ns RAS Hold Time from CAS Precharge tRHCP 35 — 40 — 45 — ns RAS to CAS Delay Time tRCD 20 45 20 50 20 60 ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 15 40 ns 6 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 15 — 15 — 15 — ns Column Address Hold Time from RAS tAR 50 — 55 — 60 — ns Column Address to RAS Lead Time tRAL 30 — 35 — 40 — ns 6/16 ¡ Semiconductor MSM512100/L AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM512100 MSM512100 MSM512100 /L-70 /L-80 /L-60 Unit Note Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 9 Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time tWCH 10 — 10 — 10 — ns Write Command Hold Time from RAS tWCR 45 — 50 — 60 — ns Write Command Pulse Width tWP 10 — 10 — 10 — ns OE Command Hold Time tOEH 15 — 20 — 20 — ns Write Command to RAS Lead Time tRWL 15 — 20 — 20 — ns Write Command to CAS Lead Time tCWL 15 — 20 — 20 — ns Data-in Set-up Time tDS 0 — 0 — 0 — ns 10 Data-in Hold Time tDH 15 — 15 — 15 — ns 10 Data-in Hold Time from RAS tDHR 50 — 55 — 60 — ns OE to Data-in Delay Time tOED 15 — 20 — 20 — ns CAS to WE Delay Time tCWD 15 — 20 — 20 — ns 9 Column Address to WE Delay Time tAWD 30 — 35 — 40 — ns 9 RAS to WE Delay Time tRWD 60 — 70 — 80 — ns 9 CAS Precharge WE Delay Time tCPWD 35 — 40 — 45 — ns 9 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) tCSR 5 — 5 — 5 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 10 — 10 — ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 — 10 — 10 — ns WE Hold Time from RAS (CAS before RAS) tWRH 10 — 10 — 10 — ns RAS to WE Set-up Time (Test Mode) tWTS 10 — 10 — 10 — ns RAS to WE Hold Time (Test Mode) tWTH 10 — 10 — 10 — ns 7/16 ¡ Semiconductor Notes: MSM512100/L 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. RA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, the data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/16 E2G0089-17-41B ¡ Semiconductor MSM512100/L TIMING WAVEFORM Read Cycle tRC tCSH tCRP CAS tRP tRAS VIH – RAS VIL – tRCD VIH – VIL – tCRP tRSH tCAS ,, , , ,, tRAD tASR Address VIH – VIL – tRAH tRAL tCAH tASC Row Column tAR tRRH tRCS WE tRCH VIH – VIL – tROH OE tOEA VIH – VIL – tCAC tAA VOH – VOL – tOFF tCLZ tRAC DOUT tOEZ Open Valid Data "H" or "L" Write Cycle (Early Write) tRC tRCD tCRP tRSH tCSH V CAS IH – VIL – tCAS tRAD tRAH tRAL tCAH tASC Row Column tWCR tCWL tWCS tWCH VIH – WE VIL – OE tWP VIH – VIL – tRWL tDHR tDS DIN VIH – VIL – DOUT VOH – VOL – tCRP tAR tASR Address VIH – VIL – tRP tRAS VIH – RAS V – IL tDH Valid Data Open "H" or "L" 9/16 ¡ Semiconductor MSM512100/L Read Modify Write Cycle tRWC tCRP CAS tRP tRAS VIH – RAS V – IL tRSH tRCD tRWL tCRP tCAS VIH – VIL – , , tASR V Address IH – VIL – tRAD tRAH tCSH tAR tASC Row tCWL tRAL tCAH Column tAWD tRWD tCWD WE VIH – VIL – tRCS tOED OE tOEH tOEA VIH – VIL – tOEZ tDS DIN tWP VIH – VIL – tDH Valid Data tCAC tAA tRAC DOUT VOH – VOL – Valid Data Open tCLZ "H" or "L" 10/16 ¡ Semiconductor MSM512100/L Fast Page Mode Read Cycle tRASP VIH – RAS VIL – tRP tRHCP tCSH tRCD tCRP V CAS IH – VIL – tCAS tAR tASC tPC tCAS tCP tRSH tCAS tCP tCRP , , , , tASR Address VIH – VIL – tRAH Row tASC tCAH Column tRAD tCAH Column tRCH Column tRRH tRCH tRCS tRCS tRAL tCAH tASC tRCS tRCH VIH – WE VIL – tOEA tOEA tOEA VIH – OE VIL – tOEZ tOEZ tCAC tCAC tAA tCPA tAA tRAC DOUT VOH – VOL – Valid Data tCLZ tOEZ tCAC tAA tCPA Valid Data tOFF tCLZ Valid Data tOFF tCLZ tOFF "H" or "L" Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH – VIL – tRHCP tCRP CAS VIH – VIL – tASR Address VIH – VIL – WE VIH – VIL – DIN VIH – VIL – tCAS tRCD tRAH tAR tASC Row tCAH Column tRAD tWCR tWCS tPC tCAS tCP Column tASC tCRP tRAL tCAH Column tRWL tCWL tWCH tWCS tDH tDS tWP tDS tCAH tASC tRSH tCAS tCP Valid Data tCWL tWCH tWP tDH Valid Data tWCS tDS tCWL tWCH tWP tDH Valid Data tDHR DOUT VOH – VOL – Open Note: OE = "H" or "L" "H" or "L" 11/16 , ,,, ,,, ¡ Semiconductor MSM512100/L Fast Page Mode Read Modify Write Cycle tRASP RAS VIH – VIL – tRHCP tCSH tRCD CAS VIH – VIL – tASR Address VIH – VIL – tAR tRAH tASC Row tCAH tRWD tCWD VIH – WE VIL – tAWD tAA tRAD tCAC tOEA OE VIH – VIL – tCP tCAH tASC Column tRCS tPRWC tCAS tCP tCAS tCPWD tCWD tCAH tCPA tAA tCAC tDS tCWL tRCS tOEA tOEZ tCPWD tCWD tCWL tRWL tAWD tCPA tAA tCAC tWP tDS tOED tRAL Column tAWD tWP tCRP tCAS tASC Column tCWL tRCS tRP tRSH tOED tOEA tOEZ tWP tDS tOED tOEZ tRAC DOUT VOH – VOL – tCLZ Valid Data tCLZ Valid Data tDH DIN VIH – VIL – Valid Data tCLZ Valid Data tDH Valid Data tDH Valid Data "H" or "L" 12/16 , ,, ¡ Semiconductor MSM512100/L RAS-Only Refresh Cycle tRC tRP tRAS RAS VIH – VIL – tRPC tCRP CAS VIH – VIL – tASR Address VIH – VIL – tRAH Row tOFF DOUT VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRAS RAS VIH – VIL – tRPC tRPC tCP CAS WE tRP tCSR tCHR tWRP tWRH VIH – VIL – tWRP VIH – VIL – tOFF DOUT VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 13/16 ,,, , ,, , ,, ¡ Semiconductor MSM512100/L Hidden Refresh Read Cycle tRC tRAS RAS VIH – VIL – tRCD tCRP CAS VIH – VIL – VIH – VIL – tRSH tRAH tRAL tCAH tASC Row Column tAR tRCS WE VIH – VIL – OE VIH – VIL – tCHR tRAD tASR Address tRAS tRP tRRH tWRP tWRH tROH tOEA tRAC DOUT VOH – VOL – tOEZ tCAC tAA tOFF Valid Data tCLZ "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS VIH – VIL – tRCD tCRP CAS VIH – VIL – tRAD tASR Address VIH – VIL – tRAH Row tRAS tRP tRSH tCHR tAR tRAL tCAH tASC Column tWCR WE VIH – VIL – OE VIH – VIL – tRWL tWCH tWP tWCS VIH – VIL – DOUT VOH – VOL – tWRH tDH tDS DIN tWRP Valid Data tDHR Open "H" or "L" 14/16 , ¡ Semiconductor MSM512100/L Test Mode Initiate Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS tRAS tCSR tWTS WE tCHR VIH – VIL – tWTH VIH – VIL – tOFF DOUT VOH – VOL – Open Note: OE, Address, DIN = "H" or "L" "H" or "L" 15/16 ¡ Semiconductor MSM512100/L PACKAGE DIMENSIONS (Unit : mm) SOJ26/20-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16